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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's ALU                                                ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  ALU                                                         ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_alu.v,v $
// Revision 1.15  2005/01/07 09:23:39  andreje
// l.ff1 and l.cmov instructions added
//
// Revision 1.14  2004/06/08 18:17:36  lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.13  2004/05/09 19:49:03  lampret
// Added some l.cust5 custom instructions as example
//
// Revision 1.12  2004/04/05 08:29:57  lampret
// Merged branch_qmem into main tree.
//
// Revision 1.11  2003/04/24 00:16:07  lampret
// No functional changes. Added defines to disable implementation of multiplier/MAC
//
// Revision 1.10  2002/09/08 05:52:16  lampret
// Added optional l.div/l.divu insns. By default they are disabled.
//
// Revision 1.9  2002/09/07 19:16:10  lampret
// If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY].
//
// Revision 1.8  2002/09/07 05:42:02  lampret
// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
//
// Revision 1.7  2002/09/03 22:28:21  lampret
// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
//
// Revision 1.6  2002/03/29 16:40:10  lampret
// Added a directive to ignore signed division variables that are only used in simulation.
//
// Revision 1.5  2002/03/29 16:33:59  lampret
// Added again just recently removed full_case directive
//
// Revision 1.4  2002/03/29 15:16:53  lampret
// Some of the warnings fixed.
//
// Revision 1.3  2002/01/28 01:15:59  lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.2  2002/01/14 06:18:22  lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10  2001/11/12 01:45:40  lampret
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
//
// Revision 1.9  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8  2001/10/19 23:28:45  lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_alu(
        a, b, mult_mac_result, macrc_op,
        alu_op, shrot_op, comp_op,
        cust5_op, cust5_limm,
        result, flagforw, flag_we,
        cyforw, cy_we, carry, flag
);
 
parameter width = `OR1200_OPERAND_WIDTH;
 
//
// I/O
//
input   [width-1:0]              a;
input   [width-1:0]              b;
input   [width-1:0]              mult_mac_result;
input                           macrc_op;
input   [`OR1200_ALUOP_WIDTH-1:0]        alu_op;
input   [`OR1200_SHROTOP_WIDTH-1:0]      shrot_op;
input   [`OR1200_COMPOP_WIDTH-1:0]       comp_op;
input   [4:0]                    cust5_op;
input   [5:0]                    cust5_limm;
output  [width-1:0]              result;
output                          flagforw;
output                          flag_we;
output                          cyforw;
output                          cy_we;
input                           carry;
input         flag;
 
//
// Internal wires and regs
//
reg     [width-1:0]              result;
reg     [width-1:0]              shifted_rotated;
reg     [width-1:0]              result_cust5;
reg                             flagforw;
reg                             flagcomp;
reg                             flag_we;
reg                             cy_we;
wire    [width-1:0]              comp_a;
wire    [width-1:0]              comp_b;
`ifdef OR1200_IMPL_ALU_COMP1
wire                            a_eq_b;
wire                            a_lt_b;
`endif
wire    [width-1:0]              result_sum;
`ifdef OR1200_IMPL_ADDC
wire    [width-1:0]              result_csum;
wire                            cy_csum;
`endif
wire    [width-1:0]              result_and;
wire                            cy_sum;
reg                             cyforw;
 
//
// Combinatorial logic
//
assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};
assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};
`ifdef OR1200_IMPL_ALU_COMP1
assign a_eq_b = (comp_a == comp_b);
assign a_lt_b = (comp_a < comp_b);
`endif
assign {cy_sum, result_sum} = a + b;
`ifdef OR1200_IMPL_ADDC
assign {cy_csum, result_csum} = a + b + {32'd0, carry};
`endif
assign result_and = a & b;
 
//
// Simulation check for bad ALU behavior
//
`ifdef OR1200_WARNINGS
// synopsys translate_off
always @(result) begin
        if (result === 32'bx)
                $display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);
end
// synopsys translate_on
`endif
 
//
// Central part of the ALU
//
always @(alu_op or a or b or result_sum or result_and or macrc_op or shifted_rotated or mult_mac_result) begin
`ifdef OR1200_CASE_DEFAULT
        casex (alu_op)          // synopsys parallel_case
`else
        casex (alu_op)          // synopsys full_case parallel_case
`endif
    `OR1200_ALUOP_FF1: begin
        result = a[0] ? 1 : a[1] ? 2 : a[2] ? 3 : a[3] ? 4 : a[4] ? 5 : a[5] ? 6 : a[6] ? 7 : a[7] ? 8 : a[8] ? 9 : a[9] ? 10 : a[10] ? 11 : a[11] ? 12 : a[12] ? 13 : a[13] ? 14 : a[14] ? 15 : a[15] ? 16 : a[16] ? 17 : a[17] ? 18 : a[18] ? 19 : a[19] ? 20 : a[20] ? 21 : a[21] ? 22 : a[22] ? 23 : a[23] ? 24 : a[24] ? 25 : a[25] ? 26 : a[26] ? 27 : a[27] ? 28 : a[28] ? 29 : a[29] ? 30 : a[30] ? 31 : a[31] ? 32 : 0;
    end
                `OR1200_ALUOP_CUST5 : begin
                                result = result_cust5;
                end
                `OR1200_ALUOP_SHROT : begin
                                result = shifted_rotated;
                end
                `OR1200_ALUOP_ADD : begin
                                result = result_sum;
                end
`ifdef OR1200_IMPL_ADDC
                `OR1200_ALUOP_ADDC : begin
                                result = result_csum;
                end
`endif
                `OR1200_ALUOP_SUB : begin
                                result = a - b;
                end
                `OR1200_ALUOP_XOR : begin
                                result = a ^ b;
                end
                `OR1200_ALUOP_OR  : begin
                                result = a | b;
                end
                `OR1200_ALUOP_IMM : begin
                                result = b;
                end
                `OR1200_ALUOP_MOVHI : begin
                                if (macrc_op) begin
                                        result = mult_mac_result;
                                end
                                else begin
                                        result = b << 16;
                                end
                end
`ifdef OR1200_MULT_IMPLEMENTED
`ifdef OR1200_IMPL_DIV
                `OR1200_ALUOP_DIV,
                `OR1200_ALUOP_DIVU,
`endif
                `OR1200_ALUOP_MUL : begin
                                result = mult_mac_result;
                end
`endif
    `OR1200_ALUOP_CMOV: begin
        result = flag ? a : b;
    end
 
`ifdef OR1200_CASE_DEFAULT
    default: begin
`else
    `OR1200_ALUOP_COMP, `OR1200_ALUOP_AND:
    begin
`endif
      result=result_and;
    end
        endcase
end
 
//
// l.cust5 custom instructions
//
// Examples for move byte, set bit and clear bit
//
always @(cust5_op or cust5_limm or a or b) begin
        casex (cust5_op)                // synopsys parallel_case
                5'h1 : begin
                        casex (cust5_limm[1:0])
                                2'h0: result_cust5 = {a[31:8], b[7:0]};
                                2'h1: result_cust5 = {a[31:16], b[7:0], a[7:0]};
                                2'h2: result_cust5 = {a[31:24], b[7:0], a[15:0]};
                                2'h3: result_cust5 = {b[7:0], a[23:0]};
                        endcase
                end
                5'h2 :
                        result_cust5 = a | (1 << cust5_limm);
                5'h3 :
                        result_cust5 = a & (32'hffffffff ^ (1 << cust5_limm));
//
// *** Put here new l.cust5 custom instructions ***
//
                default: begin
                        result_cust5 = a;
                end
        endcase
end
 
//
// Generate flag and flag write enable
//
always @(alu_op or result_sum or result_and or flagcomp) begin
        casex (alu_op)          // synopsys parallel_case
`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
                `OR1200_ALUOP_ADD : begin
                        flagforw = (result_sum == 32'h0000_0000);
                        flag_we = 1'b1;
                end
`ifdef OR1200_IMPL_ADDC
                `OR1200_ALUOP_ADDC : begin
                        flagforw = (result_csum == 32'h0000_0000);
                        flag_we = 1'b1;
                end
`endif
                `OR1200_ALUOP_AND: begin
                        flagforw = (result_and == 32'h0000_0000);
                        flag_we = 1'b1;
                end
`endif
                `OR1200_ALUOP_COMP: begin
                        flagforw = flagcomp;
                        flag_we = 1'b1;
                end
                default: begin
                        flagforw = 1'b0;
                        flag_we = 1'b0;
                end
        endcase
end
 
//
// Generate SR[CY] write enable
//
always @(alu_op or cy_sum
`ifdef OR1200_IMPL_ADDC
        or cy_csum
`endif
        ) begin
        casex (alu_op)          // synopsys parallel_case
`ifdef OR1200_IMPL_CY
                `OR1200_ALUOP_ADD : begin
                        cyforw = cy_sum;
                        cy_we = 1'b1;
                end
`ifdef OR1200_IMPL_ADDC
                `OR1200_ALUOP_ADDC: begin
                        cyforw = cy_csum;
                        cy_we = 1'b1;
                end
`endif
`endif
                default: begin
                        cyforw = 1'b0;
                        cy_we = 1'b0;
                end
        endcase
end
 
//
// Shifts and rotation
//
always @(shrot_op or a or b) begin
        case (shrot_op)         // synopsys parallel_case
        `OR1200_SHROTOP_SLL :
                                shifted_rotated = (a << b[4:0]);
                `OR1200_SHROTOP_SRL :
                                shifted_rotated = (a >> b[4:0]);
 
`ifdef OR1200_IMPL_ALU_ROTATE
                `OR1200_SHROTOP_ROR :
                                shifted_rotated = (a << (6'd32-{1'b0, b[4:0]})) | (a >> b[4:0]);
`endif
                default:
                                shifted_rotated = ({32{a[31]}} << (6'd32-{1'b0, b[4:0]})) | a >> b[4:0];
        endcase
end
 
//
// First type of compare implementation
//
`ifdef OR1200_IMPL_ALU_COMP1
always @(comp_op or a_eq_b or a_lt_b) begin
        case(comp_op[2:0])       // synopsys parallel_case
                `OR1200_COP_SFEQ:
                        flagcomp = a_eq_b;
                `OR1200_COP_SFNE:
                        flagcomp = ~a_eq_b;
                `OR1200_COP_SFGT:
                        flagcomp = ~(a_eq_b | a_lt_b);
                `OR1200_COP_SFGE:
                        flagcomp = ~a_lt_b;
                `OR1200_COP_SFLT:
                        flagcomp = a_lt_b;
                `OR1200_COP_SFLE:
                        flagcomp = a_eq_b | a_lt_b;
                default:
                        flagcomp = 1'b0;
        endcase
end
`endif
 
//
// Second type of compare implementation
//
`ifdef OR1200_IMPL_ALU_COMP2
always @(comp_op or comp_a or comp_b) begin
        case(comp_op[2:0])       // synopsys parallel_case
                `OR1200_COP_SFEQ:
                        flagcomp = (comp_a == comp_b);
                `OR1200_COP_SFNE:
                        flagcomp = (comp_a != comp_b);
                `OR1200_COP_SFGT:
                        flagcomp = (comp_a > comp_b);
                `OR1200_COP_SFGE:
                        flagcomp = (comp_a >= comp_b);
                `OR1200_COP_SFLT:
                        flagcomp = (comp_a < comp_b);
                `OR1200_COP_SFLE:
                        flagcomp = (comp_a <= comp_b);
                default:
                        flagcomp = 1'b0;
        endcase
end
`endif
 
endmodule

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Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [or1200/] [rtl/] [verilog/] [or1200_alu.v] - Blame information for rev 12

Line No.	Rev	Author	Line
1	12	xianfeng	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's ALU ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// ALU ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: or1200_alu.v,v $`
47			`// Revision 1.15 2005/01/07 09:23:39 andreje`
48			`// l.ff1 and l.cmov instructions added`
49			`//`
50			`// Revision 1.14 2004/06/08 18:17:36 lampret`
51			`// Non-functional changes. Coding style fixes.`
52			`//`
53			`// Revision 1.13 2004/05/09 19:49:03 lampret`
54			`// Added some l.cust5 custom instructions as example`
55			`//`
56			`// Revision 1.12 2004/04/05 08:29:57 lampret`
57			`// Merged branch_qmem into main tree.`
58			`//`
59			`// Revision 1.11 2003/04/24 00:16:07 lampret`
60			`// No functional changes. Added defines to disable implementation of multiplier/MAC`
61			`//`
62			`// Revision 1.10 2002/09/08 05:52:16 lampret`
63			`// Added optional l.div/l.divu insns. By default they are disabled.`
64			`//`
65			`// Revision 1.9 2002/09/07 19:16:10 lampret`
66			`// If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY].`
67			`//`
68			`// Revision 1.8 2002/09/07 05:42:02 lampret`
69			`// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.`
70			`//`
71			`// Revision 1.7 2002/09/03 22:28:21 lampret`
72			`// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.`
73			`//`
74			`// Revision 1.6 2002/03/29 16:40:10 lampret`
75			`// Added a directive to ignore signed division variables that are only used in simulation.`
76			`//`
77			`// Revision 1.5 2002/03/29 16:33:59 lampret`
78			`// Added again just recently removed full_case directive`
79			`//`
80			`// Revision 1.4 2002/03/29 15:16:53 lampret`
81			`// Some of the warnings fixed.`
82			`//`
83			`// Revision 1.3 2002/01/28 01:15:59 lampret`
84			`// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.`
85			`//`
86			`// Revision 1.2 2002/01/14 06:18:22 lampret`
87			`// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.`
88			`//`
89			`// Revision 1.1 2002/01/03 08:16:15 lampret`
90			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
91			`//`
92			`// Revision 1.10 2001/11/12 01:45:40 lampret`
93			`// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.`
94			`//`
95			`// Revision 1.9 2001/10/21 17:57:16 lampret`
96			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
97			`//`
98			`// Revision 1.8 2001/10/19 23:28:45 lampret`
99			`// Fixed some synthesis warnings. Configured with caches and MMUs.`
100			`//`
101			`// Revision 1.7 2001/10/14 13:12:09 lampret`
102			`// MP3 version.`
103			`//`
104			`// Revision 1.1.1.1 2001/10/06 10:18:35 igorm`
105			`// no message`
106			`//`
107			`// Revision 1.2 2001/08/09 13:39:33 lampret`
108			`// Major clean-up.`
109			`//`
110			`// Revision 1.1 2001/07/20 00:46:03 lampret`
111			`// Development version of RTL. Libraries are missing.`
112			`//`
113			`//`
114
115			`// synopsys translate_off`
116			`include "timescale.v"
117			`// synopsys translate_on`
118			`include "or1200_defines.v"
119
120			`module or1200_alu(`
121			`a, b, mult_mac_result, macrc_op,`
122			`alu_op, shrot_op, comp_op,`
123			`cust5_op, cust5_limm,`
124			`result, flagforw, flag_we,`
125			`cyforw, cy_we, carry, flag`
126			`);`
127
128			parameter width = `OR1200_OPERAND_WIDTH;
129
130			`//`
131			`// I/O`
132			`//`
133			`input [width-1:0] a;`
134			`input [width-1:0] b;`
135			`input [width-1:0] mult_mac_result;`
136			`input macrc_op;`
137			input [`OR1200_ALUOP_WIDTH-1:0] alu_op;
138			input [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
139			input [`OR1200_COMPOP_WIDTH-1:0] comp_op;
140			`input [4:0] cust5_op;`
141			`input [5:0] cust5_limm;`
142			`output [width-1:0] result;`
143			`output flagforw;`
144			`output flag_we;`
145			`output cyforw;`
146			`output cy_we;`
147			`input carry;`
148			`input flag;`
149
150			`//`
151			`// Internal wires and regs`
152			`//`
153			`reg [width-1:0] result;`
154			`reg [width-1:0] shifted_rotated;`
155			`reg [width-1:0] result_cust5;`
156			`reg flagforw;`
157			`reg flagcomp;`
158			`reg flag_we;`
159			`reg cy_we;`
160			`wire [width-1:0] comp_a;`
161			`wire [width-1:0] comp_b;`
162			`ifdef OR1200_IMPL_ALU_COMP1
163			`wire a_eq_b;`
164			`wire a_lt_b;`
165			`endif
166			`wire [width-1:0] result_sum;`
167			`ifdef OR1200_IMPL_ADDC
168			`wire [width-1:0] result_csum;`
169			`wire cy_csum;`
170			`endif
171			`wire [width-1:0] result_and;`
172			`wire cy_sum;`
173			`reg cyforw;`
174
175			`//`
176			`// Combinatorial logic`
177			`//`
178			`assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};`
179			`assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};`
180			`ifdef OR1200_IMPL_ALU_COMP1
181			`assign a_eq_b = (comp_a == comp_b);`
182			`assign a_lt_b = (comp_a < comp_b);`
183			`endif
184			`assign {cy_sum, result_sum} = a + b;`
185			`ifdef OR1200_IMPL_ADDC
186			`assign {cy_csum, result_csum} = a + b + {32'd0, carry};`
187			`endif
188			`assign result_and = a & b;`
189
190			`//`
191			`// Simulation check for bad ALU behavior`
192			`//`
193			`ifdef OR1200_WARNINGS
194			`// synopsys translate_off`
195			`always @(result) begin`
196			`if (result === 32'bx)`
197			`$display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);`
198			`end`
199			`// synopsys translate_on`
200			`endif
201
202			`//`
203			`// Central part of the ALU`
204			`//`
205			`always @(alu_op or a or b or result_sum or result_and or macrc_op or shifted_rotated or mult_mac_result) begin`
206			`ifdef OR1200_CASE_DEFAULT
207			`casex (alu_op) // synopsys parallel_case`
208			`else
209			`casex (alu_op) // synopsys full_case parallel_case`
210			`endif
211			`OR1200_ALUOP_FF1: begin
212			`result = a[0] ? 1 : a[1] ? 2 : a[2] ? 3 : a[3] ? 4 : a[4] ? 5 : a[5] ? 6 : a[6] ? 7 : a[7] ? 8 : a[8] ? 9 : a[9] ? 10 : a[10] ? 11 : a[11] ? 12 : a[12] ? 13 : a[13] ? 14 : a[14] ? 15 : a[15] ? 16 : a[16] ? 17 : a[17] ? 18 : a[18] ? 19 : a[19] ? 20 : a[20] ? 21 : a[21] ? 22 : a[22] ? 23 : a[23] ? 24 : a[24] ? 25 : a[25] ? 26 : a[26] ? 27 : a[27] ? 28 : a[28] ? 29 : a[29] ? 30 : a[30] ? 31 : a[31] ? 32 : 0;`
213			`end`
214			`OR1200_ALUOP_CUST5 : begin
215			`result = result_cust5;`
216			`end`
217			`OR1200_ALUOP_SHROT : begin
218			`result = shifted_rotated;`
219			`end`
220			`OR1200_ALUOP_ADD : begin
221			`result = result_sum;`
222			`end`
223			`ifdef OR1200_IMPL_ADDC
224			`OR1200_ALUOP_ADDC : begin
225			`result = result_csum;`
226			`end`
227			`endif
228			`OR1200_ALUOP_SUB : begin
229			`result = a - b;`
230			`end`
231			`OR1200_ALUOP_XOR : begin
232			`result = a ^ b;`
233			`end`
234			`OR1200_ALUOP_OR : begin
235			`result = a \| b;`
236			`end`
237			`OR1200_ALUOP_IMM : begin
238			`result = b;`
239			`end`
240			`OR1200_ALUOP_MOVHI : begin
241			`if (macrc_op) begin`
242			`result = mult_mac_result;`
243			`end`
244			`else begin`
245			`result = b << 16;`
246			`end`
247			`end`
248			`ifdef OR1200_MULT_IMPLEMENTED
249			`ifdef OR1200_IMPL_DIV
250			`OR1200_ALUOP_DIV,
251			`OR1200_ALUOP_DIVU,
252			`endif
253			`OR1200_ALUOP_MUL : begin
254			`result = mult_mac_result;`
255			`end`
256			`endif
257			`OR1200_ALUOP_CMOV: begin
258			`result = flag ? a : b;`
259			`end`
260
261			`ifdef OR1200_CASE_DEFAULT
262			`default: begin`
263			`else
264			`OR1200_ALUOP_COMP, `OR1200_ALUOP_AND:
265			`begin`
266			`endif
267			`result=result_and;`
268			`end`
269			`endcase`
270			`end`
271
272			`//`
273			`// l.cust5 custom instructions`
274			`//`
275			`// Examples for move byte, set bit and clear bit`
276			`//`
277			`always @(cust5_op or cust5_limm or a or b) begin`
278			`casex (cust5_op) // synopsys parallel_case`
279			`5'h1 : begin`
280			`casex (cust5_limm[1:0])`
281			`2'h0: result_cust5 = {a[31:8], b[7:0]};`
282			`2'h1: result_cust5 = {a[31:16], b[7:0], a[7:0]};`
283			`2'h2: result_cust5 = {a[31:24], b[7:0], a[15:0]};`
284			`2'h3: result_cust5 = {b[7:0], a[23:0]};`
285			`endcase`
286			`end`
287			`5'h2 :`
288			`result_cust5 = a \| (1 << cust5_limm);`
289			`5'h3 :`
290			`result_cust5 = a & (32'hffffffff ^ (1 << cust5_limm));`
291			`//`
292			`// * Put here new l.cust5 custom instructions *`
293			`//`
294			`default: begin`
295			`result_cust5 = a;`
296			`end`
297			`endcase`
298			`end`
299
300			`//`
301			`// Generate flag and flag write enable`
302			`//`
303			`always @(alu_op or result_sum or result_and or flagcomp) begin`
304			`casex (alu_op) // synopsys parallel_case`
305			`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
306			`OR1200_ALUOP_ADD : begin
307			`flagforw = (result_sum == 32'h0000_0000);`
308			`flag_we = 1'b1;`
309			`end`
310			`ifdef OR1200_IMPL_ADDC
311			`OR1200_ALUOP_ADDC : begin
312			`flagforw = (result_csum == 32'h0000_0000);`
313			`flag_we = 1'b1;`
314			`end`
315			`endif
316			`OR1200_ALUOP_AND: begin
317			`flagforw = (result_and == 32'h0000_0000);`
318			`flag_we = 1'b1;`
319			`end`
320			`endif
321			`OR1200_ALUOP_COMP: begin
322			`flagforw = flagcomp;`
323			`flag_we = 1'b1;`
324			`end`
325			`default: begin`
326			`flagforw = 1'b0;`
327			`flag_we = 1'b0;`
328			`end`
329			`endcase`
330			`end`
331
332			`//`
333			`// Generate SR[CY] write enable`
334			`//`
335			`always @(alu_op or cy_sum`
336			`ifdef OR1200_IMPL_ADDC
337			`or cy_csum`
338			`endif
339			`) begin`
340			`casex (alu_op) // synopsys parallel_case`
341			`ifdef OR1200_IMPL_CY
342			`OR1200_ALUOP_ADD : begin
343			`cyforw = cy_sum;`
344			`cy_we = 1'b1;`
345			`end`
346			`ifdef OR1200_IMPL_ADDC
347			`OR1200_ALUOP_ADDC: begin
348			`cyforw = cy_csum;`
349			`cy_we = 1'b1;`
350			`end`
351			`endif
352			`endif
353			`default: begin`
354			`cyforw = 1'b0;`
355			`cy_we = 1'b0;`
356			`end`
357			`endcase`
358			`end`
359
360			`//`
361			`// Shifts and rotation`
362			`//`
363			`always @(shrot_op or a or b) begin`
364			`case (shrot_op) // synopsys parallel_case`
365			`OR1200_SHROTOP_SLL :
366			`shifted_rotated = (a << b[4:0]);`
367			`OR1200_SHROTOP_SRL :
368			`shifted_rotated = (a >> b[4:0]);`
369
370			`ifdef OR1200_IMPL_ALU_ROTATE
371			`OR1200_SHROTOP_ROR :
372			`shifted_rotated = (a << (6'd32-{1'b0, b[4:0]})) \| (a >> b[4:0]);`
373			`endif
374			`default:`
375			`shifted_rotated = ({32{a[31]}} << (6'd32-{1'b0, b[4:0]})) \| a >> b[4:0];`
376			`endcase`
377			`end`
378
379			`//`
380			`// First type of compare implementation`
381			`//`
382			`ifdef OR1200_IMPL_ALU_COMP1
383			`always @(comp_op or a_eq_b or a_lt_b) begin`
384			`case(comp_op[2:0]) // synopsys parallel_case`
385			`OR1200_COP_SFEQ:
386			`flagcomp = a_eq_b;`
387			`OR1200_COP_SFNE:
388			`flagcomp = ~a_eq_b;`
389			`OR1200_COP_SFGT:
390			`flagcomp = ~(a_eq_b \| a_lt_b);`
391			`OR1200_COP_SFGE:
392			`flagcomp = ~a_lt_b;`
393			`OR1200_COP_SFLT:
394			`flagcomp = a_lt_b;`
395			`OR1200_COP_SFLE:
396			`flagcomp = a_eq_b \| a_lt_b;`
397			`default:`
398			`flagcomp = 1'b0;`
399			`endcase`
400			`end`
401			`endif
402
403			`//`
404			`// Second type of compare implementation`
405			`//`
406			`ifdef OR1200_IMPL_ALU_COMP2
407			`always @(comp_op or comp_a or comp_b) begin`
408			`case(comp_op[2:0]) // synopsys parallel_case`
409			`OR1200_COP_SFEQ:
410			`flagcomp = (comp_a == comp_b);`
411			`OR1200_COP_SFNE:
412			`flagcomp = (comp_a != comp_b);`
413			`OR1200_COP_SFGT:
414			`flagcomp = (comp_a > comp_b);`
415			`OR1200_COP_SFGE:
416			`flagcomp = (comp_a >= comp_b);`
417			`OR1200_COP_SFLT:
418			`flagcomp = (comp_a < comp_b);`
419			`OR1200_COP_SFLE:
420			`flagcomp = (comp_a <= comp_b);`
421			`default:`
422			`flagcomp = 1'b0;`
423			`endcase`
424			`end`
425			`endif
426
427			`endmodule`