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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [or1200/] [rtl/] [verilog/] [or1200_defines.v] - Blame information for rev 12

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1 12 xianfeng 
//////////////////////////////////////////////////////////////////////
2 
////                                                              ////
3 
////  OR1200's definitions                                        ////
4 
////                                                              ////
5 
////  This file is part of the OpenRISC 1200 project              ////
6 
////  http://www.opencores.org/cores/or1k/                        ////
7 
////                                                              ////
8 
////  Description                                                 ////
9 
////  Parameters of the OR1200 core                               ////
10 
////                                                              ////
11 
////  To Do:                                                      ////
12 
////   - add parameters that are missing                          ////
13 
////                                                              ////
14 
////  Author(s):                                                  ////
15 
////      - Damjan Lampret, lampret@opencores.org                 ////
16 
////                                                              ////
17 
//////////////////////////////////////////////////////////////////////
18 
////                                                              ////
19 
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20 
////                                                              ////
21 
//// This source file may be used and distributed without         ////
22 
//// restriction provided that this copyright statement is not    ////
23 
//// removed from the file and that any derivative work contains  ////
24 
//// the original copyright notice and the associated disclaimer. ////
25 
////                                                              ////
26 
//// This source file is free software; you can redistribute it   ////
27 
//// and/or modify it under the terms of the GNU Lesser General   ////
28 
//// Public License as published by the Free Software Foundation; ////
29 
//// either version 2.1 of the License, or (at your option) any   ////
30 
//// later version.                                               ////
31 
////                                                              ////
32 
//// This source is distributed in the hope that it will be       ////
33 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36 
//// details.                                                     ////
37 
////                                                              ////
38 
//// You should have received a copy of the GNU Lesser General    ////
39 
//// Public License along with this source; if not, download it   ////
40 
//// from http://www.opencores.org/lgpl.shtml                     ////
41 
////                                                              ////
42 
//////////////////////////////////////////////////////////////////////
43 
//
44 
// CVS Revision History
45 
//
46 
// $Log: or1200_defines.v,v $
47 
// Revision 1.45  2006/04/09 01:32:29  lampret
48 
// See OR1200_MAC_SHIFTBY in or1200_defines.v for explanation of the change. Since now no more 28 bits shift for l.macrc insns however for backward compatbility it is possible to set arbitry number of shifts.
49 
//
50 
// Revision 1.44  2005/10/19 11:37:56  jcastillo
51 
// Added support for RAMB16 Xilinx4/Spartan3 primitives
52 
//
53 
// Revision 1.43  2005/01/07 09:23:39  andreje
54 
// l.ff1 and l.cmov instructions added
55 
//
56 
// Revision 1.42  2004/06/08 18:17:36  lampret
57 
// Non-functional changes. Coding style fixes.
58 
//
59 
// Revision 1.41  2004/05/09 20:03:20  lampret
60 
// By default l.cust5 insns are disabled
61 
//
62 
// Revision 1.40  2004/05/09 19:49:04  lampret
63 
// Added some l.cust5 custom instructions as example
64 
//
65 
// Revision 1.39  2004/04/08 11:00:46  simont
66 
// Add support for 512B instruction cache.
67 
//
68 
// Revision 1.38  2004/04/05 08:29:57  lampret
69 
// Merged branch_qmem into main tree.
70 
//
71 
// Revision 1.35.4.6  2004/02/11 01:40:11  lampret
72 
// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
73 
//
74 
// Revision 1.35.4.5  2004/01/15 06:46:38  markom
75 
// interface to debug changed; no more opselect; stb-ack protocol
76 
//
77 
// Revision 1.35.4.4  2004/01/11 22:45:46  andreje
78 
// Separate instruction and data QMEM decoders, QMEM acknowledge and byte-select added
79 
//
80 
// Revision 1.35.4.3  2003/12/17 13:43:38  simons
81 
// Exception prefix configuration changed.
82 
//
83 
// Revision 1.35.4.2  2003/12/05 00:05:03  lampret
84 
// Static exception prefix.
85 
//
86 
// Revision 1.35.4.1  2003/07/08 15:36:37  lampret
87 
// Added embedded memory QMEM.
88 
//
89 
// Revision 1.35  2003/04/24 00:16:07  lampret
90 
// No functional changes. Added defines to disable implementation of multiplier/MAC
91 
//
92 
// Revision 1.34  2003/04/20 22:23:57  lampret
93 
// No functional change. Only added customization for exception vectors.
94 
//
95 
// Revision 1.33  2003/04/07 20:56:07  lampret
96 
// Fixed OR1200_CLKDIV_x_SUPPORTED defines. Better description.
97 
//
98 
// Revision 1.32  2003/04/07 01:26:57  lampret
99 
// RFRAM defines comments updated. Altera LPM option added.
100 
//
101 
// Revision 1.31  2002/12/08 08:57:56  lampret
102 
// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.
103 
//
104 
// Revision 1.30  2002/10/28 15:09:22  mohor
105 
// Previous check-in was done by mistake.
106 
//
107 
// Revision 1.29  2002/10/28 15:03:50  mohor
108 
// Signal scanb_sen renamed to scanb_en.
109 
//
110 
// Revision 1.28  2002/10/17 20:04:40  lampret
111 
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
112 
//
113 
// Revision 1.27  2002/09/16 03:13:23  lampret
114 
// Removed obsolete comment.
115 
//
116 
// Revision 1.26  2002/09/08 05:52:16  lampret
117 
// Added optional l.div/l.divu insns. By default they are disabled.
118 
//
119 
// Revision 1.25  2002/09/07 19:16:10  lampret
120 
// If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY].
121 
//
122 
// Revision 1.24  2002/09/07 05:42:02  lampret
123 
// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
124 
//
125 
// Revision 1.23  2002/09/04 00:50:34  lampret
126 
// Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v.
127 
//
128 
// Revision 1.22  2002/09/03 22:28:21  lampret
129 
// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
130 
//
131 
// Revision 1.21  2002/08/22 02:18:55  lampret
132 
// Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.
133 
//
134 
// Revision 1.20  2002/08/18 21:59:45  lampret
135 
// Disable SB until it is tested
136 
//
137 
// Revision 1.19  2002/08/18 19:53:08  lampret
138 
// Added store buffer.
139 
//
140 
// Revision 1.18  2002/08/15 06:04:11  lampret
141 
// Fixed Xilinx trace buffer address. REported by Taylor Su.
142 
//
143 
// Revision 1.17  2002/08/12 05:31:44  lampret
144 
// Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section.
145 
//
146 
// Revision 1.16  2002/07/14 22:17:17  lampret
147 
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
148 
//
149 
// Revision 1.15  2002/06/08 16:20:21  lampret
150 
// Added defines for enabling generic FF based memory macro for register file.
151 
//
152 
// Revision 1.14  2002/03/29 16:24:06  lampret
153 
// Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives
154 
//
155 
// Revision 1.13  2002/03/29 15:16:55  lampret
156 
// Some of the warnings fixed.
157 
//
158 
// Revision 1.12  2002/03/28 19:25:42  lampret
159 
// Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.
160 
//
161 
// Revision 1.11  2002/03/28 19:13:17  lampret
162 
// Updated defines.
163 
//
164 
// Revision 1.10  2002/03/14 00:30:24  lampret
165 
// Added alternative for critical path in DU.
166 
//
167 
// Revision 1.9  2002/03/11 01:26:26  lampret
168 
// Fixed async loop. Changed multiplier type for ASIC.
169 
//
170 
// Revision 1.8  2002/02/11 04:33:17  lampret
171 
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
172 
//
173 
// Revision 1.7  2002/02/01 19:56:54  lampret
174 
// Fixed combinational loops.
175 
//
176 
// Revision 1.6  2002/01/19 14:10:22  lampret
177 
// Fixed OR1200_XILINX_RAM32X1D.
178 
//
179 
// Revision 1.5  2002/01/18 07:56:00  lampret
180 
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
181 
//
182 
// Revision 1.4  2002/01/14 09:44:12  lampret
183 
// Default ASIC configuration does not sample WB inputs.
184 
//
185 
// Revision 1.3  2002/01/08 00:51:08  lampret
186 
// Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be.
187 
//
188 
// Revision 1.2  2002/01/03 21:23:03  lampret
189 
// Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target.
190 
//
191 
// Revision 1.1  2002/01/03 08:16:15  lampret
192 
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
193 
//
194 
// Revision 1.20  2001/12/04 05:02:36  lampret
195 
// Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32
196 
//
197 
// Revision 1.19  2001/11/27 19:46:57  lampret
198 
// Now FPGA and ASIC target are separate.
199 
//
200 
// Revision 1.18  2001/11/23 21:42:31  simons
201 
// Program counter divided to PPC and NPC.
202 
//
203 
// Revision 1.17  2001/11/23 08:38:51  lampret
204 
// Changed DSR/DRR behavior and exception detection.
205 
//
206 
// Revision 1.16  2001/11/20 21:30:38  lampret
207 
// Added OR1200_REGISTERED_INPUTS.
208 
//
209 
// Revision 1.15  2001/11/19 14:29:48  simons
210 
// Cashes disabled.
211 
//
212 
// Revision 1.14  2001/11/13 10:02:21  lampret
213 
// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
214 
//
215 
// Revision 1.13  2001/11/12 01:45:40  lampret
216 
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
217 
//
218 
// Revision 1.12  2001/11/10 03:43:57  lampret
219 
// Fixed exceptions.
220 
//
221 
// Revision 1.11  2001/11/02 18:57:14  lampret
222 
// Modified virtual silicon instantiations.
223 
//
224 
// Revision 1.10  2001/10/21 17:57:16  lampret
225 
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
226 
//
227 
// Revision 1.9  2001/10/19 23:28:46  lampret
228 
// Fixed some synthesis warnings. Configured with caches and MMUs.
229 
//
230 
// Revision 1.8  2001/10/14 13:12:09  lampret
231 
// MP3 version.
232 
//
233 
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
234 
// no message
235 
//
236 
// Revision 1.3  2001/08/17 08:01:19  lampret
237 
// IC enable/disable.
238 
//
239 
// Revision 1.2  2001/08/13 03:36:20  lampret
240 
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
241 
//
242 
// Revision 1.1  2001/08/09 13:39:33  lampret
243 
// Major clean-up.
244 
//
245 
// Revision 1.2  2001/07/22 03:31:54  lampret
246 
// Fixed RAM's oen bug. Cache bypass under development.
247 
//
248 
// Revision 1.1  2001/07/20 00:46:03  lampret
249 
// Development version of RTL. Libraries are missing.
250 
//
251 
//
252 
 
253 
//
254 
// Dump VCD
255 
//
256 
//`define OR1200_VCD_DUMP
257 
 
258 
//
259 
// Generate debug messages during simulation
260 
//
261 
//`define OR1200_VERBOSE
262 
 
263 
//  `define OR1200_ASIC
264 
////////////////////////////////////////////////////////
265 
//
266 
// Typical configuration for an ASIC
267 
//
268 
`ifdef OR1200_ASIC
269 
 
270 
//
271 
// Target ASIC memories
272 
//
273 
//`define OR1200_ARTISAN_SSP
274 
//`define OR1200_ARTISAN_SDP
275 
//`define OR1200_ARTISAN_STP
276 
`define OR1200_VIRTUALSILICON_SSP
277 
//`define OR1200_VIRTUALSILICON_STP_T1
278 
//`define OR1200_VIRTUALSILICON_STP_T2
279 
 
280 
//
281 
// Do not implement Data cache
282 
//
283 
//`define OR1200_NO_DC
284 
 
285 
//
286 
// Do not implement Insn cache
287 
//
288 
//`define OR1200_NO_IC
289 
 
290 
//
291 
// Do not implement Data MMU
292 
//
293 
//`define OR1200_NO_DMMU
294 
 
295 
//
296 
// Do not implement Insn MMU
297 
//
298 
//`define OR1200_NO_IMMU
299 
 
300 
//
301 
// Select between ASIC optimized and generic multiplier
302 
//
303 
//`define OR1200_ASIC_MULTP2_32X32
304 
`define OR1200_GENERIC_MULTP2_32X32
305 
 
306 
//
307 
// Size/type of insn/data cache if implemented
308 
//
309 
// `define OR1200_IC_1W_512B
310 
// `define OR1200_IC_1W_4KB
311 
`define OR1200_IC_1W_8KB
312 
// `define OR1200_DC_1W_4KB
313 
`define OR1200_DC_1W_8KB
314 
 
315 
`else
316 
 
317 
 
318 
/////////////////////////////////////////////////////////
319 
//
320 
// Typical configuration for an FPGA
321 
//
322 
 
323 
//
324 
// Target FPGA memories
325 
//
326 
//`define OR1200_ALTERA_LPM
327 
//`define OR1200_XILINX_RAMB16
328 
//`define OR1200_XILINX_RAMB4
329 
//`define OR1200_XILINX_RAM32X1D
330 
//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D
331 
 
332 
//
333 
// Do not implement Data cache
334 
//
335 
//`define OR1200_NO_DC
336 
 
337 
//
338 
// Do not implement Insn cache
339 
//
340 
//`define OR1200_NO_IC
341 
 
342 
//
343 
// Do not implement Data MMU
344 
//
345 
//`define OR1200_NO_DMMU
346 
 
347 
//
348 
// Do not implement Insn MMU
349 
//
350 
//`define OR1200_NO_IMMU
351 
 
352 
//
353 
// Select between ASIC and generic multiplier
354 
//
355 
// (Generic seems to trigger a bug in the Cadence Ncsim simulator)
356 
//
357 
//`define OR1200_ASIC_MULTP2_32X32
358 
`define OR1200_GENERIC_MULTP2_32X32
359 
 
360 
//
361 
// Size/type of insn/data cache if implemented
362 
// (consider available FPGA memory resources)
363 
//
364 
//`define OR1200_IC_1W_512B
365 
//`define OR1200_IC_1W_4KB
366 
`define OR1200_IC_1W_8KB
367 
//`define OR1200_DC_1W_4KB
368 
`define OR1200_DC_1W_8KB
369 
 
370 
`endif
371 
 
372 
 
373 
//////////////////////////////////////////////////////////
374 
//
375 
// Do not change below unless you know what you are doing
376 
//
377 
 
378 
//
379 
// Enable RAM BIST
380 
//
381 
// At the moment this only works for Virtual Silicon
382 
// single port RAMs. For other RAMs it has not effect.
383 
// Special wrapper for VS RAMs needs to be provided
384 
// with scan flops to facilitate bist scan.
385 
//
386 
//`define OR1200_BIST
387 
 
388 
//
389 
// Register OR1200 WISHBONE outputs
390 
// (must be defined/enabled)
391 
//
392 
`define OR1200_REGISTERED_OUTPUTS
393 
 
394 
//
395 
// Register OR1200 WISHBONE inputs
396 
//
397 
// (must be undefined/disabled)
398 
//
399 
//`define OR1200_REGISTERED_INPUTS
400 
 
401 
//
402 
// Disable bursts if they are not supported by the
403 
// memory subsystem (only affect cache line fill)
404 
//
405 
//`define OR1200_NO_BURSTS
406 
//
407 
 
408 
//
409 
// WISHBONE retry counter range
410 
//
411 
// 2^value range for retry counter. Retry counter
412 
// is activated whenever *wb_rty_i is asserted and
413 
// until retry counter expires, corresponding
414 
// WISHBONE interface is deactivated.
415 
//
416 
// To disable retry counters and *wb_rty_i all together,
417 
// undefine this macro.
418 
//
419 
//`define OR1200_WB_RETRY 7
420 
 
421 
//
422 
// WISHBONE Consecutive Address Burst
423 
//
424 
// This was used prior to WISHBONE B3 specification
425 
// to identify bursts. It is no longer needed but
426 
// remains enabled for compatibility with old designs.
427 
//
428 
// To remove *wb_cab_o ports undefine this macro.
429 
//
430 
`define OR1200_WB_CAB
431 
 
432 
//
433 
// WISHBONE B3 compatible interface
434 
//
435 
// This follows the WISHBONE B3 specification.
436 
// It is not enabled by default because most
437 
// designs still don't use WB b3.
438 
//
439 
// To enable *wb_cti_o/*wb_bte_o ports,
440 
// define this macro.
441 
//
442 
//`define OR1200_WB_B3
443 
 
444 
//
445 
// Enable additional synthesis directives if using
446 
// _Synopsys_ synthesis tool
447 
//
448 
//`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
449 
 
450 
//
451 
// Enables default statement in some case blocks
452 
// and disables Synopsys synthesis directive full_case
453 
//
454 
// By default it is enabled. When disabled it
455 
// can increase clock frequency.
456 
//
457 
`define OR1200_CASE_DEFAULT
458 
 
459 
//
460 
// Operand width / register file address width
461 
//
462 
// (DO NOT CHANGE)
463 
//
464 
`define OR1200_OPERAND_WIDTH            32
465 
`define OR1200_REGFILE_ADDR_WIDTH       5
466 
 
467 
//
468 
// l.add/l.addi/l.and and optional l.addc/l.addic
469 
// also set (compare) flag when result of their
470 
// operation equals zero
471 
//
472 
// At the time of writing this, default or32
473 
// C/C++ compiler doesn't generate code that
474 
// would benefit from this optimization.
475 
//
476 
// By default this optimization is disabled to
477 
// save area.
478 
//
479 
//`define OR1200_ADDITIONAL_FLAG_MODIFIERS
480 
 
481 
//
482 
// Implement l.addc/l.addic instructions
483 
//
484 
// By default implementation of l.addc/l.addic
485 
// instructions is enabled in case you need them.
486 
// If you don't use them, then disable implementation
487 
// to save area.
488 
//
489 
`define OR1200_IMPL_ADDC
490 
 
491 
//
492 
// Implement carry bit SR[CY]
493 
//
494 
// By default implementation of SR[CY] is enabled
495 
// to be compliant with the simulator. However
496 
// SR[CY] is explicitly only used by l.addc/l.addic
497 
// instructions and if these two insns are not
498 
// implemented there is not much point having SR[CY].
499 
//
500 
`define OR1200_IMPL_CY
501 
 
502 
//
503 
// Implement optional l.div/l.divu instructions
504 
//
505 
// By default divide instructions are not implemented
506 
// to save area and increase clock frequency. or32 C/C++
507 
// compiler can use soft library for division.
508 
//
509 
// To implement divide, multiplier needs to be implemented.
510 
//
511 
//`define OR1200_IMPL_DIV
512 
 
513 
//
514 
// Implement rotate in the ALU
515 
//
516 
// At the time of writing this, or32
517 
// C/C++ compiler doesn't generate rotate
518 
// instructions. However or32 assembler
519 
// can assemble code that uses rotate insn.
520 
// This means that rotate instructions
521 
// must be used manually inserted.
522 
//
523 
// By default implementation of rotate
524 
// is disabled to save area and increase
525 
// clock frequency.
526 
//
527 
//`define OR1200_IMPL_ALU_ROTATE
528 
 
529 
//
530 
// Type of ALU compare to implement
531 
//
532 
// Try either one to find what yields
533 
// higher clock frequencyin your case.
534 
//
535 
//`define OR1200_IMPL_ALU_COMP1
536 
`define OR1200_IMPL_ALU_COMP2
537 
 
538 
//
539 
// Implement multiplier
540 
//
541 
// By default multiplier is implemented
542 
//
543 
`define OR1200_MULT_IMPLEMENTED
544 
 
545 
//
546 
// Implement multiply-and-accumulate
547 
//
548 
// By default MAC is implemented. To
549 
// implement MAC, multiplier needs to be
550 
// implemented.
551 
//
552 
`define OR1200_MAC_IMPLEMENTED
553 
 
554 
//
555 
// Low power, slower multiplier
556 
//
557 
// Select between low-power (larger) multiplier
558 
// and faster multiplier. The actual difference
559 
// is only AND logic that prevents distribution
560 
// of operands into the multiplier when instruction
561 
// in execution is not multiply instruction
562 
//
563 
//`define OR1200_LOWPWR_MULT
564 
 
565 
//
566 
// Clock ratio RISC clock versus WB clock
567 
//
568 
// If you plan to run WB:RISC clock fixed to 1:1, disable
569 
// both defines
570 
//
571 
// For WB:RISC 1:2 or 1:1, enable OR1200_CLKDIV_2_SUPPORTED
572 
// and use clmode to set ratio
573 
//
574 
// For WB:RISC 1:4, 1:2 or 1:1, enable both defines and use
575 
// clmode to set ratio
576 
//
577 
//`define OR1200_CLKDIV_2_SUPPORTED
578 
//`define OR1200_CLKDIV_4_SUPPORTED
579 
 
580 
//
581 
// Type of register file RAM
582 
//
583 
// Memory macro w/ two ports (see or1200_tpram_32x32.v)
584 
//`define OR1200_RFRAM_TWOPORT
585 
//
586 
// Memory macro dual port (see or1200_dpram_32x32.v)
587 
//`define OR1200_RFRAM_DUALPORT
588 
//
589 
// Generic (flip-flop based) register file (see or1200_rfram_generic.v)
590 
`define OR1200_RFRAM_GENERIC
591 
 
592 
//
593 
// Type of mem2reg aligner to implement.
594 
//
595 
// Once OR1200_IMPL_MEM2REG2 yielded faster
596 
// circuit, however with today tools it will
597 
// most probably give you slower circuit.
598 
//
599 
`define OR1200_IMPL_MEM2REG1
600 
//`define OR1200_IMPL_MEM2REG2
601 
 
602 
//
603 
// ALUOPs
604 
//
605 
`define OR1200_ALUOP_WIDTH      4
606 
`define OR1200_ALUOP_NOP        4'd4
607 
/* Order defined by arith insns that have two source operands both in regs
608 
   (see binutils/include/opcode/or32.h) */
609 
`define OR1200_ALUOP_ADD        4'd0
610 
`define OR1200_ALUOP_ADDC       4'd1
611 
`define OR1200_ALUOP_SUB        4'd2
612 
`define OR1200_ALUOP_AND        4'd3
613 
`define OR1200_ALUOP_OR         4'd4
614 
`define OR1200_ALUOP_XOR        4'd5
615 
`define OR1200_ALUOP_MUL        4'd6
616 
`define OR1200_ALUOP_CUST5      4'd7
617 
`define OR1200_ALUOP_SHROT      4'd8
618 
`define OR1200_ALUOP_DIV        4'd9
619 
`define OR1200_ALUOP_DIVU       4'd10
620 
/* Order not specifically defined. */
621 
`define OR1200_ALUOP_IMM        4'd11
622 
`define OR1200_ALUOP_MOVHI      4'd12
623 
`define OR1200_ALUOP_COMP       4'd13
624 
`define OR1200_ALUOP_MTSR       4'd14
625 
`define OR1200_ALUOP_MFSR       4'd15
626 
`define OR1200_ALUOP_CMOV 4'd14
627 
`define OR1200_ALUOP_FF1  4'd15
628 
//
629 
// MACOPs
630 
//
631 
`define OR1200_MACOP_WIDTH      2
632 
`define OR1200_MACOP_NOP        2'b00
633 
`define OR1200_MACOP_MAC        2'b01
634 
`define OR1200_MACOP_MSB        2'b10
635 
 
636 
//
637 
// Shift/rotate ops
638 
//
639 
`define OR1200_SHROTOP_WIDTH    2
640 
`define OR1200_SHROTOP_NOP      2'd0
641 
`define OR1200_SHROTOP_SLL      2'd0
642 
`define OR1200_SHROTOP_SRL      2'd1
643 
`define OR1200_SHROTOP_SRA      2'd2
644 
`define OR1200_SHROTOP_ROR      2'd3
645 
 
646 
// Execution cycles per instruction
647 
`define OR1200_MULTICYCLE_WIDTH 2
648 
`define OR1200_ONE_CYCLE                2'd0
649 
`define OR1200_TWO_CYCLES               2'd1
650 
 
651 
// Operand MUX selects
652 
`define OR1200_SEL_WIDTH                2
653 
`define OR1200_SEL_RF                   2'd0
654 
`define OR1200_SEL_IMM                  2'd1
655 
`define OR1200_SEL_EX_FORW              2'd2
656 
`define OR1200_SEL_WB_FORW              2'd3
657 
 
658 
//
659 
// BRANCHOPs
660 
//
661 
`define OR1200_BRANCHOP_WIDTH           3
662 
`define OR1200_BRANCHOP_NOP             3'd0
663 
`define OR1200_BRANCHOP_J               3'd1
664 
`define OR1200_BRANCHOP_JR              3'd2
665 
`define OR1200_BRANCHOP_BAL             3'd3
666 
`define OR1200_BRANCHOP_BF              3'd4
667 
`define OR1200_BRANCHOP_BNF             3'd5
668 
`define OR1200_BRANCHOP_RFE             3'd6
669 
 
670 
//
671 
// LSUOPs
672 
//
673 
// Bit 0: sign extend
674 
// Bits 1-2: 00 doubleword, 01 byte, 10 halfword, 11 singleword
675 
// Bit 3: 0 load, 1 store
676 
`define OR1200_LSUOP_WIDTH              4
677 
`define OR1200_LSUOP_NOP                4'b0000
678 
`define OR1200_LSUOP_LBZ                4'b0010
679 
`define OR1200_LSUOP_LBS                4'b0011
680 
`define OR1200_LSUOP_LHZ                4'b0100
681 
`define OR1200_LSUOP_LHS                4'b0101
682 
`define OR1200_LSUOP_LWZ                4'b0110
683 
`define OR1200_LSUOP_LWS                4'b0111
684 
`define OR1200_LSUOP_LD         4'b0001
685 
`define OR1200_LSUOP_SD         4'b1000
686 
`define OR1200_LSUOP_SB         4'b1010
687 
`define OR1200_LSUOP_SH         4'b1100
688 
`define OR1200_LSUOP_SW         4'b1110
689 
 
690 
// FETCHOPs
691 
`define OR1200_FETCHOP_WIDTH            1
692 
`define OR1200_FETCHOP_NOP              1'b0
693 
`define OR1200_FETCHOP_LW               1'b1
694 
 
695 
//
696 
// Register File Write-Back OPs
697 
//
698 
// Bit 0: register file write enable
699 
// Bits 2-1: write-back mux selects
700 
`define OR1200_RFWBOP_WIDTH             3
701 
`define OR1200_RFWBOP_NOP               3'b000
702 
`define OR1200_RFWBOP_ALU               3'b001
703 
`define OR1200_RFWBOP_LSU               3'b011
704 
`define OR1200_RFWBOP_SPRS              3'b101
705 
`define OR1200_RFWBOP_LR                3'b111
706 
 
707 
// Compare instructions
708 
`define OR1200_COP_SFEQ       3'b000
709 
`define OR1200_COP_SFNE       3'b001
710 
`define OR1200_COP_SFGT       3'b010
711 
`define OR1200_COP_SFGE       3'b011
712 
`define OR1200_COP_SFLT       3'b100
713 
`define OR1200_COP_SFLE       3'b101
714 
`define OR1200_COP_X          3'b111
715 
`define OR1200_SIGNED_COMPARE 'd3
716 
`define OR1200_COMPOP_WIDTH     4
717 
 
718 
//
719 
// TAGs for instruction bus
720 
//
721 
`define OR1200_ITAG_IDLE        4'h0    // idle bus
722 
`define OR1200_ITAG_NI          4'h1    // normal insn
723 
`define OR1200_ITAG_BE          4'hb    // Bus error exception
724 
`define OR1200_ITAG_PE          4'hc    // Page fault exception
725 
`define OR1200_ITAG_TE          4'hd    // TLB miss exception
726 
 
727 
//
728 
// TAGs for data bus
729 
//
730 
`define OR1200_DTAG_IDLE        4'h0    // idle bus
731 
`define OR1200_DTAG_ND          4'h1    // normal data
732 
`define OR1200_DTAG_AE          4'ha    // Alignment exception
733 
`define OR1200_DTAG_BE          4'hb    // Bus error exception
734 
`define OR1200_DTAG_PE          4'hc    // Page fault exception
735 
`define OR1200_DTAG_TE          4'hd    // TLB miss exception
736 
 
737 
 
738 
//////////////////////////////////////////////
739 
//
740 
// ORBIS32 ISA specifics
741 
//
742 
 
743 
// SHROT_OP position in machine word
744 
`define OR1200_SHROTOP_POS              7:6
745 
 
746 
// ALU instructions multicycle field in machine word
747 
`define OR1200_ALUMCYC_POS              9:8
748 
 
749 
//
750 
// Instruction opcode groups (basic)
751 
//
752 
`define OR1200_OR32_J                 6'b000000
753 
`define OR1200_OR32_JAL               6'b000001
754 
`define OR1200_OR32_BNF               6'b000011
755 
`define OR1200_OR32_BF                6'b000100
756 
`define OR1200_OR32_NOP               6'b000101
757 
`define OR1200_OR32_MOVHI             6'b000110
758 
`define OR1200_OR32_XSYNC             6'b001000
759 
`define OR1200_OR32_RFE               6'b001001
760 
/* */
761 
`define OR1200_OR32_JR                6'b010001
762 
`define OR1200_OR32_JALR              6'b010010
763 
`define OR1200_OR32_MACI              6'b010011
764 
/* */
765 
`define OR1200_OR32_LWZ               6'b100001
766 
`define OR1200_OR32_LBZ               6'b100011
767 
`define OR1200_OR32_LBS               6'b100100
768 
`define OR1200_OR32_LHZ               6'b100101
769 
`define OR1200_OR32_LHS               6'b100110
770 
`define OR1200_OR32_ADDI              6'b100111
771 
`define OR1200_OR32_ADDIC             6'b101000
772 
`define OR1200_OR32_ANDI              6'b101001
773 
`define OR1200_OR32_ORI               6'b101010
774 
`define OR1200_OR32_XORI              6'b101011
775 
`define OR1200_OR32_MULI              6'b101100
776 
`define OR1200_OR32_MFSPR             6'b101101
777 
`define OR1200_OR32_SH_ROTI           6'b101110
778 
`define OR1200_OR32_SFXXI             6'b101111
779 
/* */
780 
`define OR1200_OR32_MTSPR             6'b110000
781 
`define OR1200_OR32_MACMSB            6'b110001
782 
/* */
783 
`define OR1200_OR32_SW                6'b110101
784 
`define OR1200_OR32_SB                6'b110110
785 
`define OR1200_OR32_SH                6'b110111
786 
`define OR1200_OR32_ALU               6'b111000
787 
`define OR1200_OR32_SFXX              6'b111001
788 
//`define OR1200_OR32_CUST5             6'b111100
789 
 
790 
 
791 
/////////////////////////////////////////////////////
792 
//
793 
// Exceptions
794 
//
795 
 
796 
//
797 
// Exception vectors per OR1K architecture:
798 
// 0xPPPPP100 - reset
799 
// 0xPPPPP200 - bus error
800 
// ... etc
801 
// where P represents exception prefix.
802 
//
803 
// Exception vectors can be customized as per
804 
// the following formula:
805 
// 0xPPPPPNVV - exception N
806 
//
807 
// P represents exception prefix
808 
// N represents exception N
809 
// VV represents length of the individual vector space,
810 
//   usually it is 8 bits wide and starts with all bits zero
811 
//
812 
 
813 
//
814 
// PPPPP and VV parts
815 
//
816 
// Sum of these two defines needs to be 28
817 
//
818 
`define OR1200_EXCEPT_EPH0_P 20'h00000
819 
`define OR1200_EXCEPT_EPH1_P 20'hF0000
820 
`define OR1200_EXCEPT_V            8'h00
821 
 
822 
//
823 
// N part width
824 
//
825 
`define OR1200_EXCEPT_WIDTH 4
826 
 
827 
//
828 
// Definition of exception vectors
829 
//
830 
// To avoid implementation of a certain exception,
831 
// simply comment out corresponding line
832 
//
833 
`define OR1200_EXCEPT_UNUSED            `OR1200_EXCEPT_WIDTH'hf
834 
`define OR1200_EXCEPT_TRAP              `OR1200_EXCEPT_WIDTH'he
835 
`define OR1200_EXCEPT_BREAK             `OR1200_EXCEPT_WIDTH'hd
836 
`define OR1200_EXCEPT_SYSCALL           `OR1200_EXCEPT_WIDTH'hc
837 
`define OR1200_EXCEPT_RANGE             `OR1200_EXCEPT_WIDTH'hb
838 
`define OR1200_EXCEPT_ITLBMISS          `OR1200_EXCEPT_WIDTH'ha
839 
`define OR1200_EXCEPT_DTLBMISS          `OR1200_EXCEPT_WIDTH'h9
840 
`define OR1200_EXCEPT_INT               `OR1200_EXCEPT_WIDTH'h8
841 
`define OR1200_EXCEPT_ILLEGAL           `OR1200_EXCEPT_WIDTH'h7
842 
`define OR1200_EXCEPT_ALIGN             `OR1200_EXCEPT_WIDTH'h6
843 
`define OR1200_EXCEPT_TICK              `OR1200_EXCEPT_WIDTH'h5
844 
`define OR1200_EXCEPT_IPF               `OR1200_EXCEPT_WIDTH'h4
845 
`define OR1200_EXCEPT_DPF               `OR1200_EXCEPT_WIDTH'h3
846 
`define OR1200_EXCEPT_BUSERR            `OR1200_EXCEPT_WIDTH'h2
847 
`define OR1200_EXCEPT_RESET             `OR1200_EXCEPT_WIDTH'h1
848 
`define OR1200_EXCEPT_NONE              `OR1200_EXCEPT_WIDTH'h0
849 
 
850 
 
851 
/////////////////////////////////////////////////////
852 
//
853 
// SPR groups
854 
//
855 
 
856 
// Bits that define the group
857 
`define OR1200_SPR_GROUP_BITS   15:11
858 
 
859 
// Width of the group bits
860 
`define OR1200_SPR_GROUP_WIDTH  5
861 
 
862 
// Bits that define offset inside the group
863 
`define OR1200_SPR_OFS_BITS 10:0
864 
 
865 
// List of groups
866 
`define OR1200_SPR_GROUP_SYS    5'd00
867 
`define OR1200_SPR_GROUP_DMMU   5'd01
868 
`define OR1200_SPR_GROUP_IMMU   5'd02
869 
`define OR1200_SPR_GROUP_DC     5'd03
870 
`define OR1200_SPR_GROUP_IC     5'd04
871 
`define OR1200_SPR_GROUP_MAC    5'd05
872 
`define OR1200_SPR_GROUP_DU     5'd06
873 
`define OR1200_SPR_GROUP_PM     5'd08
874 
`define OR1200_SPR_GROUP_PIC    5'd09
875 
`define OR1200_SPR_GROUP_TT     5'd10
876 
 
877 
 
878 
/////////////////////////////////////////////////////
879 
//
880 
// System group
881 
//
882 
 
883 
//
884 
// System registers
885 
//
886 
`define OR1200_SPR_CFGR         7'd0
887 
`define OR1200_SPR_RF           6'd32   // 1024 >> 5
888 
`define OR1200_SPR_NPC          11'd16
889 
`define OR1200_SPR_SR           11'd17
890 
`define OR1200_SPR_PPC          11'd18
891 
`define OR1200_SPR_EPCR         11'd32
892 
`define OR1200_SPR_EEAR         11'd48
893 
`define OR1200_SPR_ESR          11'd64
894 
 
895 
//
896 
// SR bits
897 
//
898 
`define OR1200_SR_WIDTH 16
899 
`define OR1200_SR_SM   0
900 
`define OR1200_SR_TEE  1
901 
`define OR1200_SR_IEE  2
902 
`define OR1200_SR_DCE  3
903 
`define OR1200_SR_ICE  4
904 
`define OR1200_SR_DME  5
905 
`define OR1200_SR_IME  6
906 
`define OR1200_SR_LEE  7
907 
`define OR1200_SR_CE   8
908 
`define OR1200_SR_F    9
909 
`define OR1200_SR_CY   10       // Unused
910 
`define OR1200_SR_OV   11       // Unused
911 
`define OR1200_SR_OVE  12       // Unused
912 
`define OR1200_SR_DSX  13       // Unused
913 
`define OR1200_SR_EPH  14
914 
`define OR1200_SR_FO   15
915 
`define OR1200_SR_CID  31:28    // Unimplemented
916 
 
917 
//
918 
// Bits that define offset inside the group
919 
//
920 
`define OR1200_SPROFS_BITS 10:0
921 
 
922 
//
923 
// Default Exception Prefix
924 
//
925 
// 1'b0 - OR1200_EXCEPT_EPH0_P (0x0000_0000)
926 
// 1'b1 - OR1200_EXCEPT_EPH1_P (0xF000_0000)
927 
//
928 
`define OR1200_SR_EPH_DEF       1'b1
929 
 
930 
/////////////////////////////////////////////////////
931 
//
932 
// Power Management (PM)
933 
//
934 
 
935 
// Define it if you want PM implemented
936 
`define OR1200_PM_IMPLEMENTED
937 
 
938 
// Bit positions inside PMR (don't change)
939 
`define OR1200_PM_PMR_SDF 3:0
940 
`define OR1200_PM_PMR_DME 4
941 
`define OR1200_PM_PMR_SME 5
942 
`define OR1200_PM_PMR_DCGE 6
943 
`define OR1200_PM_PMR_UNUSED 31:7
944 
 
945 
// PMR offset inside PM group of registers
946 
`define OR1200_PM_OFS_PMR 11'b0
947 
 
948 
// PM group
949 
`define OR1200_SPRGRP_PM 5'd8
950 
 
951 
// Define if PMR can be read/written at any address inside PM group
952 
`define OR1200_PM_PARTIAL_DECODING
953 
 
954 
// Define if reading PMR is allowed
955 
`define OR1200_PM_READREGS
956 
 
957 
// Define if unused PMR bits should be zero
958 
`define OR1200_PM_UNUSED_ZERO
959 
 
960 
 
961 
/////////////////////////////////////////////////////
962 
//
963 
// Debug Unit (DU)
964 
//
965 
 
966 
// Define it if you want DU implemented
967 
`define OR1200_DU_IMPLEMENTED
968 
 
969 
//
970 
// Define if you want HW Breakpoints
971 
// (if HW breakpoints are not implemented
972 
// only default software trapping is
973 
// possible with l.trap insn - this is
974 
// however already enough for use
975 
// with or32 gdb)
976 
//
977 
//`define OR1200_DU_HWBKPTS
978 
 
979 
// Number of DVR/DCR pairs if HW breakpoints enabled
980 
`define OR1200_DU_DVRDCR_PAIRS 8
981 
 
982 
// Define if you want trace buffer
983 
//`define OR1200_DU_TB_IMPLEMENTED
984 
 
985 
//
986 
// Address offsets of DU registers inside DU group
987 
//
988 
// To not implement a register, doq not define its address
989 
//
990 
`ifdef OR1200_DU_HWBKPTS
991 
`define OR1200_DU_DVR0          11'd0
992 
`define OR1200_DU_DVR1          11'd1
993 
`define OR1200_DU_DVR2          11'd2
994 
`define OR1200_DU_DVR3          11'd3
995 
`define OR1200_DU_DVR4          11'd4
996 
`define OR1200_DU_DVR5          11'd5
997 
`define OR1200_DU_DVR6          11'd6
998 
`define OR1200_DU_DVR7          11'd7
999 
`define OR1200_DU_DCR0          11'd8
1000 
`define OR1200_DU_DCR1          11'd9
1001 
`define OR1200_DU_DCR2          11'd10
1002 
`define OR1200_DU_DCR3          11'd11
1003 
`define OR1200_DU_DCR4          11'd12
1004 
`define OR1200_DU_DCR5          11'd13
1005 
`define OR1200_DU_DCR6          11'd14
1006 
`define OR1200_DU_DCR7          11'd15
1007 
`endif
1008 
`define OR1200_DU_DMR1          11'd16
1009 
`ifdef OR1200_DU_HWBKPTS
1010 
`define OR1200_DU_DMR2          11'd17
1011 
`define OR1200_DU_DWCR0         11'd18
1012 
`define OR1200_DU_DWCR1         11'd19
1013 
`endif
1014 
`define OR1200_DU_DSR           11'd20
1015 
`define OR1200_DU_DRR           11'd21
1016 
`ifdef OR1200_DU_TB_IMPLEMENTED
1017 
`define OR1200_DU_TBADR         11'h0ff
1018 
`define OR1200_DU_TBIA          11'h1xx
1019 
`define OR1200_DU_TBIM          11'h2xx
1020 
`define OR1200_DU_TBAR          11'h3xx
1021 
`define OR1200_DU_TBTS          11'h4xx
1022 
`endif
1023 
 
1024 
// Position of offset bits inside SPR address
1025 
`define OR1200_DUOFS_BITS       10:0
1026 
 
1027 
// DCR bits
1028 
`define OR1200_DU_DCR_DP        0
1029 
`define OR1200_DU_DCR_CC        3:1
1030 
`define OR1200_DU_DCR_SC        4
1031 
`define OR1200_DU_DCR_CT        7:5
1032 
 
1033 
// DMR1 bits
1034 
`define OR1200_DU_DMR1_CW0      1:0
1035 
`define OR1200_DU_DMR1_CW1      3:2
1036 
`define OR1200_DU_DMR1_CW2      5:4
1037 
`define OR1200_DU_DMR1_CW3      7:6
1038 
`define OR1200_DU_DMR1_CW4      9:8
1039 
`define OR1200_DU_DMR1_CW5      11:10
1040 
`define OR1200_DU_DMR1_CW6      13:12
1041 
`define OR1200_DU_DMR1_CW7      15:14
1042 
`define OR1200_DU_DMR1_CW8      17:16
1043 
`define OR1200_DU_DMR1_CW9      19:18
1044 
`define OR1200_DU_DMR1_CW10     21:20
1045 
`define OR1200_DU_DMR1_ST       22
1046 
`define OR1200_DU_DMR1_BT       23
1047 
`define OR1200_DU_DMR1_DXFW     24
1048 
`define OR1200_DU_DMR1_ETE      25
1049 
 
1050 
// DMR2 bits
1051 
`define OR1200_DU_DMR2_WCE0     0
1052 
`define OR1200_DU_DMR2_WCE1     1
1053 
`define OR1200_DU_DMR2_AWTC     12:2
1054 
`define OR1200_DU_DMR2_WGB      23:13
1055 
 
1056 
// DWCR bits
1057 
`define OR1200_DU_DWCR_COUNT    15:0
1058 
`define OR1200_DU_DWCR_MATCH    31:16
1059 
 
1060 
// DSR bits
1061 
`define OR1200_DU_DSR_WIDTH     14
1062 
`define OR1200_DU_DSR_RSTE      0
1063 
`define OR1200_DU_DSR_BUSEE     1
1064 
`define OR1200_DU_DSR_DPFE      2
1065 
`define OR1200_DU_DSR_IPFE      3
1066 
`define OR1200_DU_DSR_TTE       4
1067 
`define OR1200_DU_DSR_AE        5
1068 
`define OR1200_DU_DSR_IIE       6
1069 
`define OR1200_DU_DSR_IE        7
1070 
`define OR1200_DU_DSR_DME       8
1071 
`define OR1200_DU_DSR_IME       9
1072 
`define OR1200_DU_DSR_RE        10
1073 
`define OR1200_DU_DSR_SCE       11
1074 
`define OR1200_DU_DSR_BE        12
1075 
`define OR1200_DU_DSR_TE        13
1076 
 
1077 
// DRR bits
1078 
`define OR1200_DU_DRR_RSTE      0
1079 
`define OR1200_DU_DRR_BUSEE     1
1080 
`define OR1200_DU_DRR_DPFE      2
1081 
`define OR1200_DU_DRR_IPFE      3
1082 
`define OR1200_DU_DRR_TTE       4
1083 
`define OR1200_DU_DRR_AE        5
1084 
`define OR1200_DU_DRR_IIE       6
1085 
`define OR1200_DU_DRR_IE        7
1086 
`define OR1200_DU_DRR_DME       8
1087 
`define OR1200_DU_DRR_IME       9
1088 
`define OR1200_DU_DRR_RE        10
1089 
`define OR1200_DU_DRR_SCE       11
1090 
`define OR1200_DU_DRR_BE        12
1091 
`define OR1200_DU_DRR_TE        13
1092 
 
1093 
// Define if reading DU regs is allowed
1094 
`define OR1200_DU_READREGS
1095 
 
1096 
// Define if unused DU registers bits should be zero
1097 
`define OR1200_DU_UNUSED_ZERO
1098 
 
1099 
// Define if IF/LSU status is not needed by devel i/f
1100 
`define OR1200_DU_STATUS_UNIMPLEMENTED
1101 
 
1102 
/////////////////////////////////////////////////////
1103 
//
1104 
// Programmable Interrupt Controller (PIC)
1105 
//
1106 
 
1107 
// Define it if you want PIC implemented
1108 
`define OR1200_PIC_IMPLEMENTED
1109 
 
1110 
// Define number of interrupt inputs (2-31)
1111 
`define OR1200_PIC_INTS 20
1112 
 
1113 
// Address offsets of PIC registers inside PIC group
1114 
`define OR1200_PIC_OFS_PICMR 2'd0
1115 
`define OR1200_PIC_OFS_PICSR 2'd2
1116 
 
1117 
// Position of offset bits inside SPR address
1118 
`define OR1200_PICOFS_BITS 1:0
1119 
 
1120 
// Define if you want these PIC registers to be implemented
1121 
`define OR1200_PIC_PICMR
1122 
`define OR1200_PIC_PICSR
1123 
 
1124 
// Define if reading PIC registers is allowed
1125 
`define OR1200_PIC_READREGS
1126 
 
1127 
// Define if unused PIC register bits should be zero
1128 
`define OR1200_PIC_UNUSED_ZERO
1129 
 
1130 
 
1131 
/////////////////////////////////////////////////////
1132 
//
1133 
// Tick Timer (TT)
1134 
//
1135 
 
1136 
// Define it if you want TT implemented
1137 
`define OR1200_TT_IMPLEMENTED
1138 
 
1139 
// Address offsets of TT registers inside TT group
1140 
`define OR1200_TT_OFS_TTMR 1'd0
1141 
`define OR1200_TT_OFS_TTCR 1'd1
1142 
 
1143 
// Position of offset bits inside SPR group
1144 
`define OR1200_TTOFS_BITS 0
1145 
 
1146 
// Define if you want these TT registers to be implemented
1147 
`define OR1200_TT_TTMR
1148 
`define OR1200_TT_TTCR
1149 
 
1150 
// TTMR bits
1151 
`define OR1200_TT_TTMR_TP 27:0
1152 
`define OR1200_TT_TTMR_IP 28
1153 
`define OR1200_TT_TTMR_IE 29
1154 
`define OR1200_TT_TTMR_M 31:30
1155 
 
1156 
// Define if reading TT registers is allowed
1157 
`define OR1200_TT_READREGS
1158 
 
1159 
 
1160 
//////////////////////////////////////////////
1161 
//
1162 
// MAC
1163 
//
1164 
`define OR1200_MAC_ADDR         0        // MACLO 0xxxxxxxx1, MACHI 0xxxxxxxx0
1165 
`define OR1200_MAC_SPR_WE               // Define if MACLO/MACHI are SPR writable
1166 
 
1167 
//
1168 
// Shift {MACHI,MACLO} into destination register when executing l.macrc
1169 
//
1170 
// According to architecture manual there is no shift, so default value is 0.
1171 
//
1172 
// However the implementation has deviated in this from the arch manual and had hard coded shift by 28 bits which
1173 
// is a useful optimization for MP3 decoding (if using libmad fixed point library). Shifts are no longer
1174 
// default setup, but if you need to remain backward compatible, define your shift bits, which were normally
1175 
// dest_GPR = {MACHI,MACLO}[59:28]
1176 
`define OR1200_MAC_SHIFTBY      0        // 0 = According to arch manual, 28 = obsolete backward compatibility
1177 
 
1178 
 
1179 
//////////////////////////////////////////////
1180 
//
1181 
// Data MMU (DMMU)
1182 
//
1183 
 
1184 
//
1185 
// Address that selects between TLB TR and MR
1186 
//
1187 
`define OR1200_DTLB_TM_ADDR     7
1188 
 
1189 
//
1190 
// DTLBMR fields
1191 
//
1192 
`define OR1200_DTLBMR_V_BITS    0
1193 
`define OR1200_DTLBMR_CID_BITS  4:1
1194 
`define OR1200_DTLBMR_RES_BITS  11:5
1195 
`define OR1200_DTLBMR_VPN_BITS  31:13
1196 
 
1197 
//
1198 
// DTLBTR fields
1199 
//
1200 
`define OR1200_DTLBTR_CC_BITS   0
1201 
`define OR1200_DTLBTR_CI_BITS   1
1202 
`define OR1200_DTLBTR_WBC_BITS  2
1203 
`define OR1200_DTLBTR_WOM_BITS  3
1204 
`define OR1200_DTLBTR_A_BITS    4
1205 
`define OR1200_DTLBTR_D_BITS    5
1206 
`define OR1200_DTLBTR_URE_BITS  6
1207 
`define OR1200_DTLBTR_UWE_BITS  7
1208 
`define OR1200_DTLBTR_SRE_BITS  8
1209 
`define OR1200_DTLBTR_SWE_BITS  9
1210 
`define OR1200_DTLBTR_RES_BITS  11:10
1211 
`define OR1200_DTLBTR_PPN_BITS  31:13
1212 
 
1213 
//
1214 
// DTLB configuration
1215 
//
1216 
`define OR1200_DMMU_PS          13                                      // 13 for 8KB page size
1217 
`define OR1200_DTLB_INDXW       6                                       // 6 for 64 entry DTLB  7 for 128 entries
1218 
`define OR1200_DTLB_INDXL       `OR1200_DMMU_PS                         // 13                   13
1219 
`define OR1200_DTLB_INDXH       `OR1200_DMMU_PS+`OR1200_DTLB_INDXW-1    // 18                   19
1220 
`define OR1200_DTLB_INDX        `OR1200_DTLB_INDXH:`OR1200_DTLB_INDXL   // 18:13                19:13
1221 
`define OR1200_DTLB_TAGW        32-`OR1200_DTLB_INDXW-`OR1200_DMMU_PS   // 13                   12
1222 
`define OR1200_DTLB_TAGL        `OR1200_DTLB_INDXH+1                    // 19                   20
1223 
`define OR1200_DTLB_TAG         31:`OR1200_DTLB_TAGL                    // 31:19                31:20
1224 
`define OR1200_DTLBMRW          `OR1200_DTLB_TAGW+1                     // +1 because of V bit
1225 
`define OR1200_DTLBTRW          32-`OR1200_DMMU_PS+5                    // +5 because of protection bits and CI
1226 
 
1227 
//
1228 
// Cache inhibit while DMMU is not enabled/implemented
1229 
//
1230 
// cache inhibited 0GB-4GB              1'b1
1231 
// cache inhibited 0GB-2GB              !dcpu_adr_i[31]
1232 
// cache inhibited 0GB-1GB 2GB-3GB      !dcpu_adr_i[30]
1233 
// cache inhibited 1GB-2GB 3GB-4GB      dcpu_adr_i[30]
1234 
// cache inhibited 2GB-4GB (default)    dcpu_adr_i[31]
1235 
// cached 0GB-4GB                       1'b0
1236 
//
1237 
`define OR1200_DMMU_CI                  dcpu_adr_i[31]
1238 
 
1239 
 
1240 
//////////////////////////////////////////////
1241 
//
1242 
// Insn MMU (IMMU)
1243 
//
1244 
 
1245 
//
1246 
// Address that selects between TLB TR and MR
1247 
//
1248 
`define OR1200_ITLB_TM_ADDR     7
1249 
 
1250 
//
1251 
// ITLBMR fields
1252 
//
1253 
`define OR1200_ITLBMR_V_BITS    0
1254 
`define OR1200_ITLBMR_CID_BITS  4:1
1255 
`define OR1200_ITLBMR_RES_BITS  11:5
1256 
`define OR1200_ITLBMR_VPN_BITS  31:13
1257 
 
1258 
//
1259 
// ITLBTR fields
1260 
//
1261 
`define OR1200_ITLBTR_CC_BITS   0
1262 
`define OR1200_ITLBTR_CI_BITS   1
1263 
`define OR1200_ITLBTR_WBC_BITS  2
1264 
`define OR1200_ITLBTR_WOM_BITS  3
1265 
`define OR1200_ITLBTR_A_BITS    4
1266 
`define OR1200_ITLBTR_D_BITS    5
1267 
`define OR1200_ITLBTR_SXE_BITS  6
1268 
`define OR1200_ITLBTR_UXE_BITS  7
1269 
`define OR1200_ITLBTR_RES_BITS  11:8
1270 
`define OR1200_ITLBTR_PPN_BITS  31:13
1271 
 
1272 
//
1273 
// ITLB configuration
1274 
//
1275 
`define OR1200_IMMU_PS          13                                      // 13 for 8KB page size
1276 
`define OR1200_ITLB_INDXW       6                                       // 6 for 64 entry ITLB  7 for 128 entries
1277 
`define OR1200_ITLB_INDXL       `OR1200_IMMU_PS                         // 13                   13
1278 
`define OR1200_ITLB_INDXH       `OR1200_IMMU_PS+`OR1200_ITLB_INDXW-1    // 18                   19
1279 
`define OR1200_ITLB_INDX        `OR1200_ITLB_INDXH:`OR1200_ITLB_INDXL   // 18:13                19:13
1280 
`define OR1200_ITLB_TAGW        32-`OR1200_ITLB_INDXW-`OR1200_IMMU_PS   // 13                   12
1281 
`define OR1200_ITLB_TAGL        `OR1200_ITLB_INDXH+1                    // 19                   20
1282 
`define OR1200_ITLB_TAG         31:`OR1200_ITLB_TAGL                    // 31:19                31:20
1283 
`define OR1200_ITLBMRW          `OR1200_ITLB_TAGW+1                     // +1 because of V bit
1284 
`define OR1200_ITLBTRW          32-`OR1200_IMMU_PS+3                    // +3 because of protection bits and CI
1285 
 
1286 
//
1287 
// Cache inhibit while IMMU is not enabled/implemented
1288 
// Note: all combinations that use icpu_adr_i cause async loop
1289 
//
1290 
// cache inhibited 0GB-4GB              1'b1
1291 
// cache inhibited 0GB-2GB              !icpu_adr_i[31]
1292 
// cache inhibited 0GB-1GB 2GB-3GB      !icpu_adr_i[30]
1293 
// cache inhibited 1GB-2GB 3GB-4GB      icpu_adr_i[30]
1294 
// cache inhibited 2GB-4GB (default)    icpu_adr_i[31]
1295 
// cached 0GB-4GB                       1'b0
1296 
//
1297 
`define OR1200_IMMU_CI                  1'b0
1298 
 
1299 
 
1300 
/////////////////////////////////////////////////
1301 
//
1302 
// Insn cache (IC)
1303 
//
1304 
 
1305 
// 3 for 8 bytes, 4 for 16 bytes etc
1306 
`define OR1200_ICLS             4
1307 
 
1308 
//
1309 
// IC configurations
1310 
//
1311 
`ifdef OR1200_IC_1W_512B
1312 
`define OR1200_ICSIZE   9     // 512
1313 
`define OR1200_ICINDX   `OR1200_ICSIZE-2 // 7
1314 
`define OR1200_ICINDXH  `OR1200_ICSIZE-1 // 8
1315 
`define OR1200_ICTAGL   `OR1200_ICINDXH+1 // 9
1316 
`define OR1200_ICTAG    `OR1200_ICSIZE-`OR1200_ICLS // 5
1317 
`define OR1200_ICTAG_W  24
1318 
`endif
1319 
`ifdef OR1200_IC_1W_4KB
1320 
`define OR1200_ICSIZE                   12                      // 4096
1321 
`define OR1200_ICINDX                   `OR1200_ICSIZE-2        // 10
1322 
`define OR1200_ICINDXH                  `OR1200_ICSIZE-1        // 11
1323 
`define OR1200_ICTAGL                   `OR1200_ICINDXH+1       // 12
1324 
`define OR1200_ICTAG                    `OR1200_ICSIZE-`OR1200_ICLS     // 8
1325 
`define OR1200_ICTAG_W                  21
1326 
`endif
1327 
`ifdef OR1200_IC_1W_8KB
1328 
`define OR1200_ICSIZE                   13                      // 8192
1329 
`define OR1200_ICINDX                   `OR1200_ICSIZE-2        // 11
1330 
`define OR1200_ICINDXH                  `OR1200_ICSIZE-1        // 12
1331 
`define OR1200_ICTAGL                   `OR1200_ICINDXH+1       // 13
1332 
`define OR1200_ICTAG                    `OR1200_ICSIZE-`OR1200_ICLS     // 9
1333 
`define OR1200_ICTAG_W                  20
1334 
`endif
1335 
 
1336 
 
1337 
/////////////////////////////////////////////////
1338 
//
1339 
// Data cache (DC)
1340 
//
1341 
 
1342 
// 3 for 8 bytes, 4 for 16 bytes etc
1343 
`define OR1200_DCLS             4
1344 
 
1345 
// Define to perform store refill (potential performance penalty)
1346 
// `define OR1200_DC_STORE_REFILL
1347 
 
1348 
//
1349 
// DC configurations
1350 
//
1351 
`ifdef OR1200_DC_1W_4KB
1352 
`define OR1200_DCSIZE                   12                      // 4096
1353 
`define OR1200_DCINDX                   `OR1200_DCSIZE-2        // 10
1354 
`define OR1200_DCINDXH                  `OR1200_DCSIZE-1        // 11
1355 
`define OR1200_DCTAGL                   `OR1200_DCINDXH+1       // 12
1356 
`define OR1200_DCTAG                    `OR1200_DCSIZE-`OR1200_DCLS     // 8
1357 
`define OR1200_DCTAG_W                  21
1358 
`endif
1359 
`ifdef OR1200_DC_1W_8KB
1360 
`define OR1200_DCSIZE                   13                      // 8192
1361 
`define OR1200_DCINDX                   `OR1200_DCSIZE-2        // 11
1362 
`define OR1200_DCINDXH                  `OR1200_DCSIZE-1        // 12
1363 
`define OR1200_DCTAGL                   `OR1200_DCINDXH+1       // 13
1364 
`define OR1200_DCTAG                    `OR1200_DCSIZE-`OR1200_DCLS     // 9
1365 
`define OR1200_DCTAG_W                  20
1366 
`endif
1367 
 
1368 
/////////////////////////////////////////////////
1369 
//
1370 
// Store buffer (SB)
1371 
//
1372 
 
1373 
//
1374 
// Store buffer
1375 
//
1376 
// It will improve performance by "caching" CPU stores
1377 
// using store buffer. This is most important for function
1378 
// prologues because DC can only work in write though mode
1379 
// and all stores would have to complete external WB writes
1380 
// to memory.
1381 
// Store buffer is between DC and data BIU.
1382 
// All stores will be stored into store buffer and immediately
1383 
// completed by the CPU, even though actual external writes
1384 
// will be performed later. As a consequence store buffer masks
1385 
// all data bus errors related to stores (data bus errors
1386 
// related to loads are delivered normally).
1387 
// All pending CPU loads will wait until store buffer is empty to
1388 
// ensure strict memory model. Right now this is necessary because
1389 
// we don't make destinction between cached and cache inhibited
1390 
// address space, so we simply empty store buffer until loads
1391 
// can begin.
1392 
//
1393 
// It makes design a bit bigger, depending what is the number of
1394 
// entries in SB FIFO. Number of entries can be changed further
1395 
// down.
1396 
//
1397 
//`define OR1200_SB_IMPLEMENTED
1398 
 
1399 
//
1400 
// Number of store buffer entries
1401 
//
1402 
// Verified number of entries are 4 and 8 entries
1403 
// (2 and 3 for OR1200_SB_LOG). OR1200_SB_ENTRIES must
1404 
// always match 2**OR1200_SB_LOG.
1405 
// To disable store buffer, undefine
1406 
// OR1200_SB_IMPLEMENTED.
1407 
//
1408 
`define OR1200_SB_LOG           2       // 2 or 3
1409 
`define OR1200_SB_ENTRIES       4       // 4 or 8
1410 
 
1411 
 
1412 
/////////////////////////////////////////////////
1413 
//
1414 
// Quick Embedded Memory (QMEM)
1415 
//
1416 
 
1417 
//
1418 
// Quick Embedded Memory
1419 
//
1420 
// Instantiation of dedicated insn/data memory (RAM or ROM).
1421 
// Insn fetch has effective throughput 1insn / clock cycle.
1422 
// Data load takes two clock cycles / access, data store
1423 
// takes 1 clock cycle / access (if there is no insn fetch)).
1424 
// Memory instantiation is shared between insn and data,
1425 
// meaning if insn fetch are performed, data load/store
1426 
// performance will be lower.
1427 
//
1428 
// Main reason for QMEM is to put some time critical functions
1429 
// into this memory and to have predictable and fast access
1430 
// to these functions. (soft fpu, context switch, exception
1431 
// handlers, stack, etc)
1432 
//
1433 
// It makes design a bit bigger and slower. QMEM sits behind
1434 
// IMMU/DMMU so all addresses are physical (so the MMUs can be
1435 
// used with QMEM and QMEM is seen by the CPU just like any other
1436 
// memory in the system). IC/DC are sitting behind QMEM so the
1437 
// whole design timing might be worse with QMEM implemented.
1438 
//
1439 
`define OR1200_QMEM_IMPLEMENTED
1440 
 
1441 
//
1442 
// Base address and mask of QMEM
1443 
//
1444 
// Base address defines first address of QMEM. Mask defines
1445 
// QMEM range in address space. Actual size of QMEM is however
1446 
// determined with instantiated RAM/ROM. However bigger
1447 
// mask will reserve more address space for QMEM, but also
1448 
// make design faster, while more tight mask will take
1449 
// less address space but also make design slower. If
1450 
// instantiated RAM/ROM is smaller than space reserved with
1451 
// the mask, instatiated RAM/ROM will also be shadowed
1452 
// at higher addresses in reserved space.
1453 
//
1454 
`define OR1200_QMEM_IADDR       32'h0080_0000
1455 
`define OR1200_QMEM_IMASK       32'hfff0_0000   // Max QMEM size 1MB
1456 
`define OR1200_QMEM_DADDR  32'h0080_0000
1457 
`define OR1200_QMEM_DMASK  32'hfff0_0000 // Max QMEM size 1MB
1458 
 
1459 
//
1460 
// QMEM interface byte-select capability
1461 
//
1462 
// To enable qmem_sel* ports, define this macro.
1463 
//
1464 
//`define OR1200_QMEM_BSEL
1465 
 
1466 
//
1467 
// QMEM interface acknowledge
1468 
//
1469 
// To enable qmem_ack port, define this macro.
1470 
//
1471 
//`define OR1200_QMEM_ACK
1472 
 
1473 
/////////////////////////////////////////////////////
1474 
//
1475 
// VR, UPR and Configuration Registers
1476 
//
1477 
//
1478 
// VR, UPR and configuration registers are optional. If
1479 
// implemented, operating system can automatically figure
1480 
// out how to use the processor because it knows
1481 
// what units are available in the processor and how they
1482 
// are configured.
1483 
//
1484 
// This section must be last in or1200_defines.v file so
1485 
// that all units are already configured and thus
1486 
// configuration registers are properly set.
1487 
//
1488 
 
1489 
// Define if you want configuration registers implemented
1490 
`define OR1200_CFGR_IMPLEMENTED
1491 
 
1492 
// Define if you want full address decode inside SYS group
1493 
`define OR1200_SYS_FULL_DECODE
1494 
 
1495 
// Offsets of VR, UPR and CFGR registers
1496 
`define OR1200_SPRGRP_SYS_VR            4'h0
1497 
`define OR1200_SPRGRP_SYS_UPR           4'h1
1498 
`define OR1200_SPRGRP_SYS_CPUCFGR       4'h2
1499 
`define OR1200_SPRGRP_SYS_DMMUCFGR      4'h3
1500 
`define OR1200_SPRGRP_SYS_IMMUCFGR      4'h4
1501 
`define OR1200_SPRGRP_SYS_DCCFGR        4'h5
1502 
`define OR1200_SPRGRP_SYS_ICCFGR        4'h6
1503 
`define OR1200_SPRGRP_SYS_DCFGR 4'h7
1504 
 
1505 
// VR fields
1506 
`define OR1200_VR_REV_BITS              5:0
1507 
`define OR1200_VR_RES1_BITS             15:6
1508 
`define OR1200_VR_CFG_BITS              23:16
1509 
`define OR1200_VR_VER_BITS              31:24
1510 
 
1511 
// VR values
1512 
`define OR1200_VR_REV                   6'h01
1513 
`define OR1200_VR_RES1                  10'h000
1514 
`define OR1200_VR_CFG                   8'h00
1515 
`define OR1200_VR_VER                   8'h12
1516 
 
1517 
// UPR fields
1518 
`define OR1200_UPR_UP_BITS              0
1519 
`define OR1200_UPR_DCP_BITS             1
1520 
`define OR1200_UPR_ICP_BITS             2
1521 
`define OR1200_UPR_DMP_BITS             3
1522 
`define OR1200_UPR_IMP_BITS             4
1523 
`define OR1200_UPR_MP_BITS              5
1524 
`define OR1200_UPR_DUP_BITS             6
1525 
`define OR1200_UPR_PCUP_BITS            7
1526 
`define OR1200_UPR_PMP_BITS             8
1527 
`define OR1200_UPR_PICP_BITS            9
1528 
`define OR1200_UPR_TTP_BITS             10
1529 
`define OR1200_UPR_RES1_BITS            23:11
1530 
`define OR1200_UPR_CUP_BITS             31:24
1531 
 
1532 
// UPR values
1533 
`define OR1200_UPR_UP                   1'b1
1534 
`ifdef OR1200_NO_DC
1535 
`define OR1200_UPR_DCP                  1'b0
1536 
`else
1537 
`define OR1200_UPR_DCP                  1'b1
1538 
`endif
1539 
`ifdef OR1200_NO_IC
1540 
`define OR1200_UPR_ICP                  1'b0
1541 
`else
1542 
`define OR1200_UPR_ICP                  1'b1
1543 
`endif
1544 
`ifdef OR1200_NO_DMMU
1545 
`define OR1200_UPR_DMP                  1'b0
1546 
`else
1547 
`define OR1200_UPR_DMP                  1'b1
1548 
`endif
1549 
`ifdef OR1200_NO_IMMU
1550 
`define OR1200_UPR_IMP                  1'b0
1551 
`else
1552 
`define OR1200_UPR_IMP                  1'b1
1553 
`endif
1554 
`define OR1200_UPR_MP                   1'b1    // MAC always present
1555 
`ifdef OR1200_DU_IMPLEMENTED
1556 
`define OR1200_UPR_DUP                  1'b1
1557 
`else
1558 
`define OR1200_UPR_DUP                  1'b0
1559 
`endif
1560 
`define OR1200_UPR_PCUP                 1'b0    // Performance counters not present
1561 
`ifdef OR1200_DU_IMPLEMENTED
1562 
`define OR1200_UPR_PMP                  1'b1
1563 
`else
1564 
`define OR1200_UPR_PMP                  1'b0
1565 
`endif
1566 
`ifdef OR1200_DU_IMPLEMENTED
1567 
`define OR1200_UPR_PICP                 1'b1
1568 
`else
1569 
`define OR1200_UPR_PICP                 1'b0
1570 
`endif
1571 
`ifdef OR1200_DU_IMPLEMENTED
1572 
`define OR1200_UPR_TTP                  1'b1
1573 
`else
1574 
`define OR1200_UPR_TTP                  1'b0
1575 
`endif
1576 
`define OR1200_UPR_RES1                 13'h0000
1577 
`define OR1200_UPR_CUP                  8'h00
1578 
 
1579 
// CPUCFGR fields
1580 
`define OR1200_CPUCFGR_NSGF_BITS        3:0
1581 
`define OR1200_CPUCFGR_HGF_BITS 4
1582 
`define OR1200_CPUCFGR_OB32S_BITS       5
1583 
`define OR1200_CPUCFGR_OB64S_BITS       6
1584 
`define OR1200_CPUCFGR_OF32S_BITS       7
1585 
`define OR1200_CPUCFGR_OF64S_BITS       8
1586 
`define OR1200_CPUCFGR_OV64S_BITS       9
1587 
`define OR1200_CPUCFGR_RES1_BITS        31:10
1588 
 
1589 
// CPUCFGR values
1590 
`define OR1200_CPUCFGR_NSGF             4'h0
1591 
`define OR1200_CPUCFGR_HGF              1'b0
1592 
`define OR1200_CPUCFGR_OB32S            1'b1
1593 
`define OR1200_CPUCFGR_OB64S            1'b0
1594 
`define OR1200_CPUCFGR_OF32S            1'b0
1595 
`define OR1200_CPUCFGR_OF64S            1'b0
1596 
`define OR1200_CPUCFGR_OV64S            1'b0
1597 
`define OR1200_CPUCFGR_RES1             22'h000000
1598 
 
1599 
// DMMUCFGR fields
1600 
`define OR1200_DMMUCFGR_NTW_BITS        1:0
1601 
`define OR1200_DMMUCFGR_NTS_BITS        4:2
1602 
`define OR1200_DMMUCFGR_NAE_BITS        7:5
1603 
`define OR1200_DMMUCFGR_CRI_BITS        8
1604 
`define OR1200_DMMUCFGR_PRI_BITS        9
1605 
`define OR1200_DMMUCFGR_TEIRI_BITS      10
1606 
`define OR1200_DMMUCFGR_HTR_BITS        11
1607 
`define OR1200_DMMUCFGR_RES1_BITS       31:12
1608 
 
1609 
// DMMUCFGR values
1610 
`ifdef OR1200_NO_DMMU
1611 
`define OR1200_DMMUCFGR_NTW             2'h0    // Irrelevant
1612 
`define OR1200_DMMUCFGR_NTS             3'h0    // Irrelevant
1613 
`define OR1200_DMMUCFGR_NAE             3'h0    // Irrelevant
1614 
`define OR1200_DMMUCFGR_CRI             1'b0    // Irrelevant
1615 
`define OR1200_DMMUCFGR_PRI             1'b0    // Irrelevant
1616 
`define OR1200_DMMUCFGR_TEIRI           1'b0    // Irrelevant
1617 
`define OR1200_DMMUCFGR_HTR             1'b0    // Irrelevant
1618 
`define OR1200_DMMUCFGR_RES1            20'h00000
1619 
`else
1620 
`define OR1200_DMMUCFGR_NTW             2'h0    // 1 TLB way
1621 
`define OR1200_DMMUCFGR_NTS 3'h`OR1200_DTLB_INDXW       // Num TLB sets
1622 
`define OR1200_DMMUCFGR_NAE             3'h0    // No ATB entries
1623 
`define OR1200_DMMUCFGR_CRI             1'b0    // No control register
1624 
`define OR1200_DMMUCFGR_PRI             1'b0    // No protection reg
1625 
`define OR1200_DMMUCFGR_TEIRI           1'b1    // TLB entry inv reg impl.
1626 
`define OR1200_DMMUCFGR_HTR             1'b0    // No HW TLB reload
1627 
`define OR1200_DMMUCFGR_RES1            20'h00000
1628 
`endif
1629 
 
1630 
// IMMUCFGR fields
1631 
`define OR1200_IMMUCFGR_NTW_BITS        1:0
1632 
`define OR1200_IMMUCFGR_NTS_BITS        4:2
1633 
`define OR1200_IMMUCFGR_NAE_BITS        7:5
1634 
`define OR1200_IMMUCFGR_CRI_BITS        8
1635 
`define OR1200_IMMUCFGR_PRI_BITS        9
1636 
`define OR1200_IMMUCFGR_TEIRI_BITS      10
1637 
`define OR1200_IMMUCFGR_HTR_BITS        11
1638 
`define OR1200_IMMUCFGR_RES1_BITS       31:12
1639 
 
1640 
// IMMUCFGR values
1641 
`ifdef OR1200_NO_IMMU
1642 
`define OR1200_IMMUCFGR_NTW             2'h0    // Irrelevant
1643 
`define OR1200_IMMUCFGR_NTS             3'h0    // Irrelevant
1644 
`define OR1200_IMMUCFGR_NAE             3'h0    // Irrelevant
1645 
`define OR1200_IMMUCFGR_CRI             1'b0    // Irrelevant
1646 
`define OR1200_IMMUCFGR_PRI             1'b0    // Irrelevant
1647 
`define OR1200_IMMUCFGR_TEIRI           1'b0    // Irrelevant
1648 
`define OR1200_IMMUCFGR_HTR             1'b0    // Irrelevant
1649 
`define OR1200_IMMUCFGR_RES1            20'h00000
1650 
`else
1651 
`define OR1200_IMMUCFGR_NTW             2'h0    // 1 TLB way
1652 
`define OR1200_IMMUCFGR_NTS 3'h`OR1200_ITLB_INDXW       // Num TLB sets
1653 
`define OR1200_IMMUCFGR_NAE             3'h0    // No ATB entry
1654 
`define OR1200_IMMUCFGR_CRI             1'b0    // No control reg
1655 
`define OR1200_IMMUCFGR_PRI             1'b0    // No protection reg
1656 
`define OR1200_IMMUCFGR_TEIRI           1'b1    // TLB entry inv reg impl
1657 
`define OR1200_IMMUCFGR_HTR             1'b0    // No HW TLB reload
1658 
`define OR1200_IMMUCFGR_RES1            20'h00000
1659 
`endif
1660 
 
1661 
// DCCFGR fields
1662 
`define OR1200_DCCFGR_NCW_BITS          2:0
1663 
`define OR1200_DCCFGR_NCS_BITS          6:3
1664 
`define OR1200_DCCFGR_CBS_BITS          7
1665 
`define OR1200_DCCFGR_CWS_BITS          8
1666 
`define OR1200_DCCFGR_CCRI_BITS         9
1667 
`define OR1200_DCCFGR_CBIRI_BITS        10
1668 
`define OR1200_DCCFGR_CBPRI_BITS        11
1669 
`define OR1200_DCCFGR_CBLRI_BITS        12
1670 
`define OR1200_DCCFGR_CBFRI_BITS        13
1671 
`define OR1200_DCCFGR_CBWBRI_BITS       14
1672 
`define OR1200_DCCFGR_RES1_BITS 31:15
1673 
 
1674 
// DCCFGR values
1675 
`ifdef OR1200_NO_DC
1676 
`define OR1200_DCCFGR_NCW               3'h0    // Irrelevant
1677 
`define OR1200_DCCFGR_NCS               4'h0    // Irrelevant
1678 
`define OR1200_DCCFGR_CBS               1'b0    // Irrelevant
1679 
`define OR1200_DCCFGR_CWS               1'b0    // Irrelevant
1680 
`define OR1200_DCCFGR_CCRI              1'b1    // Irrelevant
1681 
`define OR1200_DCCFGR_CBIRI             1'b1    // Irrelevant
1682 
`define OR1200_DCCFGR_CBPRI             1'b0    // Irrelevant
1683 
`define OR1200_DCCFGR_CBLRI             1'b0    // Irrelevant
1684 
`define OR1200_DCCFGR_CBFRI             1'b1    // Irrelevant
1685 
`define OR1200_DCCFGR_CBWBRI            1'b0    // Irrelevant
1686 
`define OR1200_DCCFGR_RES1              17'h00000
1687 
`else
1688 
`define OR1200_DCCFGR_NCW               3'h0    // 1 cache way
1689 
`define OR1200_DCCFGR_NCS (`OR1200_DCTAG)       // Num cache sets
1690 
`define OR1200_DCCFGR_CBS (`OR1200_DCLS-4)      // 16 byte cache block
1691 
`define OR1200_DCCFGR_CWS               1'b0    // Write-through strategy
1692 
`define OR1200_DCCFGR_CCRI              1'b1    // Cache control reg impl.
1693 
`define OR1200_DCCFGR_CBIRI             1'b1    // Cache block inv reg impl.
1694 
`define OR1200_DCCFGR_CBPRI             1'b0    // Cache block prefetch reg not impl.
1695 
`define OR1200_DCCFGR_CBLRI             1'b0    // Cache block lock reg not impl.
1696 
`define OR1200_DCCFGR_CBFRI             1'b1    // Cache block flush reg impl.
1697 
`define OR1200_DCCFGR_CBWBRI            1'b0    // Cache block WB reg not impl.
1698 
`define OR1200_DCCFGR_RES1              17'h00000
1699 
`endif
1700 
 
1701 
// ICCFGR fields
1702 
`define OR1200_ICCFGR_NCW_BITS          2:0
1703 
`define OR1200_ICCFGR_NCS_BITS          6:3
1704 
`define OR1200_ICCFGR_CBS_BITS          7
1705 
`define OR1200_ICCFGR_CWS_BITS          8
1706 
`define OR1200_ICCFGR_CCRI_BITS         9
1707 
`define OR1200_ICCFGR_CBIRI_BITS        10
1708 
`define OR1200_ICCFGR_CBPRI_BITS        11
1709 
`define OR1200_ICCFGR_CBLRI_BITS        12
1710 
`define OR1200_ICCFGR_CBFRI_BITS        13
1711 
`define OR1200_ICCFGR_CBWBRI_BITS       14
1712 
`define OR1200_ICCFGR_RES1_BITS 31:15
1713 
 
1714 
// ICCFGR values
1715 
`ifdef OR1200_NO_IC
1716 
`define OR1200_ICCFGR_NCW               3'h0    // Irrelevant
1717 
`define OR1200_ICCFGR_NCS               4'h0    // Irrelevant
1718 
`define OR1200_ICCFGR_CBS               1'b0    // Irrelevant
1719 
`define OR1200_ICCFGR_CWS               1'b0    // Irrelevant
1720 
`define OR1200_ICCFGR_CCRI              1'b0    // Irrelevant
1721 
`define OR1200_ICCFGR_CBIRI             1'b0    // Irrelevant
1722 
`define OR1200_ICCFGR_CBPRI             1'b0    // Irrelevant
1723 
`define OR1200_ICCFGR_CBLRI             1'b0    // Irrelevant
1724 
`define OR1200_ICCFGR_CBFRI             1'b0    // Irrelevant
1725 
`define OR1200_ICCFGR_CBWBRI            1'b0    // Irrelevant
1726 
`define OR1200_ICCFGR_RES1              17'h00000
1727 
`else
1728 
`define OR1200_ICCFGR_NCW               3'h0    // 1 cache way
1729 
`define OR1200_ICCFGR_NCS (`OR1200_ICTAG)       // Num cache sets
1730 
`define OR1200_ICCFGR_CBS (`OR1200_ICLS-4)      // 16 byte cache block
1731 
`define OR1200_ICCFGR_CWS               1'b0    // Irrelevant
1732 
`define OR1200_ICCFGR_CCRI              1'b1    // Cache control reg impl.
1733 
`define OR1200_ICCFGR_CBIRI             1'b1    // Cache block inv reg impl.
1734 
`define OR1200_ICCFGR_CBPRI             1'b0    // Cache block prefetch reg not impl.
1735 
`define OR1200_ICCFGR_CBLRI             1'b0    // Cache block lock reg not impl.
1736 
`define OR1200_ICCFGR_CBFRI             1'b1    // Cache block flush reg impl.
1737 
`define OR1200_ICCFGR_CBWBRI            1'b0    // Irrelevant
1738 
`define OR1200_ICCFGR_RES1              17'h00000
1739 
`endif
1740 
 
1741 
// DCFGR fields
1742 
`define OR1200_DCFGR_NDP_BITS           2:0
1743 
`define OR1200_DCFGR_WPCI_BITS          3
1744 
`define OR1200_DCFGR_RES1_BITS          31:4
1745 
 
1746 
// DCFGR values
1747 
`ifdef OR1200_DU_HWBKPTS
1748 
`define OR1200_DCFGR_NDP        3'h`OR1200_DU_DVRDCR_PAIRS // # of DVR/DCR pairs
1749 
`ifdef OR1200_DU_DWCR0
1750 
`define OR1200_DCFGR_WPCI               1'b1
1751 
`else
1752 
`define OR1200_DCFGR_WPCI               1'b0    // WP counters not impl.
1753 
`endif
1754 
`else
1755 
`define OR1200_DCFGR_NDP                3'h0    // Zero DVR/DCR pairs
1756 
`define OR1200_DCFGR_WPCI               1'b0    // WP counters not impl.
1757 
`endif
1758 
`define OR1200_DCFGR_RES1               28'h0000000
1759 
 

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