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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [or1200/] [rtl/] [verilog/] [or1200_du.v] - Blame information for rev 12

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1 12 xianfeng 
//////////////////////////////////////////////////////////////////////
2 
////                                                              ////
3 
////  OR1200's Debug Unit                                         ////
4 
////                                                              ////
5 
////  This file is part of the OpenRISC 1200 project              ////
6 
////  http://www.opencores.org/cores/or1k/                        ////
7 
////                                                              ////
8 
////  Description                                                 ////
9 
////  Basic OR1200 debug unit.                                    ////
10 
////                                                              ////
11 
////  To Do:                                                      ////
12 
////   - make it smaller and faster                               ////
13 
////                                                              ////
14 
////  Author(s):                                                  ////
15 
////      - Damjan Lampret, lampret@opencores.org                 ////
16 
////                                                              ////
17 
//////////////////////////////////////////////////////////////////////
18 
////                                                              ////
19 
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20 
////                                                              ////
21 
//// This source file may be used and distributed without         ////
22 
//// restriction provided that this copyright statement is not    ////
23 
//// removed from the file and that any derivative work contains  ////
24 
//// the original copyright notice and the associated disclaimer. ////
25 
////                                                              ////
26 
//// This source file is free software; you can redistribute it   ////
27 
//// and/or modify it under the terms of the GNU Lesser General   ////
28 
//// Public License as published by the Free Software Foundation; ////
29 
//// either version 2.1 of the License, or (at your option) any   ////
30 
//// later version.                                               ////
31 
////                                                              ////
32 
//// This source is distributed in the hope that it will be       ////
33 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36 
//// details.                                                     ////
37 
////                                                              ////
38 
//// You should have received a copy of the GNU Lesser General    ////
39 
//// Public License along with this source; if not, download it   ////
40 
//// from http://www.opencores.org/lgpl.shtml                     ////
41 
////                                                              ////
42 
//////////////////////////////////////////////////////////////////////
43 
//
44 
// CVS Revision History
45 
//
46 
// $Log: or1200_du.v,v $
47 
// Revision 1.12  2005/10/19 11:37:56  jcastillo
48 
// Added support for RAMB16 Xilinx4/Spartan3 primitives
49 
//
50 
// Revision 1.11  2005/01/07 09:35:08  andreje
51 
// du_hwbkpt disabled when debug unit not implemented
52 
//
53 
// Revision 1.10  2004/04/05 08:29:57  lampret
54 
// Merged branch_qmem into main tree.
55 
//
56 
// Revision 1.9.4.4  2004/02/11 01:40:11  lampret
57 
// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
58 
//
59 
// Revision 1.9.4.3  2004/01/18 10:08:00  simons
60 
// Error fixed.
61 
//
62 
// Revision 1.9.4.2  2004/01/17 21:14:14  simons
63 
// Errors fixed.
64 
//
65 
// Revision 1.9.4.1  2004/01/15 06:46:38  markom
66 
// interface to debug changed; no more opselect; stb-ack protocol
67 
//
68 
// Revision 1.9  2003/01/22 03:23:47  lampret
69 
// Updated sensitivity list for trace buffer [only relevant for Xilinx FPGAs]
70 
//
71 
// Revision 1.8  2002/09/08 19:31:52  lampret
72 
// Fixed a typo, reported by Taylor Su.
73 
//
74 
// Revision 1.7  2002/07/14 22:17:17  lampret
75 
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
76 
//
77 
// Revision 1.6  2002/03/14 00:30:24  lampret
78 
// Added alternative for critical path in DU.
79 
//
80 
// Revision 1.5  2002/02/11 04:33:17  lampret
81 
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
82 
//
83 
// Revision 1.4  2002/01/28 01:16:00  lampret
84 
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
85 
//
86 
// Revision 1.3  2002/01/18 07:56:00  lampret
87 
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
88 
//
89 
// Revision 1.2  2002/01/14 06:18:22  lampret
90 
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
91 
//
92 
// Revision 1.1  2002/01/03 08:16:15  lampret
93 
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
94 
//
95 
// Revision 1.12  2001/11/30 18:58:00  simons
96 
// Trap insn couses break after exits ex_insn.
97 
//
98 
// Revision 1.11  2001/11/23 08:38:51  lampret
99 
// Changed DSR/DRR behavior and exception detection.
100 
//
101 
// Revision 1.10  2001/11/20 21:25:44  lampret
102 
// Fixed dbg_is_o assignment width.
103 
//
104 
// Revision 1.9  2001/11/20 18:46:14  simons
105 
// Break point bug fixed
106 
//
107 
// Revision 1.8  2001/11/18 08:36:28  lampret
108 
// For GDB changed single stepping and disabled trap exception.
109 
//
110 
// Revision 1.7  2001/10/21 18:09:53  lampret
111 
// Fixed sensitivity list.
112 
//
113 
// Revision 1.6  2001/10/14 13:12:09  lampret
114 
// MP3 version.
115 
//
116 
//
117 
 
118 
// synopsys translate_off
119 
`include "timescale.v"
120 
// synopsys translate_on
121 
`include "or1200_defines.v"
122 
 
123 
//
124 
// Debug unit
125 
//
126 
 
127 
module or1200_du(
128 
        // RISC Internal Interface
129 
        clk, rst,
130 
        dcpu_cycstb_i, dcpu_we_i, dcpu_adr_i, dcpu_dat_lsu,
131 
        dcpu_dat_dc, icpu_cycstb_i,
132 
        ex_freeze, branch_op, ex_insn, id_pc,
133 
        spr_dat_npc, rf_dataw,
134 
        du_dsr, du_stall, du_addr, du_dat_i, du_dat_o,
135 
        du_read, du_write, du_except, du_hwbkpt,
136 
        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
137 
 
138 
        // External Debug Interface
139 
        dbg_stall_i, dbg_ewt_i, dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o,
140 
        dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o
141 
);
142 
 
143 
parameter dw = `OR1200_OPERAND_WIDTH;
144 
parameter aw = `OR1200_OPERAND_WIDTH;
145 
 
146 
//
147 
// I/O
148 
//
149 
 
150 
//
151 
// RISC Internal Interface
152 
//
153 
input                           clk;            // Clock
154 
input                           rst;            // Reset
155 
input                           dcpu_cycstb_i;  // LSU status
156 
input                           dcpu_we_i;      // LSU status
157 
input   [31:0]                   dcpu_adr_i;     // LSU addr
158 
input   [31:0]                   dcpu_dat_lsu;   // LSU store data
159 
input   [31:0]                   dcpu_dat_dc;    // LSU load data
160 
input   [`OR1200_FETCHOP_WIDTH-1:0]      icpu_cycstb_i;  // IFETCH unit status
161 
input                           ex_freeze;      // EX stage freeze
162 
input   [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;      // Branch op
163 
input   [dw-1:0]         ex_insn;        // EX insn
164 
input   [31:0]                   id_pc;          // insn fetch EA
165 
input   [31:0]                   spr_dat_npc;    // Next PC (for trace)
166 
input   [31:0]                   rf_dataw;       // ALU result (for trace)
167 
output  [`OR1200_DU_DSR_WIDTH-1:0]     du_dsr;           // DSR
168 
output                          du_stall;       // Debug Unit Stall
169 
output  [aw-1:0]         du_addr;        // Debug Unit Address
170 
input   [dw-1:0]         du_dat_i;       // Debug Unit Data In
171 
output  [dw-1:0]         du_dat_o;       // Debug Unit Data Out
172 
output                          du_read;        // Debug Unit Read Enable
173 
output                          du_write;       // Debug Unit Write Enable
174 
input   [12:0]                   du_except;      // Exception masked by DSR
175 
output                          du_hwbkpt;      // Cause trap exception (HW Breakpoints)
176 
input                           spr_cs;         // SPR Chip Select
177 
input                           spr_write;      // SPR Read/Write
178 
input   [aw-1:0]         spr_addr;       // SPR Address
179 
input   [dw-1:0]         spr_dat_i;      // SPR Data Input
180 
output  [dw-1:0]         spr_dat_o;      // SPR Data Output
181 
 
182 
//
183 
// External Debug Interface
184 
//
185 
input                   dbg_stall_i;    // External Stall Input
186 
input                   dbg_ewt_i;      // External Watchpoint Trigger Input
187 
output  [3:0]            dbg_lss_o;      // External Load/Store Unit Status
188 
output  [1:0]            dbg_is_o;       // External Insn Fetch Status
189 
output  [10:0]           dbg_wp_o;       // Watchpoints Outputs
190 
output                  dbg_bp_o;       // Breakpoint Output
191 
input                   dbg_stb_i;      // External Address/Data Strobe
192 
input                   dbg_we_i;       // External Write Enable
193 
input   [aw-1:0] dbg_adr_i;      // External Address Input
194 
input   [dw-1:0] dbg_dat_i;      // External Data Input
195 
output  [dw-1:0] dbg_dat_o;      // External Data Output
196 
output                  dbg_ack_o;      // External Data Acknowledge (not WB compatible)
197 
 
198 
 
199 
//
200 
// Some connections go directly from the CPU through DU to Debug I/F
201 
//
202 
`ifdef OR1200_DU_STATUS_UNIMPLEMENTED
203 
assign dbg_lss_o = 4'b0000;
204 
 
205 
reg     [1:0]                    dbg_is_o;
206 
//
207 
// Show insn activity (temp, must be removed)
208 
//
209 
always @(posedge clk or posedge rst)
210 
        if (rst)
211 
                dbg_is_o <= #1 2'b00;
212 
        else if (!ex_freeze &
213 
                ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]))
214 
                dbg_is_o <= #1 ~dbg_is_o;
215 
`ifdef UNUSED
216 
assign dbg_is_o = 2'b00;
217 
`endif
218 
`else
219 
assign dbg_lss_o = dcpu_cycstb_i ? {dcpu_we_i, 3'b000} : 4'b0000;
220 
assign dbg_is_o = {1'b0, icpu_cycstb_i};
221 
`endif
222 
assign dbg_wp_o = 11'b000_0000_0000;
223 
assign dbg_dat_o = du_dat_i;
224 
 
225 
//
226 
// Some connections go directly from Debug I/F through DU to the CPU
227 
//
228 
assign du_stall = dbg_stall_i;
229 
assign du_addr = dbg_adr_i;
230 
assign du_dat_o = dbg_dat_i;
231 
assign du_read = dbg_stb_i && !dbg_we_i;
232 
assign du_write = dbg_stb_i && dbg_we_i;
233 
 
234 
//
235 
// Generate acknowledge -- just delay stb signal
236 
//
237 
reg dbg_ack_o;
238 
always @(posedge clk or posedge rst)
239 
        if (rst)
240 
                dbg_ack_o <= #1 1'b0;
241 
        else
242 
                dbg_ack_o <= #1 dbg_stb_i;
243 
 
244 
`ifdef OR1200_DU_IMPLEMENTED
245 
 
246 
//
247 
// Debug Mode Register 1
248 
//
249 
`ifdef OR1200_DU_DMR1
250 
reg     [24:0]                   dmr1;           // DMR1 implemented
251 
`else
252 
wire    [24:0]                   dmr1;           // DMR1 not implemented
253 
`endif
254 
 
255 
//
256 
// Debug Mode Register 2
257 
//
258 
`ifdef OR1200_DU_DMR2
259 
reg     [23:0]                   dmr2;           // DMR2 implemented
260 
`else
261 
wire    [23:0]                   dmr2;           // DMR2 not implemented
262 
`endif
263 
 
264 
//
265 
// Debug Stop Register
266 
//
267 
`ifdef OR1200_DU_DSR
268 
reg     [`OR1200_DU_DSR_WIDTH-1:0]       dsr;            // DSR implemented
269 
`else
270 
wire    [`OR1200_DU_DSR_WIDTH-1:0]       dsr;            // DSR not implemented
271 
`endif
272 
 
273 
//
274 
// Debug Reason Register
275 
//
276 
`ifdef OR1200_DU_DRR
277 
reg     [13:0]                   drr;            // DRR implemented
278 
`else
279 
wire    [13:0]                   drr;            // DRR not implemented
280 
`endif
281 
 
282 
//
283 
// Debug Value Register N
284 
//
285 
`ifdef OR1200_DU_DVR0
286 
reg     [31:0]                   dvr0;
287 
`else
288 
wire    [31:0]                   dvr0;
289 
`endif
290 
 
291 
//
292 
// Debug Value Register N
293 
//
294 
`ifdef OR1200_DU_DVR1
295 
reg     [31:0]                   dvr1;
296 
`else
297 
wire    [31:0]                   dvr1;
298 
`endif
299 
 
300 
//
301 
// Debug Value Register N
302 
//
303 
`ifdef OR1200_DU_DVR2
304 
reg     [31:0]                   dvr2;
305 
`else
306 
wire    [31:0]                   dvr2;
307 
`endif
308 
 
309 
//
310 
// Debug Value Register N
311 
//
312 
`ifdef OR1200_DU_DVR3
313 
reg     [31:0]                   dvr3;
314 
`else
315 
wire    [31:0]                   dvr3;
316 
`endif
317 
 
318 
//
319 
// Debug Value Register N
320 
//
321 
`ifdef OR1200_DU_DVR4
322 
reg     [31:0]                   dvr4;
323 
`else
324 
wire    [31:0]                   dvr4;
325 
`endif
326 
 
327 
//
328 
// Debug Value Register N
329 
//
330 
`ifdef OR1200_DU_DVR5
331 
reg     [31:0]                   dvr5;
332 
`else
333 
wire    [31:0]                   dvr5;
334 
`endif
335 
 
336 
//
337 
// Debug Value Register N
338 
//
339 
`ifdef OR1200_DU_DVR6
340 
reg     [31:0]                   dvr6;
341 
`else
342 
wire    [31:0]                   dvr6;
343 
`endif
344 
 
345 
//
346 
// Debug Value Register N
347 
//
348 
`ifdef OR1200_DU_DVR7
349 
reg     [31:0]                   dvr7;
350 
`else
351 
wire    [31:0]                   dvr7;
352 
`endif
353 
 
354 
//
355 
// Debug Control Register N
356 
//
357 
`ifdef OR1200_DU_DCR0
358 
reg     [7:0]                    dcr0;
359 
`else
360 
wire    [7:0]                    dcr0;
361 
`endif
362 
 
363 
//
364 
// Debug Control Register N
365 
//
366 
`ifdef OR1200_DU_DCR1
367 
reg     [7:0]                    dcr1;
368 
`else
369 
wire    [7:0]                    dcr1;
370 
`endif
371 
 
372 
//
373 
// Debug Control Register N
374 
//
375 
`ifdef OR1200_DU_DCR2
376 
reg     [7:0]                    dcr2;
377 
`else
378 
wire    [7:0]                    dcr2;
379 
`endif
380 
 
381 
//
382 
// Debug Control Register N
383 
//
384 
`ifdef OR1200_DU_DCR3
385 
reg     [7:0]                    dcr3;
386 
`else
387 
wire    [7:0]                    dcr3;
388 
`endif
389 
 
390 
//
391 
// Debug Control Register N
392 
//
393 
`ifdef OR1200_DU_DCR4
394 
reg     [7:0]                    dcr4;
395 
`else
396 
wire    [7:0]                    dcr4;
397 
`endif
398 
 
399 
//
400 
// Debug Control Register N
401 
//
402 
`ifdef OR1200_DU_DCR5
403 
reg     [7:0]                    dcr5;
404 
`else
405 
wire    [7:0]                    dcr5;
406 
`endif
407 
 
408 
//
409 
// Debug Control Register N
410 
//
411 
`ifdef OR1200_DU_DCR6
412 
reg     [7:0]                    dcr6;
413 
`else
414 
wire    [7:0]                    dcr6;
415 
`endif
416 
 
417 
//
418 
// Debug Control Register N
419 
//
420 
`ifdef OR1200_DU_DCR7
421 
reg     [7:0]                    dcr7;
422 
`else
423 
wire    [7:0]                    dcr7;
424 
`endif
425 
 
426 
//
427 
// Debug Watchpoint Counter Register 0
428 
//
429 
`ifdef OR1200_DU_DWCR0
430 
reg     [31:0]                   dwcr0;
431 
`else
432 
wire    [31:0]                   dwcr0;
433 
`endif
434 
 
435 
//
436 
// Debug Watchpoint Counter Register 1
437 
//
438 
`ifdef OR1200_DU_DWCR1
439 
reg     [31:0]                   dwcr1;
440 
`else
441 
wire    [31:0]                   dwcr1;
442 
`endif
443 
 
444 
//
445 
// Internal wires
446 
//
447 
wire                            dmr1_sel;       // DMR1 select
448 
wire                            dmr2_sel;       // DMR2 select
449 
wire                            dsr_sel;        // DSR select
450 
wire                            drr_sel;        // DRR select
451 
wire                            dvr0_sel,
452 
                                dvr1_sel,
453 
                                dvr2_sel,
454 
                                dvr3_sel,
455 
                                dvr4_sel,
456 
                                dvr5_sel,
457 
                                dvr6_sel,
458 
                                dvr7_sel;       // DVR selects
459 
wire                            dcr0_sel,
460 
                                dcr1_sel,
461 
                                dcr2_sel,
462 
                                dcr3_sel,
463 
                                dcr4_sel,
464 
                                dcr5_sel,
465 
                                dcr6_sel,
466 
                                dcr7_sel;       // DCR selects
467 
wire                            dwcr0_sel,
468 
                                dwcr1_sel;      // DWCR selects
469 
reg                             dbg_bp_r;
470 
`ifdef OR1200_DU_HWBKPTS
471 
reg     [31:0]                   match_cond0_ct;
472 
reg     [31:0]                   match_cond1_ct;
473 
reg     [31:0]                   match_cond2_ct;
474 
reg     [31:0]                   match_cond3_ct;
475 
reg     [31:0]                   match_cond4_ct;
476 
reg     [31:0]                   match_cond5_ct;
477 
reg     [31:0]                   match_cond6_ct;
478 
reg     [31:0]                   match_cond7_ct;
479 
reg                             match_cond0_stb;
480 
reg                             match_cond1_stb;
481 
reg                             match_cond2_stb;
482 
reg                             match_cond3_stb;
483 
reg                             match_cond4_stb;
484 
reg                             match_cond5_stb;
485 
reg                             match_cond6_stb;
486 
reg                             match_cond7_stb;
487 
reg                             match0;
488 
reg                             match1;
489 
reg                             match2;
490 
reg                             match3;
491 
reg                             match4;
492 
reg                             match5;
493 
reg                             match6;
494 
reg                             match7;
495 
reg                             wpcntr0_match;
496 
reg                             wpcntr1_match;
497 
reg                             incr_wpcntr0;
498 
reg                             incr_wpcntr1;
499 
reg     [10:0]                   wp;
500 
`endif
501 
wire                            du_hwbkpt;
502 
`ifdef OR1200_DU_READREGS
503 
reg     [31:0]                   spr_dat_o;
504 
`endif
505 
reg     [13:0]                   except_stop;    // Exceptions that stop because of DSR
506 
`ifdef OR1200_DU_TB_IMPLEMENTED
507 
wire                            tb_enw;
508 
reg     [7:0]                    tb_wadr;
509 
reg [31:0]                       tb_timstmp;
510 
`endif
511 
wire    [31:0]                   tbia_dat_o;
512 
wire    [31:0]                   tbim_dat_o;
513 
wire    [31:0]                   tbar_dat_o;
514 
wire    [31:0]                   tbts_dat_o;
515 
 
516 
//
517 
// DU registers address decoder
518 
//
519 
`ifdef OR1200_DU_DMR1
520 
assign dmr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DMR1));
521 
`endif
522 
`ifdef OR1200_DU_DMR2
523 
assign dmr2_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DMR2));
524 
`endif
525 
`ifdef OR1200_DU_DSR
526 
assign dsr_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DSR));
527 
`endif
528 
`ifdef OR1200_DU_DRR
529 
assign drr_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DRR));
530 
`endif
531 
`ifdef OR1200_DU_DVR0
532 
assign dvr0_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR0));
533 
`endif
534 
`ifdef OR1200_DU_DVR1
535 
assign dvr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR1));
536 
`endif
537 
`ifdef OR1200_DU_DVR2
538 
assign dvr2_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR2));
539 
`endif
540 
`ifdef OR1200_DU_DVR3
541 
assign dvr3_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR3));
542 
`endif
543 
`ifdef OR1200_DU_DVR4
544 
assign dvr4_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR4));
545 
`endif
546 
`ifdef OR1200_DU_DVR5
547 
assign dvr5_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR5));
548 
`endif
549 
`ifdef OR1200_DU_DVR6
550 
assign dvr6_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR6));
551 
`endif
552 
`ifdef OR1200_DU_DVR7
553 
assign dvr7_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR7));
554 
`endif
555 
`ifdef OR1200_DU_DCR0
556 
assign dcr0_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR0));
557 
`endif
558 
`ifdef OR1200_DU_DCR1
559 
assign dcr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR1));
560 
`endif
561 
`ifdef OR1200_DU_DCR2
562 
assign dcr2_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR2));
563 
`endif
564 
`ifdef OR1200_DU_DCR3
565 
assign dcr3_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR3));
566 
`endif
567 
`ifdef OR1200_DU_DCR4
568 
assign dcr4_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR4));
569 
`endif
570 
`ifdef OR1200_DU_DCR5
571 
assign dcr5_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR5));
572 
`endif
573 
`ifdef OR1200_DU_DCR6
574 
assign dcr6_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR6));
575 
`endif
576 
`ifdef OR1200_DU_DCR7
577 
assign dcr7_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR7));
578 
`endif
579 
`ifdef OR1200_DU_DWCR0
580 
assign dwcr0_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DWCR0));
581 
`endif
582 
`ifdef OR1200_DU_DWCR1
583 
assign dwcr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DWCR1));
584 
`endif
585 
 
586 
//
587 
// Decode started exception
588 
//
589 
always @(du_except) begin
590 
        except_stop = 14'b0000_0000_0000;
591 
        casex (du_except)
592 
                13'b1_xxxx_xxxx_xxxx:
593 
                        except_stop[`OR1200_DU_DRR_TTE] = 1'b1;
594 
                13'b0_1xxx_xxxx_xxxx: begin
595 
                        except_stop[`OR1200_DU_DRR_IE] = 1'b1;
596 
                end
597 
                13'b0_01xx_xxxx_xxxx: begin
598 
                        except_stop[`OR1200_DU_DRR_IME] = 1'b1;
599 
                end
600 
                13'b0_001x_xxxx_xxxx:
601 
                        except_stop[`OR1200_DU_DRR_IPFE] = 1'b1;
602 
                13'b0_0001_xxxx_xxxx: begin
603 
                        except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
604 
                end
605 
                13'b0_0000_1xxx_xxxx:
606 
                        except_stop[`OR1200_DU_DRR_IIE] = 1'b1;
607 
                13'b0_0000_01xx_xxxx: begin
608 
                        except_stop[`OR1200_DU_DRR_AE] = 1'b1;
609 
                end
610 
                13'b0_0000_001x_xxxx: begin
611 
                        except_stop[`OR1200_DU_DRR_DME] = 1'b1;
612 
                end
613 
                13'b0_0000_0001_xxxx:
614 
                        except_stop[`OR1200_DU_DRR_DPFE] = 1'b1;
615 
                13'b0_0000_0000_1xxx:
616 
                        except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
617 
                13'b0_0000_0000_01xx: begin
618 
                        except_stop[`OR1200_DU_DRR_RE] = 1'b1;
619 
                end
620 
                13'b0_0000_0000_001x: begin
621 
                        except_stop[`OR1200_DU_DRR_TE] = 1'b1;
622 
                end
623 
                13'b0_0000_0000_0001:
624 
                        except_stop[`OR1200_DU_DRR_SCE] = 1'b1;
625 
                default:
626 
                        except_stop = 14'b0000_0000_0000;
627 
        endcase
628 
end
629 
 
630 
//
631 
// dbg_bp_o is registered
632 
//
633 
assign dbg_bp_o = dbg_bp_r;
634 
 
635 
//
636 
// Breakpoint activation register
637 
//
638 
always @(posedge clk or posedge rst)
639 
        if (rst)
640 
                dbg_bp_r <= #1 1'b0;
641 
        else if (!ex_freeze)
642 
                dbg_bp_r <= #1 |except_stop
643 
`ifdef OR1200_DU_DMR1_ST
644 
                        | ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]) & dmr1[`OR1200_DU_DMR1_ST]
645 
`endif
646 
`ifdef OR1200_DU_DMR1_BT
647 
                        | (branch_op != `OR1200_BRANCHOP_NOP) & dmr1[`OR1200_DU_DMR1_BT]
648 
`endif
649 
                        ;
650 
        else
651 
                dbg_bp_r <= #1 |except_stop;
652 
 
653 
//
654 
// Write to DMR1
655 
//
656 
`ifdef OR1200_DU_DMR1
657 
always @(posedge clk or posedge rst)
658 
        if (rst)
659 
                dmr1 <= 25'h000_0000;
660 
        else if (dmr1_sel && spr_write)
661 
`ifdef OR1200_DU_HWBKPTS
662 
                dmr1 <= #1 spr_dat_i[24:0];
663 
`else
664 
                dmr1 <= #1 {1'b0, spr_dat_i[23:22], 22'h00_0000};
665 
`endif
666 
`else
667 
assign dmr1 = 25'h000_0000;
668 
`endif
669 
 
670 
//
671 
// Write to DMR2
672 
//
673 
`ifdef OR1200_DU_DMR2
674 
always @(posedge clk or posedge rst)
675 
        if (rst)
676 
                dmr2 <= 24'h00_0000;
677 
        else if (dmr2_sel && spr_write)
678 
                dmr2 <= #1 spr_dat_i[23:0];
679 
`else
680 
assign dmr2 = 24'h00_0000;
681 
`endif
682 
 
683 
//
684 
// Write to DSR
685 
//
686 
`ifdef OR1200_DU_DSR
687 
always @(posedge clk or posedge rst)
688 
        if (rst)
689 
                dsr <= {`OR1200_DU_DSR_WIDTH{1'b0}};
690 
        else if (dsr_sel && spr_write)
691 
                dsr <= #1 spr_dat_i[`OR1200_DU_DSR_WIDTH-1:0];
692 
`else
693 
assign dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
694 
`endif
695 
 
696 
//
697 
// Write to DRR
698 
//
699 
`ifdef OR1200_DU_DRR
700 
always @(posedge clk or posedge rst)
701 
        if (rst)
702 
                drr <= 14'b0;
703 
        else if (drr_sel && spr_write)
704 
                drr <= #1 spr_dat_i[13:0];
705 
        else
706 
                drr <= #1 drr | except_stop;
707 
`else
708 
assign drr = 14'b0;
709 
`endif
710 
 
711 
//
712 
// Write to DVR0
713 
//
714 
`ifdef OR1200_DU_DVR0
715 
always @(posedge clk or posedge rst)
716 
        if (rst)
717 
                dvr0 <= 32'h0000_0000;
718 
        else if (dvr0_sel && spr_write)
719 
                dvr0 <= #1 spr_dat_i[31:0];
720 
`else
721 
assign dvr0 = 32'h0000_0000;
722 
`endif
723 
 
724 
//
725 
// Write to DVR1
726 
//
727 
`ifdef OR1200_DU_DVR1
728 
always @(posedge clk or posedge rst)
729 
        if (rst)
730 
                dvr1 <= 32'h0000_0000;
731 
        else if (dvr1_sel && spr_write)
732 
                dvr1 <= #1 spr_dat_i[31:0];
733 
`else
734 
assign dvr1 = 32'h0000_0000;
735 
`endif
736 
 
737 
//
738 
// Write to DVR2
739 
//
740 
`ifdef OR1200_DU_DVR2
741 
always @(posedge clk or posedge rst)
742 
        if (rst)
743 
                dvr2 <= 32'h0000_0000;
744 
        else if (dvr2_sel && spr_write)
745 
                dvr2 <= #1 spr_dat_i[31:0];
746 
`else
747 
assign dvr2 = 32'h0000_0000;
748 
`endif
749 
 
750 
//
751 
// Write to DVR3
752 
//
753 
`ifdef OR1200_DU_DVR3
754 
always @(posedge clk or posedge rst)
755 
        if (rst)
756 
                dvr3 <= 32'h0000_0000;
757 
        else if (dvr3_sel && spr_write)
758 
                dvr3 <= #1 spr_dat_i[31:0];
759 
`else
760 
assign dvr3 = 32'h0000_0000;
761 
`endif
762 
 
763 
//
764 
// Write to DVR4
765 
//
766 
`ifdef OR1200_DU_DVR4
767 
always @(posedge clk or posedge rst)
768 
        if (rst)
769 
                dvr4 <= 32'h0000_0000;
770 
        else if (dvr4_sel && spr_write)
771 
                dvr4 <= #1 spr_dat_i[31:0];
772 
`else
773 
assign dvr4 = 32'h0000_0000;
774 
`endif
775 
 
776 
//
777 
// Write to DVR5
778 
//
779 
`ifdef OR1200_DU_DVR5
780 
always @(posedge clk or posedge rst)
781 
        if (rst)
782 
                dvr5 <= 32'h0000_0000;
783 
        else if (dvr5_sel && spr_write)
784 
                dvr5 <= #1 spr_dat_i[31:0];
785 
`else
786 
assign dvr5 = 32'h0000_0000;
787 
`endif
788 
 
789 
//
790 
// Write to DVR6
791 
//
792 
`ifdef OR1200_DU_DVR6
793 
always @(posedge clk or posedge rst)
794 
        if (rst)
795 
                dvr6 <= 32'h0000_0000;
796 
        else if (dvr6_sel && spr_write)
797 
                dvr6 <= #1 spr_dat_i[31:0];
798 
`else
799 
assign dvr6 = 32'h0000_0000;
800 
`endif
801 
 
802 
//
803 
// Write to DVR7
804 
//
805 
`ifdef OR1200_DU_DVR7
806 
always @(posedge clk or posedge rst)
807 
        if (rst)
808 
                dvr7 <= 32'h0000_0000;
809 
        else if (dvr7_sel && spr_write)
810 
                dvr7 <= #1 spr_dat_i[31:0];
811 
`else
812 
assign dvr7 = 32'h0000_0000;
813 
`endif
814 
 
815 
//
816 
// Write to DCR0
817 
//
818 
`ifdef OR1200_DU_DCR0
819 
always @(posedge clk or posedge rst)
820 
        if (rst)
821 
                dcr0 <= 8'h00;
822 
        else if (dcr0_sel && spr_write)
823 
                dcr0 <= #1 spr_dat_i[7:0];
824 
`else
825 
assign dcr0 = 8'h00;
826 
`endif
827 
 
828 
//
829 
// Write to DCR1
830 
//
831 
`ifdef OR1200_DU_DCR1
832 
always @(posedge clk or posedge rst)
833 
        if (rst)
834 
                dcr1 <= 8'h00;
835 
        else if (dcr1_sel && spr_write)
836 
                dcr1 <= #1 spr_dat_i[7:0];
837 
`else
838 
assign dcr1 = 8'h00;
839 
`endif
840 
 
841 
//
842 
// Write to DCR2
843 
//
844 
`ifdef OR1200_DU_DCR2
845 
always @(posedge clk or posedge rst)
846 
        if (rst)
847 
                dcr2 <= 8'h00;
848 
        else if (dcr2_sel && spr_write)
849 
                dcr2 <= #1 spr_dat_i[7:0];
850 
`else
851 
assign dcr2 = 8'h00;
852 
`endif
853 
 
854 
//
855 
// Write to DCR3
856 
//
857 
`ifdef OR1200_DU_DCR3
858 
always @(posedge clk or posedge rst)
859 
        if (rst)
860 
                dcr3 <= 8'h00;
861 
        else if (dcr3_sel && spr_write)
862 
                dcr3 <= #1 spr_dat_i[7:0];
863 
`else
864 
assign dcr3 = 8'h00;
865 
`endif
866 
 
867 
//
868 
// Write to DCR4
869 
//
870 
`ifdef OR1200_DU_DCR4
871 
always @(posedge clk or posedge rst)
872 
        if (rst)
873 
                dcr4 <= 8'h00;
874 
        else if (dcr4_sel && spr_write)
875 
                dcr4 <= #1 spr_dat_i[7:0];
876 
`else
877 
assign dcr4 = 8'h00;
878 
`endif
879 
 
880 
//
881 
// Write to DCR5
882 
//
883 
`ifdef OR1200_DU_DCR5
884 
always @(posedge clk or posedge rst)
885 
        if (rst)
886 
                dcr5 <= 8'h00;
887 
        else if (dcr5_sel && spr_write)
888 
                dcr5 <= #1 spr_dat_i[7:0];
889 
`else
890 
assign dcr5 = 8'h00;
891 
`endif
892 
 
893 
//
894 
// Write to DCR6
895 
//
896 
`ifdef OR1200_DU_DCR6
897 
always @(posedge clk or posedge rst)
898 
        if (rst)
899 
                dcr6 <= 8'h00;
900 
        else if (dcr6_sel && spr_write)
901 
                dcr6 <= #1 spr_dat_i[7:0];
902 
`else
903 
assign dcr6 = 8'h00;
904 
`endif
905 
 
906 
//
907 
// Write to DCR7
908 
//
909 
`ifdef OR1200_DU_DCR7
910 
always @(posedge clk or posedge rst)
911 
        if (rst)
912 
                dcr7 <= 8'h00;
913 
        else if (dcr7_sel && spr_write)
914 
                dcr7 <= #1 spr_dat_i[7:0];
915 
`else
916 
assign dcr7 = 8'h00;
917 
`endif
918 
 
919 
//
920 
// Write to DWCR0
921 
//
922 
`ifdef OR1200_DU_DWCR0
923 
always @(posedge clk or posedge rst)
924 
        if (rst)
925 
                dwcr0 <= 32'h0000_0000;
926 
        else if (dwcr0_sel && spr_write)
927 
                dwcr0 <= #1 spr_dat_i[31:0];
928 
        else if (incr_wpcntr0)
929 
                dwcr0[`OR1200_DU_DWCR_COUNT] <= #1 dwcr0[`OR1200_DU_DWCR_COUNT] + 16'h0001;
930 
`else
931 
assign dwcr0 = 32'h0000_0000;
932 
`endif
933 
 
934 
//
935 
// Write to DWCR1
936 
//
937 
`ifdef OR1200_DU_DWCR1
938 
always @(posedge clk or posedge rst)
939 
        if (rst)
940 
                dwcr1 <= 32'h0000_0000;
941 
        else if (dwcr1_sel && spr_write)
942 
                dwcr1 <= #1 spr_dat_i[31:0];
943 
        else if (incr_wpcntr1)
944 
                dwcr1[`OR1200_DU_DWCR_COUNT] <= #1 dwcr1[`OR1200_DU_DWCR_COUNT] + 16'h0001;
945 
`else
946 
assign dwcr1 = 32'h0000_0000;
947 
`endif
948 
 
949 
//
950 
// Read DU registers
951 
//
952 
`ifdef OR1200_DU_READREGS
953 
always @(spr_addr or dsr or drr or dmr1 or dmr2
954 
        or dvr0 or dvr1 or dvr2 or dvr3 or dvr4
955 
        or dvr5 or dvr6 or dvr7
956 
        or dcr0 or dcr1 or dcr2 or dcr3 or dcr4
957 
        or dcr5 or dcr6 or dcr7
958 
        or dwcr0 or dwcr1
959 
`ifdef OR1200_DU_TB_IMPLEMENTED
960 
        or tb_wadr or tbia_dat_o or tbim_dat_o
961 
        or tbar_dat_o or tbts_dat_o
962 
`endif
963 
        )
964 
        casex (spr_addr[`OR1200_DUOFS_BITS]) // synopsys parallel_case
965 
`ifdef OR1200_DU_DVR0
966 
                `OR1200_DU_DVR0:
967 
                        spr_dat_o = dvr0;
968 
`endif
969 
`ifdef OR1200_DU_DVR1
970 
                `OR1200_DU_DVR1:
971 
                        spr_dat_o = dvr1;
972 
`endif
973 
`ifdef OR1200_DU_DVR2
974 
                `OR1200_DU_DVR2:
975 
                        spr_dat_o = dvr2;
976 
`endif
977 
`ifdef OR1200_DU_DVR3
978 
                `OR1200_DU_DVR3:
979 
                        spr_dat_o = dvr3;
980 
`endif
981 
`ifdef OR1200_DU_DVR4
982 
                `OR1200_DU_DVR4:
983 
                        spr_dat_o = dvr4;
984 
`endif
985 
`ifdef OR1200_DU_DVR5
986 
                `OR1200_DU_DVR5:
987 
                        spr_dat_o = dvr5;
988 
`endif
989 
`ifdef OR1200_DU_DVR6
990 
                `OR1200_DU_DVR6:
991 
                        spr_dat_o = dvr6;
992 
`endif
993 
`ifdef OR1200_DU_DVR7
994 
                `OR1200_DU_DVR7:
995 
                        spr_dat_o = dvr7;
996 
`endif
997 
`ifdef OR1200_DU_DCR0
998 
                `OR1200_DU_DCR0:
999 
                        spr_dat_o = {24'h00_0000, dcr0};
1000 
`endif
1001 
`ifdef OR1200_DU_DCR1
1002 
                `OR1200_DU_DCR1:
1003 
                        spr_dat_o = {24'h00_0000, dcr1};
1004 
`endif
1005 
`ifdef OR1200_DU_DCR2
1006 
                `OR1200_DU_DCR2:
1007 
                        spr_dat_o = {24'h00_0000, dcr2};
1008 
`endif
1009 
`ifdef OR1200_DU_DCR3
1010 
                `OR1200_DU_DCR3:
1011 
                        spr_dat_o = {24'h00_0000, dcr3};
1012 
`endif
1013 
`ifdef OR1200_DU_DCR4
1014 
                `OR1200_DU_DCR4:
1015 
                        spr_dat_o = {24'h00_0000, dcr4};
1016 
`endif
1017 
`ifdef OR1200_DU_DCR5
1018 
                `OR1200_DU_DCR5:
1019 
                        spr_dat_o = {24'h00_0000, dcr5};
1020 
`endif
1021 
`ifdef OR1200_DU_DCR6
1022 
                `OR1200_DU_DCR6:
1023 
                        spr_dat_o = {24'h00_0000, dcr6};
1024 
`endif
1025 
`ifdef OR1200_DU_DCR7
1026 
                `OR1200_DU_DCR7:
1027 
                        spr_dat_o = {24'h00_0000, dcr7};
1028 
`endif
1029 
`ifdef OR1200_DU_DMR1
1030 
                `OR1200_DU_DMR1:
1031 
                        spr_dat_o = {7'h00, dmr1};
1032 
`endif
1033 
`ifdef OR1200_DU_DMR2
1034 
                `OR1200_DU_DMR2:
1035 
                        spr_dat_o = {8'h00, dmr2};
1036 
`endif
1037 
`ifdef OR1200_DU_DWCR0
1038 
                `OR1200_DU_DWCR0:
1039 
                        spr_dat_o = dwcr0;
1040 
`endif
1041 
`ifdef OR1200_DU_DWCR1
1042 
                `OR1200_DU_DWCR1:
1043 
                        spr_dat_o = dwcr1;
1044 
`endif
1045 
`ifdef OR1200_DU_DSR
1046 
                `OR1200_DU_DSR:
1047 
                        spr_dat_o = {18'b0, dsr};
1048 
`endif
1049 
`ifdef OR1200_DU_DRR
1050 
                `OR1200_DU_DRR:
1051 
                        spr_dat_o = {18'b0, drr};
1052 
`endif
1053 
`ifdef OR1200_DU_TB_IMPLEMENTED
1054 
                `OR1200_DU_TBADR:
1055 
                        spr_dat_o = {24'h000000, tb_wadr};
1056 
                `OR1200_DU_TBIA:
1057 
                        spr_dat_o = tbia_dat_o;
1058 
                `OR1200_DU_TBIM:
1059 
                        spr_dat_o = tbim_dat_o;
1060 
                `OR1200_DU_TBAR:
1061 
                        spr_dat_o = tbar_dat_o;
1062 
                `OR1200_DU_TBTS:
1063 
                        spr_dat_o = tbts_dat_o;
1064 
`endif
1065 
                default:
1066 
                        spr_dat_o = 32'h0000_0000;
1067 
        endcase
1068 
`endif
1069 
 
1070 
//
1071 
// DSR alias
1072 
//
1073 
assign du_dsr = dsr;
1074 
 
1075 
`ifdef OR1200_DU_HWBKPTS
1076 
 
1077 
//
1078 
// Compare To What (Match Condition 0)
1079 
//
1080 
always @(dcr0 or id_pc or dcpu_adr_i or dcpu_dat_dc
1081 
        or dcpu_dat_lsu or dcpu_we_i)
1082 
        case (dcr0[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1083 
                3'b001: match_cond0_ct = id_pc;         // insn fetch EA
1084 
                3'b010: match_cond0_ct = dcpu_adr_i;    // load EA
1085 
                3'b011: match_cond0_ct = dcpu_adr_i;    // store EA
1086 
                3'b100: match_cond0_ct = dcpu_dat_dc;   // load data
1087 
                3'b101: match_cond0_ct = dcpu_dat_lsu;  // store data
1088 
                3'b110: match_cond0_ct = dcpu_adr_i;    // load/store EA
1089 
                default:match_cond0_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1090 
        endcase
1091 
 
1092 
//
1093 
// When To Compare (Match Condition 0)
1094 
//
1095 
always @(dcr0 or dcpu_cycstb_i)
1096 
        case (dcr0[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1097 
                3'b000: match_cond0_stb = 1'b0;         //comparison disabled
1098 
                3'b001: match_cond0_stb = 1'b1;         // insn fetch EA
1099 
                default:match_cond0_stb = dcpu_cycstb_i; // any load/store
1100 
        endcase
1101 
 
1102 
//
1103 
// Match Condition 0
1104 
//
1105 
always @(match_cond0_stb or dcr0 or dvr0 or match_cond0_ct)
1106 
        casex ({match_cond0_stb, dcr0[`OR1200_DU_DCR_CC]})
1107 
                4'b0_xxx,
1108 
                4'b1_000,
1109 
                4'b1_111: match0 = 1'b0;
1110 
                4'b1_001: match0 =
1111 
                        ((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) ==
1112 
                        (dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
1113 
                4'b1_010: match0 =
1114 
                        ((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) <
1115 
                        (dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
1116 
                4'b1_011: match0 =
1117 
                        ((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) <=
1118 
                        (dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
1119 
                4'b1_100: match0 =
1120 
                        ((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) >
1121 
                        (dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
1122 
                4'b1_101: match0 =
1123 
                        ((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) >=
1124 
                        (dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
1125 
                4'b1_110: match0 =
1126 
                        ((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) !=
1127 
                        (dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
1128 
        endcase
1129 
 
1130 
//
1131 
// Watchpoint 0
1132 
//
1133 
always @(dmr1 or match0)
1134 
        case (dmr1[`OR1200_DU_DMR1_CW0])
1135 
                2'b00: wp[0] = match0;
1136 
                2'b01: wp[0] = match0;
1137 
                2'b10: wp[0] = match0;
1138 
                2'b11: wp[0] = 1'b0;
1139 
        endcase
1140 
 
1141 
//
1142 
// Compare To What (Match Condition 1)
1143 
//
1144 
always @(dcr1 or id_pc or dcpu_adr_i or dcpu_dat_dc
1145 
        or dcpu_dat_lsu or dcpu_we_i)
1146 
        case (dcr1[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1147 
                3'b001: match_cond1_ct = id_pc;         // insn fetch EA
1148 
                3'b010: match_cond1_ct = dcpu_adr_i;    // load EA
1149 
                3'b011: match_cond1_ct = dcpu_adr_i;    // store EA
1150 
                3'b100: match_cond1_ct = dcpu_dat_dc;   // load data
1151 
                3'b101: match_cond1_ct = dcpu_dat_lsu;  // store data
1152 
                3'b110: match_cond1_ct = dcpu_adr_i;    // load/store EA
1153 
                default:match_cond1_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1154 
        endcase
1155 
 
1156 
//
1157 
// When To Compare (Match Condition 1)
1158 
//
1159 
always @(dcr1 or dcpu_cycstb_i)
1160 
        case (dcr1[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1161 
                3'b000: match_cond1_stb = 1'b0;         //comparison disabled
1162 
                3'b001: match_cond1_stb = 1'b1;         // insn fetch EA
1163 
                default:match_cond1_stb = dcpu_cycstb_i; // any load/store
1164 
        endcase
1165 
 
1166 
//
1167 
// Match Condition 1
1168 
//
1169 
always @(match_cond1_stb or dcr1 or dvr1 or match_cond1_ct)
1170 
        casex ({match_cond1_stb, dcr1[`OR1200_DU_DCR_CC]})
1171 
                4'b0_xxx,
1172 
                4'b1_000,
1173 
                4'b1_111: match1 = 1'b0;
1174 
                4'b1_001: match1 =
1175 
                        ((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) ==
1176 
                        (dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
1177 
                4'b1_010: match1 =
1178 
                        ((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) <
1179 
                        (dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
1180 
                4'b1_011: match1 =
1181 
                        ((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) <=
1182 
                        (dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
1183 
                4'b1_100: match1 =
1184 
                        ((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) >
1185 
                        (dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
1186 
                4'b1_101: match1 =
1187 
                        ((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) >=
1188 
                        (dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
1189 
                4'b1_110: match1 =
1190 
                        ((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) !=
1191 
                        (dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
1192 
        endcase
1193 
 
1194 
//
1195 
// Watchpoint 1
1196 
//
1197 
always @(dmr1 or match1 or wp)
1198 
        case (dmr1[`OR1200_DU_DMR1_CW1])
1199 
                2'b00: wp[1] = match1;
1200 
                2'b01: wp[1] = match1 & wp[0];
1201 
                2'b10: wp[1] = match1 | wp[0];
1202 
                2'b11: wp[1] = 1'b0;
1203 
        endcase
1204 
 
1205 
//
1206 
// Compare To What (Match Condition 2)
1207 
//
1208 
always @(dcr2 or id_pc or dcpu_adr_i or dcpu_dat_dc
1209 
        or dcpu_dat_lsu or dcpu_we_i)
1210 
        case (dcr2[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1211 
                3'b001: match_cond2_ct = id_pc;         // insn fetch EA
1212 
                3'b010: match_cond2_ct = dcpu_adr_i;    // load EA
1213 
                3'b011: match_cond2_ct = dcpu_adr_i;    // store EA
1214 
                3'b100: match_cond2_ct = dcpu_dat_dc;   // load data
1215 
                3'b101: match_cond2_ct = dcpu_dat_lsu;  // store data
1216 
                3'b110: match_cond2_ct = dcpu_adr_i;    // load/store EA
1217 
                default:match_cond2_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1218 
        endcase
1219 
 
1220 
//
1221 
// When To Compare (Match Condition 2)
1222 
//
1223 
always @(dcr2 or dcpu_cycstb_i)
1224 
        case (dcr2[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1225 
                3'b000: match_cond2_stb = 1'b0;         //comparison disabled
1226 
                3'b001: match_cond2_stb = 1'b1;         // insn fetch EA
1227 
                default:match_cond2_stb = dcpu_cycstb_i; // any load/store
1228 
        endcase
1229 
 
1230 
//
1231 
// Match Condition 2
1232 
//
1233 
always @(match_cond2_stb or dcr2 or dvr2 or match_cond2_ct)
1234 
        casex ({match_cond2_stb, dcr2[`OR1200_DU_DCR_CC]})
1235 
                4'b0_xxx,
1236 
                4'b1_000,
1237 
                4'b1_111: match2 = 1'b0;
1238 
                4'b1_001: match2 =
1239 
                        ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) ==
1240 
                        (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
1241 
                4'b1_010: match2 =
1242 
                        ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) <
1243 
                        (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
1244 
                4'b1_011: match2 =
1245 
                        ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) <=
1246 
                        (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
1247 
                4'b1_100: match2 =
1248 
                        ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) >
1249 
                        (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
1250 
                4'b1_101: match2 =
1251 
                        ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) >=
1252 
                        (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
1253 
                4'b1_110: match2 =
1254 
                        ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) !=
1255 
                        (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
1256 
        endcase
1257 
 
1258 
//
1259 
// Watchpoint 2
1260 
//
1261 
always @(dmr1 or match2 or wp)
1262 
        case (dmr1[`OR1200_DU_DMR1_CW2])
1263 
                2'b00: wp[2] = match2;
1264 
                2'b01: wp[2] = match2 & wp[1];
1265 
                2'b10: wp[2] = match2 | wp[1];
1266 
                2'b11: wp[2] = 1'b0;
1267 
        endcase
1268 
 
1269 
//
1270 
// Compare To What (Match Condition 3)
1271 
//
1272 
always @(dcr3 or id_pc or dcpu_adr_i or dcpu_dat_dc
1273 
        or dcpu_dat_lsu or dcpu_we_i)
1274 
        case (dcr3[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1275 
                3'b001: match_cond3_ct = id_pc;         // insn fetch EA
1276 
                3'b010: match_cond3_ct = dcpu_adr_i;    // load EA
1277 
                3'b011: match_cond3_ct = dcpu_adr_i;    // store EA
1278 
                3'b100: match_cond3_ct = dcpu_dat_dc;   // load data
1279 
                3'b101: match_cond3_ct = dcpu_dat_lsu;  // store data
1280 
                3'b110: match_cond3_ct = dcpu_adr_i;    // load/store EA
1281 
                default:match_cond3_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1282 
        endcase
1283 
 
1284 
//
1285 
// When To Compare (Match Condition 3)
1286 
//
1287 
always @(dcr3 or dcpu_cycstb_i)
1288 
        case (dcr3[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1289 
                3'b000: match_cond3_stb = 1'b0;         //comparison disabled
1290 
                3'b001: match_cond3_stb = 1'b1;         // insn fetch EA
1291 
                default:match_cond3_stb = dcpu_cycstb_i; // any load/store
1292 
        endcase
1293 
 
1294 
//
1295 
// Match Condition 3
1296 
//
1297 
always @(match_cond3_stb or dcr3 or dvr3 or match_cond3_ct)
1298 
        casex ({match_cond3_stb, dcr3[`OR1200_DU_DCR_CC]})
1299 
                4'b0_xxx,
1300 
                4'b1_000,
1301 
                4'b1_111: match3 = 1'b0;
1302 
                4'b1_001: match3 =
1303 
                        ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) ==
1304 
                        (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
1305 
                4'b1_010: match3 =
1306 
                        ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) <
1307 
                        (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
1308 
                4'b1_011: match3 =
1309 
                        ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) <=
1310 
                        (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
1311 
                4'b1_100: match3 =
1312 
                        ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) >
1313 
                        (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
1314 
                4'b1_101: match3 =
1315 
                        ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) >=
1316 
                        (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
1317 
                4'b1_110: match3 =
1318 
                        ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) !=
1319 
                        (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
1320 
        endcase
1321 
 
1322 
//
1323 
// Watchpoint 3
1324 
//
1325 
always @(dmr1 or match3 or wp)
1326 
        case (dmr1[`OR1200_DU_DMR1_CW3])
1327 
                2'b00: wp[3] = match3;
1328 
                2'b01: wp[3] = match3 & wp[2];
1329 
                2'b10: wp[3] = match3 | wp[2];
1330 
                2'b11: wp[3] = 1'b0;
1331 
        endcase
1332 
 
1333 
//
1334 
// Compare To What (Match Condition 4)
1335 
//
1336 
always @(dcr4 or id_pc or dcpu_adr_i or dcpu_dat_dc
1337 
        or dcpu_dat_lsu or dcpu_we_i)
1338 
        case (dcr4[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1339 
                3'b001: match_cond4_ct = id_pc;         // insn fetch EA
1340 
                3'b010: match_cond4_ct = dcpu_adr_i;    // load EA
1341 
                3'b011: match_cond4_ct = dcpu_adr_i;    // store EA
1342 
                3'b100: match_cond4_ct = dcpu_dat_dc;   // load data
1343 
                3'b101: match_cond4_ct = dcpu_dat_lsu;  // store data
1344 
                3'b110: match_cond4_ct = dcpu_adr_i;    // load/store EA
1345 
                default:match_cond4_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1346 
        endcase
1347 
 
1348 
//
1349 
// When To Compare (Match Condition 4)
1350 
//
1351 
always @(dcr4 or dcpu_cycstb_i)
1352 
        case (dcr4[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1353 
                3'b000: match_cond4_stb = 1'b0;         //comparison disabled
1354 
                3'b001: match_cond4_stb = 1'b1;         // insn fetch EA
1355 
                default:match_cond4_stb = dcpu_cycstb_i; // any load/store
1356 
        endcase
1357 
 
1358 
//
1359 
// Match Condition 4
1360 
//
1361 
always @(match_cond4_stb or dcr4 or dvr4 or match_cond4_ct)
1362 
        casex ({match_cond4_stb, dcr4[`OR1200_DU_DCR_CC]})
1363 
                4'b0_xxx,
1364 
                4'b1_000,
1365 
                4'b1_111: match4 = 1'b0;
1366 
                4'b1_001: match4 =
1367 
                        ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) ==
1368 
                        (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
1369 
                4'b1_010: match4 =
1370 
                        ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) <
1371 
                        (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
1372 
                4'b1_011: match4 =
1373 
                        ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) <=
1374 
                        (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
1375 
                4'b1_100: match4 =
1376 
                        ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) >
1377 
                        (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
1378 
                4'b1_101: match4 =
1379 
                        ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) >=
1380 
                        (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
1381 
                4'b1_110: match4 =
1382 
                        ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) !=
1383 
                        (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
1384 
        endcase
1385 
 
1386 
//
1387 
// Watchpoint 4
1388 
//
1389 
always @(dmr1 or match4 or wp)
1390 
        case (dmr1[`OR1200_DU_DMR1_CW4])
1391 
                2'b00: wp[4] = match4;
1392 
                2'b01: wp[4] = match4 & wp[3];
1393 
                2'b10: wp[4] = match4 | wp[3];
1394 
                2'b11: wp[4] = 1'b0;
1395 
        endcase
1396 
 
1397 
//
1398 
// Compare To What (Match Condition 5)
1399 
//
1400 
always @(dcr5 or id_pc or dcpu_adr_i or dcpu_dat_dc
1401 
        or dcpu_dat_lsu or dcpu_we_i)
1402 
        case (dcr5[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1403 
                3'b001: match_cond5_ct = id_pc;         // insn fetch EA
1404 
                3'b010: match_cond5_ct = dcpu_adr_i;    // load EA
1405 
                3'b011: match_cond5_ct = dcpu_adr_i;    // store EA
1406 
                3'b100: match_cond5_ct = dcpu_dat_dc;   // load data
1407 
                3'b101: match_cond5_ct = dcpu_dat_lsu;  // store data
1408 
                3'b110: match_cond5_ct = dcpu_adr_i;    // load/store EA
1409 
                default:match_cond5_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1410 
        endcase
1411 
 
1412 
//
1413 
// When To Compare (Match Condition 5)
1414 
//
1415 
always @(dcr5 or dcpu_cycstb_i)
1416 
        case (dcr5[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1417 
                3'b000: match_cond5_stb = 1'b0;         //comparison disabled
1418 
                3'b001: match_cond5_stb = 1'b1;         // insn fetch EA
1419 
                default:match_cond5_stb = dcpu_cycstb_i; // any load/store
1420 
        endcase
1421 
 
1422 
//
1423 
// Match Condition 5
1424 
//
1425 
always @(match_cond5_stb or dcr5 or dvr5 or match_cond5_ct)
1426 
        casex ({match_cond5_stb, dcr5[`OR1200_DU_DCR_CC]})
1427 
                4'b0_xxx,
1428 
                4'b1_000,
1429 
                4'b1_111: match5 = 1'b0;
1430 
                4'b1_001: match5 =
1431 
                        ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) ==
1432 
                        (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
1433 
                4'b1_010: match5 =
1434 
                        ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) <
1435 
                        (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
1436 
                4'b1_011: match5 =
1437 
                        ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) <=
1438 
                        (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
1439 
                4'b1_100: match5 =
1440 
                        ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) >
1441 
                        (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
1442 
                4'b1_101: match5 =
1443 
                        ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) >=
1444 
                        (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
1445 
                4'b1_110: match5 =
1446 
                        ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) !=
1447 
                        (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
1448 
        endcase
1449 
 
1450 
//
1451 
// Watchpoint 5
1452 
//
1453 
always @(dmr1 or match5 or wp)
1454 
        case (dmr1[`OR1200_DU_DMR1_CW5])
1455 
                2'b00: wp[5] = match5;
1456 
                2'b01: wp[5] = match5 & wp[4];
1457 
                2'b10: wp[5] = match5 | wp[4];
1458 
                2'b11: wp[5] = 1'b0;
1459 
        endcase
1460 
 
1461 
//
1462 
// Compare To What (Match Condition 6)
1463 
//
1464 
always @(dcr6 or id_pc or dcpu_adr_i or dcpu_dat_dc
1465 
        or dcpu_dat_lsu or dcpu_we_i)
1466 
        case (dcr6[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1467 
                3'b001: match_cond6_ct = id_pc;         // insn fetch EA
1468 
                3'b010: match_cond6_ct = dcpu_adr_i;    // load EA
1469 
                3'b011: match_cond6_ct = dcpu_adr_i;    // store EA
1470 
                3'b100: match_cond6_ct = dcpu_dat_dc;   // load data
1471 
                3'b101: match_cond6_ct = dcpu_dat_lsu;  // store data
1472 
                3'b110: match_cond6_ct = dcpu_adr_i;    // load/store EA
1473 
                default:match_cond6_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1474 
        endcase
1475 
 
1476 
//
1477 
// When To Compare (Match Condition 6)
1478 
//
1479 
always @(dcr6 or dcpu_cycstb_i)
1480 
        case (dcr6[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1481 
                3'b000: match_cond6_stb = 1'b0;         //comparison disabled
1482 
                3'b001: match_cond6_stb = 1'b1;         // insn fetch EA
1483 
                default:match_cond6_stb = dcpu_cycstb_i; // any load/store
1484 
        endcase
1485 
 
1486 
//
1487 
// Match Condition 6
1488 
//
1489 
always @(match_cond6_stb or dcr6 or dvr6 or match_cond6_ct)
1490 
        casex ({match_cond6_stb, dcr6[`OR1200_DU_DCR_CC]})
1491 
                4'b0_xxx,
1492 
                4'b1_000,
1493 
                4'b1_111: match6 = 1'b0;
1494 
                4'b1_001: match6 =
1495 
                        ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) ==
1496 
                        (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
1497 
                4'b1_010: match6 =
1498 
                        ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) <
1499 
                        (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
1500 
                4'b1_011: match6 =
1501 
                        ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) <=
1502 
                        (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
1503 
                4'b1_100: match6 =
1504 
                        ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) >
1505 
                        (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
1506 
                4'b1_101: match6 =
1507 
                        ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) >=
1508 
                        (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
1509 
                4'b1_110: match6 =
1510 
                        ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) !=
1511 
                        (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
1512 
        endcase
1513 
 
1514 
//
1515 
// Watchpoint 6
1516 
//
1517 
always @(dmr1 or match6 or wp)
1518 
        case (dmr1[`OR1200_DU_DMR1_CW6])
1519 
                2'b00: wp[6] = match6;
1520 
                2'b01: wp[6] = match6 & wp[5];
1521 
                2'b10: wp[6] = match6 | wp[5];
1522 
                2'b11: wp[6] = 1'b0;
1523 
        endcase
1524 
 
1525 
//
1526 
// Compare To What (Match Condition 7)
1527 
//
1528 
always @(dcr7 or id_pc or dcpu_adr_i or dcpu_dat_dc
1529 
        or dcpu_dat_lsu or dcpu_we_i)
1530 
        case (dcr7[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1531 
                3'b001: match_cond7_ct = id_pc;         // insn fetch EA
1532 
                3'b010: match_cond7_ct = dcpu_adr_i;    // load EA
1533 
                3'b011: match_cond7_ct = dcpu_adr_i;    // store EA
1534 
                3'b100: match_cond7_ct = dcpu_dat_dc;   // load data
1535 
                3'b101: match_cond7_ct = dcpu_dat_lsu;  // store data
1536 
                3'b110: match_cond7_ct = dcpu_adr_i;    // load/store EA
1537 
                default:match_cond7_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1538 
        endcase
1539 
 
1540 
//
1541 
// When To Compare (Match Condition 7)
1542 
//
1543 
always @(dcr7 or dcpu_cycstb_i)
1544 
        case (dcr7[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1545 
                3'b000: match_cond7_stb = 1'b0;         //comparison disabled
1546 
                3'b001: match_cond7_stb = 1'b1;         // insn fetch EA
1547 
                default:match_cond7_stb = dcpu_cycstb_i; // any load/store
1548 
        endcase
1549 
 
1550 
//
1551 
// Match Condition 7
1552 
//
1553 
always @(match_cond7_stb or dcr7 or dvr7 or match_cond7_ct)
1554 
        casex ({match_cond7_stb, dcr7[`OR1200_DU_DCR_CC]})
1555 
                4'b0_xxx,
1556 
                4'b1_000,
1557 
                4'b1_111: match7 = 1'b0;
1558 
                4'b1_001: match7 =
1559 
                        ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) ==
1560 
                        (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
1561 
                4'b1_010: match7 =
1562 
                        ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) <
1563 
                        (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
1564 
                4'b1_011: match7 =
1565 
                        ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) <=
1566 
                        (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
1567 
                4'b1_100: match7 =
1568 
                        ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) >
1569 
                        (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
1570 
                4'b1_101: match7 =
1571 
                        ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) >=
1572 
                        (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
1573 
                4'b1_110: match7 =
1574 
                        ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) !=
1575 
                        (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
1576 
        endcase
1577 
 
1578 
//
1579 
// Watchpoint 7
1580 
//
1581 
always @(dmr1 or match7 or wp)
1582 
        case (dmr1[`OR1200_DU_DMR1_CW7])
1583 
                2'b00: wp[7] = match7;
1584 
                2'b01: wp[7] = match7 & wp[6];
1585 
                2'b10: wp[7] = match7 | wp[6];
1586 
                2'b11: wp[7] = 1'b0;
1587 
        endcase
1588 
 
1589 
//
1590 
// Increment Watchpoint Counter 0
1591 
//
1592 
always @(wp or dmr2)
1593 
        if (dmr2[`OR1200_DU_DMR2_WCE0])
1594 
                incr_wpcntr0 = |(wp & ~dmr2[`OR1200_DU_DMR2_AWTC]);
1595 
        else
1596 
                incr_wpcntr0 = 1'b0;
1597 
 
1598 
//
1599 
// Match Condition Watchpoint Counter 0
1600 
//
1601 
always @(dwcr0)
1602 
        if (dwcr0[`OR1200_DU_DWCR_MATCH] == dwcr0[`OR1200_DU_DWCR_COUNT])
1603 
                wpcntr0_match = 1'b1;
1604 
        else
1605 
                wpcntr0_match = 1'b0;
1606 
 
1607 
 
1608 
//
1609 
// Watchpoint 8
1610 
//
1611 
always @(dmr1 or wpcntr0_match or wp)
1612 
        case (dmr1[`OR1200_DU_DMR1_CW8])
1613 
                2'b00: wp[8] = wpcntr0_match;
1614 
                2'b01: wp[8] = wpcntr0_match & wp[7];
1615 
                2'b10: wp[8] = wpcntr0_match | wp[7];
1616 
                2'b11: wp[8] = 1'b0;
1617 
        endcase
1618 
 
1619 
 
1620 
//
1621 
// Increment Watchpoint Counter 1
1622 
//
1623 
always @(wp or dmr2)
1624 
        if (dmr2[`OR1200_DU_DMR2_WCE1])
1625 
                incr_wpcntr1 = |(wp & dmr2[`OR1200_DU_DMR2_AWTC]);
1626 
        else
1627 
                incr_wpcntr1 = 1'b0;
1628 
 
1629 
//
1630 
// Match Condition Watchpoint Counter 1
1631 
//
1632 
always @(dwcr1)
1633 
        if (dwcr1[`OR1200_DU_DWCR_MATCH] == dwcr1[`OR1200_DU_DWCR_COUNT])
1634 
                wpcntr1_match = 1'b1;
1635 
        else
1636 
                wpcntr1_match = 1'b0;
1637 
 
1638 
//
1639 
// Watchpoint 9
1640 
//
1641 
always @(dmr1 or wpcntr1_match or wp)
1642 
        case (dmr1[`OR1200_DU_DMR1_CW9])
1643 
                2'b00: wp[9] = wpcntr1_match;
1644 
                2'b01: wp[9] = wpcntr1_match & wp[8];
1645 
                2'b10: wp[9] = wpcntr1_match | wp[8];
1646 
                2'b11: wp[9] = 1'b0;
1647 
        endcase
1648 
 
1649 
//
1650 
// Watchpoint 10
1651 
//
1652 
always @(dmr1 or dbg_ewt_i or wp)
1653 
        case (dmr1[`OR1200_DU_DMR1_CW10])
1654 
                2'b00: wp[10] = dbg_ewt_i;
1655 
                2'b01: wp[10] = dbg_ewt_i & wp[9];
1656 
                2'b10: wp[10] = dbg_ewt_i | wp[9];
1657 
                2'b11: wp[10] = 1'b0;
1658 
        endcase
1659 
 
1660 
`endif
1661 
 
1662 
//
1663 
// Watchpoints can cause trap exception
1664 
//
1665 
`ifdef OR1200_DU_HWBKPTS
1666 
assign du_hwbkpt = |(wp & dmr2[`OR1200_DU_DMR2_WGB]);
1667 
`else
1668 
assign du_hwbkpt = 1'b0;
1669 
`endif
1670 
 
1671 
`ifdef OR1200_DU_TB_IMPLEMENTED
1672 
//
1673 
// Simple trace buffer
1674 
// (right now hardcoded for Xilinx Virtex FPGAs)
1675 
//
1676 
// Stores last 256 instruction addresses, instruction
1677 
// machine words and ALU results
1678 
//
1679 
 
1680 
//
1681 
// Trace buffer write enable
1682 
//
1683 
assign tb_enw = ~ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]);
1684 
 
1685 
//
1686 
// Trace buffer write address pointer
1687 
//
1688 
always @(posedge clk or posedge rst)
1689 
        if (rst)
1690 
                tb_wadr <= #1 8'h00;
1691 
        else if (tb_enw)
1692 
                tb_wadr <= #1 tb_wadr + 8'd1;
1693 
 
1694 
//
1695 
// Free running counter (time stamp)
1696 
//
1697 
always @(posedge clk or posedge rst)
1698 
        if (rst)
1699 
                tb_timstmp <= #1 32'h00000000;
1700 
        else if (!dbg_bp_r)
1701 
                tb_timstmp <= #1 tb_timstmp + 32'd1;
1702 
 
1703 
//
1704 
// Trace buffer RAMs
1705 
//
1706 
 
1707 
or1200_dpram_256x32 tbia_ram(
1708 
        .clk_a(clk),
1709 
        .rst_a(rst),
1710 
        .addr_a(spr_addr[7:0]),
1711 
        .ce_a(1'b1),
1712 
        .oe_a(1'b1),
1713 
        .do_a(tbia_dat_o),
1714 
 
1715 
        .clk_b(clk),
1716 
        .rst_b(rst),
1717 
        .addr_b(tb_wadr),
1718 
        .di_b(spr_dat_npc),
1719 
        .ce_b(1'b1),
1720 
        .we_b(tb_enw)
1721 
 
1722 
);
1723 
 
1724 
or1200_dpram_256x32 tbim_ram(
1725 
        .clk_a(clk),
1726 
        .rst_a(rst),
1727 
        .addr_a(spr_addr[7:0]),
1728 
        .ce_a(1'b1),
1729 
        .oe_a(1'b1),
1730 
        .do_a(tbim_dat_o),
1731 
 
1732 
        .clk_b(clk),
1733 
        .rst_b(rst),
1734 
        .addr_b(tb_wadr),
1735 
        .di_b(ex_insn),
1736 
        .ce_b(1'b1),
1737 
        .we_b(tb_enw)
1738 
);
1739 
 
1740 
or1200_dpram_256x32 tbar_ram(
1741 
        .clk_a(clk),
1742 
        .rst_a(rst),
1743 
        .addr_a(spr_addr[7:0]),
1744 
        .ce_a(1'b1),
1745 
        .oe_a(1'b1),
1746 
        .do_a(tbar_dat_o),
1747 
 
1748 
        .clk_b(clk),
1749 
        .rst_b(rst),
1750 
        .addr_b(tb_wadr),
1751 
        .di_b(rf_dataw),
1752 
        .ce_b(1'b1),
1753 
        .we_b(tb_enw)
1754 
);
1755 
 
1756 
or1200_dpram_256x32 tbts_ram(
1757 
        .clk_a(clk),
1758 
        .rst_a(rst),
1759 
        .addr_a(spr_addr[7:0]),
1760 
        .ce_a(1'b1),
1761 
        .oe_a(1'b1),
1762 
        .do_a(tbts_dat_o),
1763 
 
1764 
        .clk_b(clk),
1765 
        .rst_b(rst),
1766 
        .addr_b(tb_wadr),
1767 
        .di_b(tb_timstmp),
1768 
        .ce_b(1'b1),
1769 
        .we_b(tb_enw)
1770 
);
1771 
 
1772 
`else
1773 
 
1774 
assign tbia_dat_o = 32'h0000_0000;
1775 
assign tbim_dat_o = 32'h0000_0000;
1776 
assign tbar_dat_o = 32'h0000_0000;
1777 
assign tbts_dat_o = 32'h0000_0000;
1778 
 
1779 
`endif  // OR1200_DU_TB_IMPLEMENTED
1780 
 
1781 
`else   // OR1200_DU_IMPLEMENTED
1782 
 
1783 
//
1784 
// When DU is not implemented, drive all outputs as would when DU is disabled
1785 
//
1786 
assign dbg_bp_o = 1'b0;
1787 
assign du_dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
1788 
assign du_hwbkpt = 1'b0;
1789 
 
1790 
//
1791 
// Read DU registers
1792 
//
1793 
`ifdef OR1200_DU_READREGS
1794 
assign spr_dat_o = 32'h0000_0000;
1795 
`ifdef OR1200_DU_UNUSED_ZERO
1796 
`endif
1797 
`endif
1798 
 
1799 
`endif
1800 
 
1801 
endmodule

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