URL https://opencores.org/ocsvn/or1k_soc_on_altera_embedded_dev_kit/or1k_soc_on_altera_embedded_dev_kit/trunk

Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [or1200/] [rtl/] [verilog/] [or1200_lsu.v] - Blame information for rev 12

Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Load/Store unit                                    ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Interface between CPU and DC.                               ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_lsu.v,v $
// Revision 1.5  2004/04/05 08:29:57  lampret
// Merged branch_qmem into main tree.
//
// Revision 1.4  2002/03/29 15:16:56  lampret
// Some of the warnings fixed.
//
// Revision 1.3  2002/02/11 04:33:17  lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.2  2002/01/18 07:56:00  lampret
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.9  2001/11/30 18:59:47  simons
// *** empty log message ***
//
// Revision 1.8  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_lsu(
 
        // Internal i/f
        addrbase, addrofs, lsu_op, lsu_datain, lsu_dataout, lsu_stall, lsu_unstall,
        du_stall, except_align, except_dtlbmiss, except_dmmufault, except_dbuserr,
 
        // External i/f to DC
        dcpu_adr_o, dcpu_cycstb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o, dcpu_dat_o,
        dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i
);
 
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
 
//
// I/O
//
 
//
// Internal i/f
//
input   [31:0]                   addrbase;
input   [31:0]                   addrofs;
input   [`OR1200_LSUOP_WIDTH-1:0]        lsu_op;
input   [dw-1:0]         lsu_datain;
output  [dw-1:0]         lsu_dataout;
output                          lsu_stall;
output                          lsu_unstall;
input                           du_stall;
output                          except_align;
output                          except_dtlbmiss;
output                          except_dmmufault;
output                          except_dbuserr;
 
//
// External i/f to DC
//
output  [31:0]                   dcpu_adr_o;
output                          dcpu_cycstb_o;
output                          dcpu_we_o;
output  [3:0]                    dcpu_sel_o;
output  [3:0]                    dcpu_tag_o;
output  [31:0]                   dcpu_dat_o;
input   [31:0]                   dcpu_dat_i;
input                           dcpu_ack_i;
input                           dcpu_rty_i;
input                           dcpu_err_i;
input   [3:0]                    dcpu_tag_i;
 
//
// Internal wires/regs
//
reg     [3:0]                    dcpu_sel_o;
 
//
// Internal I/F assignments
//
assign lsu_stall = dcpu_rty_i & dcpu_cycstb_o;
assign lsu_unstall = dcpu_ack_i;
assign except_align = ((lsu_op == `OR1200_LSUOP_SH) | (lsu_op == `OR1200_LSUOP_LHZ) | (lsu_op == `OR1200_LSUOP_LHS)) & dcpu_adr_o[0]
                |  ((lsu_op == `OR1200_LSUOP_SW) | (lsu_op == `OR1200_LSUOP_LWZ) | (lsu_op == `OR1200_LSUOP_LWS)) & |dcpu_adr_o[1:0];
assign except_dtlbmiss = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_TE);
assign except_dmmufault = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_PE);
assign except_dbuserr = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_BE);
 
//
// External I/F assignments
//
assign dcpu_adr_o = addrbase + addrofs;
assign dcpu_cycstb_o = du_stall | lsu_unstall | except_align ? 1'b0 : |lsu_op;
assign dcpu_we_o = lsu_op[3];
assign dcpu_tag_o = dcpu_cycstb_o ? `OR1200_DTAG_ND : `OR1200_DTAG_IDLE;
always @(lsu_op or dcpu_adr_o)
        casex({lsu_op, dcpu_adr_o[1:0]})
                {`OR1200_LSUOP_SB, 2'b00} : dcpu_sel_o = 4'b1000;
                {`OR1200_LSUOP_SB, 2'b01} : dcpu_sel_o = 4'b0100;
                {`OR1200_LSUOP_SB, 2'b10} : dcpu_sel_o = 4'b0010;
                {`OR1200_LSUOP_SB, 2'b11} : dcpu_sel_o = 4'b0001;
                {`OR1200_LSUOP_SH, 2'b00} : dcpu_sel_o = 4'b1100;
                {`OR1200_LSUOP_SH, 2'b10} : dcpu_sel_o = 4'b0011;
                {`OR1200_LSUOP_SW, 2'b00} : dcpu_sel_o = 4'b1111;
                {`OR1200_LSUOP_LBZ, 2'b00}, {`OR1200_LSUOP_LBS, 2'b00} : dcpu_sel_o = 4'b1000;
                {`OR1200_LSUOP_LBZ, 2'b01}, {`OR1200_LSUOP_LBS, 2'b01} : dcpu_sel_o = 4'b0100;
                {`OR1200_LSUOP_LBZ, 2'b10}, {`OR1200_LSUOP_LBS, 2'b10} : dcpu_sel_o = 4'b0010;
                {`OR1200_LSUOP_LBZ, 2'b11}, {`OR1200_LSUOP_LBS, 2'b11} : dcpu_sel_o = 4'b0001;
                {`OR1200_LSUOP_LHZ, 2'b00}, {`OR1200_LSUOP_LHS, 2'b00} : dcpu_sel_o = 4'b1100;
                {`OR1200_LSUOP_LHZ, 2'b10}, {`OR1200_LSUOP_LHS, 2'b10} : dcpu_sel_o = 4'b0011;
                {`OR1200_LSUOP_LWZ, 2'b00}, {`OR1200_LSUOP_LWS, 2'b00} : dcpu_sel_o = 4'b1111;
                default : dcpu_sel_o = 4'b0000;
        endcase
 
//
// Instantiation of Memory-to-regfile aligner
//
or1200_mem2reg or1200_mem2reg(
        .addr(dcpu_adr_o[1:0]),
        .lsu_op(lsu_op),
        .memdata(dcpu_dat_i),
        .regdata(lsu_dataout)
);
 
//
// Instantiation of Regfile-to-memory aligner
//
or1200_reg2mem or1200_reg2mem(
        .addr(dcpu_adr_o[1:0]),
        .lsu_op(lsu_op),
        .regdata(lsu_datain),
        .memdata(dcpu_dat_o)
);
 
endmodule

Line No.	Rev	Author	Line
1	12	xianfeng	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Load/Store unit ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Interface between CPU and DC. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: or1200_lsu.v,v $`
47			`// Revision 1.5 2004/04/05 08:29:57 lampret`
48			`// Merged branch_qmem into main tree.`
49			`//`
50			`// Revision 1.4 2002/03/29 15:16:56 lampret`
51			`// Some of the warnings fixed.`
52			`//`
53			`// Revision 1.3 2002/02/11 04:33:17 lampret`
54			`// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.`
55			`//`
56			`// Revision 1.2 2002/01/18 07:56:00 lampret`
57			`// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.`
58			`//`
59			`// Revision 1.1 2002/01/03 08:16:15 lampret`
60			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
61			`//`
62			`// Revision 1.9 2001/11/30 18:59:47 simons`
63			`// * empty log message *`
64			`//`
65			`// Revision 1.8 2001/10/21 17:57:16 lampret`
66			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
67			`//`
68			`// Revision 1.7 2001/10/14 13:12:09 lampret`
69			`// MP3 version.`
70			`//`
71			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
72			`// no message`
73			`//`
74			`// Revision 1.2 2001/08/09 13:39:33 lampret`
75			`// Major clean-up.`
76			`//`
77			`// Revision 1.1 2001/07/20 00:46:03 lampret`
78			`// Development version of RTL. Libraries are missing.`
79			`//`
80			`//`
81
82			`// synopsys translate_off`
83			`include "timescale.v"
84			`// synopsys translate_on`
85			`include "or1200_defines.v"
86
87			`module or1200_lsu(`
88
89			`// Internal i/f`
90			`addrbase, addrofs, lsu_op, lsu_datain, lsu_dataout, lsu_stall, lsu_unstall,`
91			`du_stall, except_align, except_dtlbmiss, except_dmmufault, except_dbuserr,`
92
93			`// External i/f to DC`
94			`dcpu_adr_o, dcpu_cycstb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o, dcpu_dat_o,`
95			`dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i`
96			`);`
97
98			parameter dw = `OR1200_OPERAND_WIDTH;
99			parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
100
101			`//`
102			`// I/O`
103			`//`
104
105			`//`
106			`// Internal i/f`
107			`//`
108			`input [31:0] addrbase;`
109			`input [31:0] addrofs;`
110			input [`OR1200_LSUOP_WIDTH-1:0] lsu_op;
111			`input [dw-1:0] lsu_datain;`
112			`output [dw-1:0] lsu_dataout;`
113			`output lsu_stall;`
114			`output lsu_unstall;`
115			`input du_stall;`
116			`output except_align;`
117			`output except_dtlbmiss;`
118			`output except_dmmufault;`
119			`output except_dbuserr;`
120
121			`//`
122			`// External i/f to DC`
123			`//`
124			`output [31:0] dcpu_adr_o;`
125			`output dcpu_cycstb_o;`
126			`output dcpu_we_o;`
127			`output [3:0] dcpu_sel_o;`
128			`output [3:0] dcpu_tag_o;`
129			`output [31:0] dcpu_dat_o;`
130			`input [31:0] dcpu_dat_i;`
131			`input dcpu_ack_i;`
132			`input dcpu_rty_i;`
133			`input dcpu_err_i;`
134			`input [3:0] dcpu_tag_i;`
135
136			`//`
137			`// Internal wires/regs`
138			`//`
139			`reg [3:0] dcpu_sel_o;`
140
141			`//`
142			`// Internal I/F assignments`
143			`//`
144			`assign lsu_stall = dcpu_rty_i & dcpu_cycstb_o;`
145			`assign lsu_unstall = dcpu_ack_i;`
146			assign except_align = ((lsu_op == `OR1200_LSUOP_SH) \| (lsu_op == `OR1200_LSUOP_LHZ) \| (lsu_op == `OR1200_LSUOP_LHS)) & dcpu_adr_o[0]
147			\| ((lsu_op == `OR1200_LSUOP_SW) \| (lsu_op == `OR1200_LSUOP_LWZ) \| (lsu_op == `OR1200_LSUOP_LWS)) & \|dcpu_adr_o[1:0];
148			assign except_dtlbmiss = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_TE);
149			assign except_dmmufault = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_PE);
150			assign except_dbuserr = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_BE);
151
152			`//`
153			`// External I/F assignments`
154			`//`
155			`assign dcpu_adr_o = addrbase + addrofs;`
156			`assign dcpu_cycstb_o = du_stall \| lsu_unstall \| except_align ? 1'b0 : \|lsu_op;`
157			`assign dcpu_we_o = lsu_op[3];`
158			assign dcpu_tag_o = dcpu_cycstb_o ? `OR1200_DTAG_ND : `OR1200_DTAG_IDLE;
159			`always @(lsu_op or dcpu_adr_o)`
160			`casex({lsu_op, dcpu_adr_o[1:0]})`
161			{`OR1200_LSUOP_SB, 2'b00} : dcpu_sel_o = 4'b1000;
162			{`OR1200_LSUOP_SB, 2'b01} : dcpu_sel_o = 4'b0100;
163			{`OR1200_LSUOP_SB, 2'b10} : dcpu_sel_o = 4'b0010;
164			{`OR1200_LSUOP_SB, 2'b11} : dcpu_sel_o = 4'b0001;
165			{`OR1200_LSUOP_SH, 2'b00} : dcpu_sel_o = 4'b1100;
166			{`OR1200_LSUOP_SH, 2'b10} : dcpu_sel_o = 4'b0011;
167			{`OR1200_LSUOP_SW, 2'b00} : dcpu_sel_o = 4'b1111;
168			{`OR1200_LSUOP_LBZ, 2'b00}, {`OR1200_LSUOP_LBS, 2'b00} : dcpu_sel_o = 4'b1000;
169			{`OR1200_LSUOP_LBZ, 2'b01}, {`OR1200_LSUOP_LBS, 2'b01} : dcpu_sel_o = 4'b0100;
170			{`OR1200_LSUOP_LBZ, 2'b10}, {`OR1200_LSUOP_LBS, 2'b10} : dcpu_sel_o = 4'b0010;
171			{`OR1200_LSUOP_LBZ, 2'b11}, {`OR1200_LSUOP_LBS, 2'b11} : dcpu_sel_o = 4'b0001;
172			{`OR1200_LSUOP_LHZ, 2'b00}, {`OR1200_LSUOP_LHS, 2'b00} : dcpu_sel_o = 4'b1100;
173			{`OR1200_LSUOP_LHZ, 2'b10}, {`OR1200_LSUOP_LHS, 2'b10} : dcpu_sel_o = 4'b0011;
174			{`OR1200_LSUOP_LWZ, 2'b00}, {`OR1200_LSUOP_LWS, 2'b00} : dcpu_sel_o = 4'b1111;
175			`default : dcpu_sel_o = 4'b0000;`
176			`endcase`
177
178			`//`
179			`// Instantiation of Memory-to-regfile aligner`
180			`//`
181			`or1200_mem2reg or1200_mem2reg(`
182			`.addr(dcpu_adr_o[1:0]),`
183			`.lsu_op(lsu_op),`
184			`.memdata(dcpu_dat_i),`
185			`.regdata(lsu_dataout)`
186			`);`
187
188			`//`
189			`// Instantiation of Regfile-to-memory aligner`
190			`//`
191			`or1200_reg2mem or1200_reg2mem(`
192			`.addr(dcpu_adr_o[1:0]),`
193			`.lsu_op(lsu_op),`
194			`.regdata(lsu_datain),`
195			`.memdata(dcpu_dat_o)`
196			`);`
197
198			`endmodule`

Browse

Tools

Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [or1200/] [rtl/] [verilog/] [or1200_lsu.v] - Blame information for rev 12