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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [or1200/] [rtl/] [verilog/] [or1200_mem2reg.v] - Blame information for rev 12

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's mem2reg alignment                                  ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Two versions of Memory to register data alignment.          ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_mem2reg.v,v $
// Revision 1.5  2002/09/03 22:28:21  lampret
// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
//
// Revision 1.4  2002/03/29 15:16:56  lampret
// Some of the warnings fixed.
//
// Revision 1.3  2002/03/28 19:14:10  lampret
// Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2
//
// Revision 1.2  2002/01/14 06:18:22  lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.9  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8  2001/10/19 23:28:46  lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_mem2reg(addr, lsu_op, memdata, regdata);
 
parameter width = `OR1200_OPERAND_WIDTH;
 
//
// I/O
//
input   [1:0]                    addr;
input   [`OR1200_LSUOP_WIDTH-1:0]        lsu_op;
input   [width-1:0]              memdata;
output  [width-1:0]              regdata;
 
 
//
// In the past faster implementation of mem2reg (today probably slower)
//
`ifdef OR1200_IMPL_MEM2REG2
 
`define OR1200_M2R_BYTE0 4'b0000
`define OR1200_M2R_BYTE1 4'b0001
`define OR1200_M2R_BYTE2 4'b0010
`define OR1200_M2R_BYTE3 4'b0011
`define OR1200_M2R_EXTB0 4'b0100
`define OR1200_M2R_EXTB1 4'b0101
`define OR1200_M2R_EXTB2 4'b0110
`define OR1200_M2R_EXTB3 4'b0111
`define OR1200_M2R_ZERO  4'b0000
 
reg     [7:0]                    regdata_hh;
reg     [7:0]                    regdata_hl;
reg     [7:0]                    regdata_lh;
reg     [7:0]                    regdata_ll;
reg     [width-1:0]              aligned;
reg     [3:0]                    sel_byte0, sel_byte1,
                                sel_byte2, sel_byte3;
 
assign regdata = {regdata_hh, regdata_hl, regdata_lh, regdata_ll};
 
//
// Byte select 0
//
always @(addr or lsu_op) begin
        casex({lsu_op[2:0], addr})       // synopsys parallel_case
                {3'b01x, 2'b00}:                        // lbz/lbs 0
                        sel_byte0 = `OR1200_M2R_BYTE3;  // take byte 3
                {3'b01x, 2'b01},                        // lbz/lbs 1
                {3'b10x, 2'b00}:                        // lhz/lhs 0
                        sel_byte0 = `OR1200_M2R_BYTE2;  // take byte 2
                {3'b01x, 2'b10}:                        // lbz/lbs 2
                        sel_byte0 = `OR1200_M2R_BYTE1;  // take byte 1
                default:                                // all other cases
                        sel_byte0 = `OR1200_M2R_BYTE0;  // take byte 0
        endcase
end
 
//
// Byte select 1
//
always @(addr or lsu_op) begin
        casex({lsu_op[2:0], addr})       // synopsys parallel_case
                {3'b010, 2'bxx}:                        // lbz
                        sel_byte1 = `OR1200_M2R_ZERO;   // zero extend
                {3'b011, 2'b00}:                        // lbs 0
                        sel_byte1 = `OR1200_M2R_EXTB3;  // sign extend from byte 3
                {3'b011, 2'b01}:                        // lbs 1
                        sel_byte1 = `OR1200_M2R_EXTB2;  // sign extend from byte 2
                {3'b011, 2'b10}:                        // lbs 2
                        sel_byte1 = `OR1200_M2R_EXTB1;  // sign extend from byte 1
                {3'b011, 2'b11}:                        // lbs 3
                        sel_byte1 = `OR1200_M2R_EXTB0;  // sign extend from byte 0
                {3'b10x, 2'b00}:                        // lhz/lhs 0
                        sel_byte1 = `OR1200_M2R_BYTE3;  // take byte 3
                default:                                // all other cases
                        sel_byte1 = `OR1200_M2R_BYTE1;  // take byte 1
        endcase
end
 
//
// Byte select 2
//
always @(addr or lsu_op) begin
        casex({lsu_op[2:0], addr})       // synopsys parallel_case
                {3'b010, 2'bxx},                        // lbz
                {3'b100, 2'bxx}:                        // lhz
                        sel_byte2 = `OR1200_M2R_ZERO;   // zero extend
                {3'b011, 2'b00},                        // lbs 0
                {3'b101, 2'b00}:                        // lhs 0
                        sel_byte2 = `OR1200_M2R_EXTB3;  // sign extend from byte 3
                {3'b011, 2'b01}:                        // lbs 1
                        sel_byte2 = `OR1200_M2R_EXTB2;  // sign extend from byte 2
                {3'b011, 2'b10},                        // lbs 2
                {3'b101, 2'b10}:                        // lhs 0
                        sel_byte2 = `OR1200_M2R_EXTB1;  // sign extend from byte 1
                {3'b011, 2'b11}:                        // lbs 3
                        sel_byte2 = `OR1200_M2R_EXTB0;  // sign extend from byte 0
                default:                                // all other cases
                        sel_byte2 = `OR1200_M2R_BYTE2;  // take byte 2
        endcase
end
 
//
// Byte select 3
//
always @(addr or lsu_op) begin
        casex({lsu_op[2:0], addr}) // synopsys parallel_case
                {3'b010, 2'bxx},                        // lbz
                {3'b100, 2'bxx}:                        // lhz
                        sel_byte3 = `OR1200_M2R_ZERO;   // zero extend
                {3'b011, 2'b00},                        // lbs 0
                {3'b101, 2'b00}:                        // lhs 0
                        sel_byte3 = `OR1200_M2R_EXTB3;  // sign extend from byte 3
                {3'b011, 2'b01}:                        // lbs 1
                        sel_byte3 = `OR1200_M2R_EXTB2;  // sign extend from byte 2
                {3'b011, 2'b10},                        // lbs 2
                {3'b101, 2'b10}:                        // lhs 0
                        sel_byte3 = `OR1200_M2R_EXTB1;  // sign extend from byte 1
                {3'b011, 2'b11}:                        // lbs 3
                        sel_byte3 = `OR1200_M2R_EXTB0;  // sign extend from byte 0
                default:                                // all other cases
                        sel_byte3 = `OR1200_M2R_BYTE3;  // take byte 3
        endcase
end
 
//
// Byte 0
//
always @(sel_byte0 or memdata) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
`ifdef OR1200_CASE_DEFAULT
        case(sel_byte0) // synopsys parallel_case infer_mux
`else
        case(sel_byte0) // synopsys full_case parallel_case infer_mux
`endif
`else
`ifdef OR1200_CASE_DEFAULT
        case(sel_byte0) // synopsys parallel_case
`else
        case(sel_byte0) // synopsys full_case parallel_case
`endif
`endif
                `OR1200_M2R_BYTE0: begin
                                regdata_ll = memdata[7:0];
                        end
                `OR1200_M2R_BYTE1: begin
                                regdata_ll = memdata[15:8];
                        end
                `OR1200_M2R_BYTE2: begin
                                regdata_ll = memdata[23:16];
                        end
`ifdef OR1200_CASE_DEFAULT
                default: begin
`else
                `OR1200_M2R_BYTE3: begin
`endif
                                regdata_ll = memdata[31:24];
                        end
        endcase
end
 
//
// Byte 1
//
always @(sel_byte1 or memdata) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
`ifdef OR1200_CASE_DEFAULT
        case(sel_byte1) // synopsys parallel_case infer_mux
`else
        case(sel_byte1) // synopsys full_case parallel_case infer_mux
`endif
`else
`ifdef OR1200_CASE_DEFAULT
        case(sel_byte1) // synopsys parallel_case
`else
        case(sel_byte1) // synopsys full_case parallel_case
`endif
`endif
                `OR1200_M2R_ZERO: begin
                                regdata_lh = 8'h00;
                        end
                `OR1200_M2R_BYTE1: begin
                                regdata_lh = memdata[15:8];
                        end
                `OR1200_M2R_BYTE3: begin
                                regdata_lh = memdata[31:24];
                        end
                `OR1200_M2R_EXTB0: begin
                                regdata_lh = {8{memdata[7]}};
                        end
                `OR1200_M2R_EXTB1: begin
                                regdata_lh = {8{memdata[15]}};
                        end
                `OR1200_M2R_EXTB2: begin
                                regdata_lh = {8{memdata[23]}};
                        end
`ifdef OR1200_CASE_DEFAULT
                default: begin
`else
                `OR1200_M2R_EXTB3: begin
`endif
                                regdata_lh = {8{memdata[31]}};
                        end
        endcase
end
 
//
// Byte 2
//
always @(sel_byte2 or memdata) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
`ifdef OR1200_CASE_DEFAULT
        case(sel_byte2) // synopsys parallel_case infer_mux
`else
        case(sel_byte2) // synopsys full_case parallel_case infer_mux
`endif
`else
`ifdef OR1200_CASE_DEFAULT
        case(sel_byte2) // synopsys parallel_case
`else
        case(sel_byte2) // synopsys full_case parallel_case
`endif
`endif
                `OR1200_M2R_ZERO: begin
                                regdata_hl = 8'h00;
                        end
                `OR1200_M2R_BYTE2: begin
                                regdata_hl = memdata[23:16];
                        end
                `OR1200_M2R_EXTB0: begin
                                regdata_hl = {8{memdata[7]}};
                        end
                `OR1200_M2R_EXTB1: begin
                                regdata_hl = {8{memdata[15]}};
                        end
                `OR1200_M2R_EXTB2: begin
                                regdata_hl = {8{memdata[23]}};
                        end
`ifdef OR1200_CASE_DEFAULT
                default: begin
`else
                `OR1200_M2R_EXTB3: begin
`endif
                                regdata_hl = {8{memdata[31]}};
                        end
        endcase
end
 
//
// Byte 3
//
always @(sel_byte3 or memdata) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
`ifdef OR1200_CASE_DEFAULT
        case(sel_byte3) // synopsys parallel_case infer_mux
`else
        case(sel_byte3) // synopsys full_case parallel_case infer_mux
`endif
`else
`ifdef OR1200_CASE_DEFAULT
        case(sel_byte3) // synopsys parallel_case
`else
        case(sel_byte3) // synopsys full_case parallel_case
`endif
`endif
                `OR1200_M2R_ZERO: begin
                                regdata_hh = 8'h00;
                        end
                `OR1200_M2R_BYTE3: begin
                                regdata_hh = memdata[31:24];
                        end
                `OR1200_M2R_EXTB0: begin
                                regdata_hh = {8{memdata[7]}};
                        end
                `OR1200_M2R_EXTB1: begin
                                regdata_hh = {8{memdata[15]}};
                        end
                `OR1200_M2R_EXTB2: begin
                                regdata_hh = {8{memdata[23]}};
                        end
`ifdef OR1200_CASE_DEFAULT
                `OR1200_M2R_EXTB3: begin
`else
                `OR1200_M2R_EXTB3: begin
`endif
                                regdata_hh = {8{memdata[31]}};
                        end
        endcase
end
 
`else
 
//
// Straightforward implementation of mem2reg
//
 
reg     [width-1:0]              regdata;
reg     [width-1:0]              aligned;
 
//
// Alignment
//
always @(addr or memdata) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
        case(addr) // synopsys parallel_case infer_mux
`else
        case(addr) // synopsys parallel_case
`endif
                2'b00:
                        aligned = memdata;
                2'b01:
                        aligned = {memdata[23:0], 8'b0};
                2'b10:
                        aligned = {memdata[15:0], 16'b0};
                2'b11:
                        aligned = {memdata[7:0], 24'b0};
        endcase
end
 
//
// Bytes
//
always @(lsu_op or aligned) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
        case(lsu_op) // synopsys parallel_case infer_mux
`else
        case(lsu_op) // synopsys parallel_case
`endif
                `OR1200_LSUOP_LBZ: begin
                                regdata[7:0] = aligned[31:24];
                                regdata[31:8] = 24'b0;
                        end
                `OR1200_LSUOP_LBS: begin
                                regdata[7:0] = aligned[31:24];
                                regdata[31:8] = {24{aligned[31]}};
                        end
                `OR1200_LSUOP_LHZ: begin
                                regdata[15:0] = aligned[31:16];
                                regdata[31:16] = 16'b0;
                        end
                `OR1200_LSUOP_LHS: begin
                                regdata[15:0] = aligned[31:16];
                                regdata[31:16] = {16{aligned[31]}};
                        end
                default:
                                regdata = aligned;
        endcase
end
 
`endif
 
endmodule

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Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [or1200/] [rtl/] [verilog/] [or1200_mem2reg.v] - Blame information for rev 12

Line No.	Rev	Author	Line
1	12	xianfeng	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's mem2reg alignment ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Two versions of Memory to register data alignment. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: or1200_mem2reg.v,v $`
47			`// Revision 1.5 2002/09/03 22:28:21 lampret`
48			`// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.`
49			`//`
50			`// Revision 1.4 2002/03/29 15:16:56 lampret`
51			`// Some of the warnings fixed.`
52			`//`
53			`// Revision 1.3 2002/03/28 19:14:10 lampret`
54			`// Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2`
55			`//`
56			`// Revision 1.2 2002/01/14 06:18:22 lampret`
57			`// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.`
58			`//`
59			`// Revision 1.1 2002/01/03 08:16:15 lampret`
60			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
61			`//`
62			`// Revision 1.9 2001/10/21 17:57:16 lampret`
63			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
64			`//`
65			`// Revision 1.8 2001/10/19 23:28:46 lampret`
66			`// Fixed some synthesis warnings. Configured with caches and MMUs.`
67			`//`
68			`// Revision 1.7 2001/10/14 13:12:09 lampret`
69			`// MP3 version.`
70			`//`
71			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
72			`// no message`
73			`//`
74			`// Revision 1.2 2001/08/09 13:39:33 lampret`
75			`// Major clean-up.`
76			`//`
77			`// Revision 1.1 2001/07/20 00:46:03 lampret`
78			`// Development version of RTL. Libraries are missing.`
79			`//`
80			`//`
81
82			`// synopsys translate_off`
83			`include "timescale.v"
84			`// synopsys translate_on`
85			`include "or1200_defines.v"
86
87			`module or1200_mem2reg(addr, lsu_op, memdata, regdata);`
88
89			parameter width = `OR1200_OPERAND_WIDTH;
90
91			`//`
92			`// I/O`
93			`//`
94			`input [1:0] addr;`
95			input [`OR1200_LSUOP_WIDTH-1:0] lsu_op;
96			`input [width-1:0] memdata;`
97			`output [width-1:0] regdata;`
98
99
100			`//`
101			`// In the past faster implementation of mem2reg (today probably slower)`
102			`//`
103			`ifdef OR1200_IMPL_MEM2REG2
104
105			`define OR1200_M2R_BYTE0 4'b0000
106			`define OR1200_M2R_BYTE1 4'b0001
107			`define OR1200_M2R_BYTE2 4'b0010
108			`define OR1200_M2R_BYTE3 4'b0011
109			`define OR1200_M2R_EXTB0 4'b0100
110			`define OR1200_M2R_EXTB1 4'b0101
111			`define OR1200_M2R_EXTB2 4'b0110
112			`define OR1200_M2R_EXTB3 4'b0111
113			`define OR1200_M2R_ZERO 4'b0000
114
115			`reg [7:0] regdata_hh;`
116			`reg [7:0] regdata_hl;`
117			`reg [7:0] regdata_lh;`
118			`reg [7:0] regdata_ll;`
119			`reg [width-1:0] aligned;`
120			`reg [3:0] sel_byte0, sel_byte1,`
121			`sel_byte2, sel_byte3;`
122
123			`assign regdata = {regdata_hh, regdata_hl, regdata_lh, regdata_ll};`
124
125			`//`
126			`// Byte select 0`
127			`//`
128			`always @(addr or lsu_op) begin`
129			`casex({lsu_op[2:0], addr}) // synopsys parallel_case`
130			`{3'b01x, 2'b00}: // lbz/lbs 0`
131			sel_byte0 = `OR1200_M2R_BYTE3; // take byte 3
132			`{3'b01x, 2'b01}, // lbz/lbs 1`
133			`{3'b10x, 2'b00}: // lhz/lhs 0`
134			sel_byte0 = `OR1200_M2R_BYTE2; // take byte 2
135			`{3'b01x, 2'b10}: // lbz/lbs 2`
136			sel_byte0 = `OR1200_M2R_BYTE1; // take byte 1
137			`default: // all other cases`
138			sel_byte0 = `OR1200_M2R_BYTE0; // take byte 0
139			`endcase`
140			`end`
141
142			`//`
143			`// Byte select 1`
144			`//`
145			`always @(addr or lsu_op) begin`
146			`casex({lsu_op[2:0], addr}) // synopsys parallel_case`
147			`{3'b010, 2'bxx}: // lbz`
148			sel_byte1 = `OR1200_M2R_ZERO; // zero extend
149			`{3'b011, 2'b00}: // lbs 0`
150			sel_byte1 = `OR1200_M2R_EXTB3; // sign extend from byte 3
151			`{3'b011, 2'b01}: // lbs 1`
152			sel_byte1 = `OR1200_M2R_EXTB2; // sign extend from byte 2
153			`{3'b011, 2'b10}: // lbs 2`
154			sel_byte1 = `OR1200_M2R_EXTB1; // sign extend from byte 1
155			`{3'b011, 2'b11}: // lbs 3`
156			sel_byte1 = `OR1200_M2R_EXTB0; // sign extend from byte 0
157			`{3'b10x, 2'b00}: // lhz/lhs 0`
158			sel_byte1 = `OR1200_M2R_BYTE3; // take byte 3
159			`default: // all other cases`
160			sel_byte1 = `OR1200_M2R_BYTE1; // take byte 1
161			`endcase`
162			`end`
163
164			`//`
165			`// Byte select 2`
166			`//`
167			`always @(addr or lsu_op) begin`
168			`casex({lsu_op[2:0], addr}) // synopsys parallel_case`
169			`{3'b010, 2'bxx}, // lbz`
170			`{3'b100, 2'bxx}: // lhz`
171			sel_byte2 = `OR1200_M2R_ZERO; // zero extend
172			`{3'b011, 2'b00}, // lbs 0`
173			`{3'b101, 2'b00}: // lhs 0`
174			sel_byte2 = `OR1200_M2R_EXTB3; // sign extend from byte 3
175			`{3'b011, 2'b01}: // lbs 1`
176			sel_byte2 = `OR1200_M2R_EXTB2; // sign extend from byte 2
177			`{3'b011, 2'b10}, // lbs 2`
178			`{3'b101, 2'b10}: // lhs 0`
179			sel_byte2 = `OR1200_M2R_EXTB1; // sign extend from byte 1
180			`{3'b011, 2'b11}: // lbs 3`
181			sel_byte2 = `OR1200_M2R_EXTB0; // sign extend from byte 0
182			`default: // all other cases`
183			sel_byte2 = `OR1200_M2R_BYTE2; // take byte 2
184			`endcase`
185			`end`
186
187			`//`
188			`// Byte select 3`
189			`//`
190			`always @(addr or lsu_op) begin`
191			`casex({lsu_op[2:0], addr}) // synopsys parallel_case`
192			`{3'b010, 2'bxx}, // lbz`
193			`{3'b100, 2'bxx}: // lhz`
194			sel_byte3 = `OR1200_M2R_ZERO; // zero extend
195			`{3'b011, 2'b00}, // lbs 0`
196			`{3'b101, 2'b00}: // lhs 0`
197			sel_byte3 = `OR1200_M2R_EXTB3; // sign extend from byte 3
198			`{3'b011, 2'b01}: // lbs 1`
199			sel_byte3 = `OR1200_M2R_EXTB2; // sign extend from byte 2
200			`{3'b011, 2'b10}, // lbs 2`
201			`{3'b101, 2'b10}: // lhs 0`
202			sel_byte3 = `OR1200_M2R_EXTB1; // sign extend from byte 1
203			`{3'b011, 2'b11}: // lbs 3`
204			sel_byte3 = `OR1200_M2R_EXTB0; // sign extend from byte 0
205			`default: // all other cases`
206			sel_byte3 = `OR1200_M2R_BYTE3; // take byte 3
207			`endcase`
208			`end`
209
210			`//`
211			`// Byte 0`
212			`//`
213			`always @(sel_byte0 or memdata) begin`
214			`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
215			`ifdef OR1200_CASE_DEFAULT
216			`case(sel_byte0) // synopsys parallel_case infer_mux`
217			`else
218			`case(sel_byte0) // synopsys full_case parallel_case infer_mux`
219			`endif
220			`else
221			`ifdef OR1200_CASE_DEFAULT
222			`case(sel_byte0) // synopsys parallel_case`
223			`else
224			`case(sel_byte0) // synopsys full_case parallel_case`
225			`endif
226			`endif
227			`OR1200_M2R_BYTE0: begin
228			`regdata_ll = memdata[7:0];`
229			`end`
230			`OR1200_M2R_BYTE1: begin
231			`regdata_ll = memdata[15:8];`
232			`end`
233			`OR1200_M2R_BYTE2: begin
234			`regdata_ll = memdata[23:16];`
235			`end`
236			`ifdef OR1200_CASE_DEFAULT
237			`default: begin`
238			`else
239			`OR1200_M2R_BYTE3: begin
240			`endif
241			`regdata_ll = memdata[31:24];`
242			`end`
243			`endcase`
244			`end`
245
246			`//`
247			`// Byte 1`
248			`//`
249			`always @(sel_byte1 or memdata) begin`
250			`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
251			`ifdef OR1200_CASE_DEFAULT
252			`case(sel_byte1) // synopsys parallel_case infer_mux`
253			`else
254			`case(sel_byte1) // synopsys full_case parallel_case infer_mux`
255			`endif
256			`else
257			`ifdef OR1200_CASE_DEFAULT
258			`case(sel_byte1) // synopsys parallel_case`
259			`else
260			`case(sel_byte1) // synopsys full_case parallel_case`
261			`endif
262			`endif
263			`OR1200_M2R_ZERO: begin
264			`regdata_lh = 8'h00;`
265			`end`
266			`OR1200_M2R_BYTE1: begin
267			`regdata_lh = memdata[15:8];`
268			`end`
269			`OR1200_M2R_BYTE3: begin
270			`regdata_lh = memdata[31:24];`
271			`end`
272			`OR1200_M2R_EXTB0: begin
273			`regdata_lh = {8{memdata[7]}};`
274			`end`
275			`OR1200_M2R_EXTB1: begin
276			`regdata_lh = {8{memdata[15]}};`
277			`end`
278			`OR1200_M2R_EXTB2: begin
279			`regdata_lh = {8{memdata[23]}};`
280			`end`
281			`ifdef OR1200_CASE_DEFAULT
282			`default: begin`
283			`else
284			`OR1200_M2R_EXTB3: begin
285			`endif
286			`regdata_lh = {8{memdata[31]}};`
287			`end`
288			`endcase`
289			`end`
290
291			`//`
292			`// Byte 2`
293			`//`
294			`always @(sel_byte2 or memdata) begin`
295			`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
296			`ifdef OR1200_CASE_DEFAULT
297			`case(sel_byte2) // synopsys parallel_case infer_mux`
298			`else
299			`case(sel_byte2) // synopsys full_case parallel_case infer_mux`
300			`endif
301			`else
302			`ifdef OR1200_CASE_DEFAULT
303			`case(sel_byte2) // synopsys parallel_case`
304			`else
305			`case(sel_byte2) // synopsys full_case parallel_case`
306			`endif
307			`endif
308			`OR1200_M2R_ZERO: begin
309			`regdata_hl = 8'h00;`
310			`end`
311			`OR1200_M2R_BYTE2: begin
312			`regdata_hl = memdata[23:16];`
313			`end`
314			`OR1200_M2R_EXTB0: begin
315			`regdata_hl = {8{memdata[7]}};`
316			`end`
317			`OR1200_M2R_EXTB1: begin
318			`regdata_hl = {8{memdata[15]}};`
319			`end`
320			`OR1200_M2R_EXTB2: begin
321			`regdata_hl = {8{memdata[23]}};`
322			`end`
323			`ifdef OR1200_CASE_DEFAULT
324			`default: begin`
325			`else
326			`OR1200_M2R_EXTB3: begin
327			`endif
328			`regdata_hl = {8{memdata[31]}};`
329			`end`
330			`endcase`
331			`end`
332
333			`//`
334			`// Byte 3`
335			`//`
336			`always @(sel_byte3 or memdata) begin`
337			`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
338			`ifdef OR1200_CASE_DEFAULT
339			`case(sel_byte3) // synopsys parallel_case infer_mux`
340			`else
341			`case(sel_byte3) // synopsys full_case parallel_case infer_mux`
342			`endif
343			`else
344			`ifdef OR1200_CASE_DEFAULT
345			`case(sel_byte3) // synopsys parallel_case`
346			`else
347			`case(sel_byte3) // synopsys full_case parallel_case`
348			`endif
349			`endif
350			`OR1200_M2R_ZERO: begin
351			`regdata_hh = 8'h00;`
352			`end`
353			`OR1200_M2R_BYTE3: begin
354			`regdata_hh = memdata[31:24];`
355			`end`
356			`OR1200_M2R_EXTB0: begin
357			`regdata_hh = {8{memdata[7]}};`
358			`end`
359			`OR1200_M2R_EXTB1: begin
360			`regdata_hh = {8{memdata[15]}};`
361			`end`
362			`OR1200_M2R_EXTB2: begin
363			`regdata_hh = {8{memdata[23]}};`
364			`end`
365			`ifdef OR1200_CASE_DEFAULT
366			`OR1200_M2R_EXTB3: begin
367			`else
368			`OR1200_M2R_EXTB3: begin
369			`endif
370			`regdata_hh = {8{memdata[31]}};`
371			`end`
372			`endcase`
373			`end`
374
375			`else
376
377			`//`
378			`// Straightforward implementation of mem2reg`
379			`//`
380
381			`reg [width-1:0] regdata;`
382			`reg [width-1:0] aligned;`
383
384			`//`
385			`// Alignment`
386			`//`
387			`always @(addr or memdata) begin`
388			`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
389			`case(addr) // synopsys parallel_case infer_mux`
390			`else
391			`case(addr) // synopsys parallel_case`
392			`endif
393			`2'b00:`
394			`aligned = memdata;`
395			`2'b01:`
396			`aligned = {memdata[23:0], 8'b0};`
397			`2'b10:`
398			`aligned = {memdata[15:0], 16'b0};`
399			`2'b11:`
400			`aligned = {memdata[7:0], 24'b0};`
401			`endcase`
402			`end`
403
404			`//`
405			`// Bytes`
406			`//`
407			`always @(lsu_op or aligned) begin`
408			`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
409			`case(lsu_op) // synopsys parallel_case infer_mux`
410			`else
411			`case(lsu_op) // synopsys parallel_case`
412			`endif
413			`OR1200_LSUOP_LBZ: begin
414			`regdata[7:0] = aligned[31:24];`
415			`regdata[31:8] = 24'b0;`
416			`end`
417			`OR1200_LSUOP_LBS: begin
418			`regdata[7:0] = aligned[31:24];`
419			`regdata[31:8] = {24{aligned[31]}};`
420			`end`
421			`OR1200_LSUOP_LHZ: begin
422			`regdata[15:0] = aligned[31:16];`
423			`regdata[31:16] = 16'b0;`
424			`end`
425			`OR1200_LSUOP_LHS: begin
426			`regdata[15:0] = aligned[31:16];`
427			`regdata[31:16] = {16{aligned[31]}};`
428			`end`
429			`default:`
430			`regdata = aligned;`
431			`endcase`
432			`end`
433
434			`endif
435
436			`endmodule`