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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [or1200/] [rtl/] [verilog/] [or1200_operandmuxes.v] - Blame information for rev 12

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's register file read operands mux                    ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Mux for two register file read operands.                    ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_operandmuxes.v,v $
// Revision 1.2  2002/03/29 15:16:56  lampret
// Some of the warnings fixed.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.9  2001/11/12 01:45:40  lampret
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
//
// Revision 1.8  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:05  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_operandmuxes(
        // Clock and reset
        clk, rst,
 
        // Internal i/f
        id_freeze, ex_freeze, rf_dataa, rf_datab, ex_forw, wb_forw,
        simm, sel_a, sel_b, operand_a, operand_b, muxed_b
);
 
parameter width = `OR1200_OPERAND_WIDTH;
 
//
// I/O
//
input                           clk;
input                           rst;
input                           id_freeze;
input                           ex_freeze;
input   [width-1:0]              rf_dataa;
input   [width-1:0]              rf_datab;
input   [width-1:0]              ex_forw;
input   [width-1:0]              wb_forw;
input   [width-1:0]              simm;
input   [`OR1200_SEL_WIDTH-1:0]  sel_a;
input   [`OR1200_SEL_WIDTH-1:0]  sel_b;
output  [width-1:0]              operand_a;
output  [width-1:0]              operand_b;
output  [width-1:0]              muxed_b;
 
//
// Internal wires and regs
//
reg     [width-1:0]              operand_a;
reg     [width-1:0]              operand_b;
reg     [width-1:0]              muxed_a;
reg     [width-1:0]              muxed_b;
reg                             saved_a;
reg                             saved_b;
 
//
// Operand A register
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                operand_a <= #1 32'd0;
                saved_a <= #1 1'b0;
        end else if (!ex_freeze && id_freeze && !saved_a) begin
                operand_a <= #1 muxed_a;
                saved_a <= #1 1'b1;
        end else if (!ex_freeze && !saved_a) begin
                operand_a <= #1 muxed_a;
        end else if (!ex_freeze && !id_freeze)
                saved_a <= #1 1'b0;
end
 
//
// Operand B register
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                operand_b <= #1 32'd0;
                saved_b <= #1 1'b0;
        end else if (!ex_freeze && id_freeze && !saved_b) begin
                operand_b <= #1 muxed_b;
                saved_b <= #1 1'b1;
        end else if (!ex_freeze && !saved_b) begin
                operand_b <= #1 muxed_b;
        end else if (!ex_freeze && !id_freeze)
                saved_b <= #1 1'b0;
end
 
//
// Forwarding logic for operand A register
//
always @(ex_forw or wb_forw or rf_dataa or sel_a) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
        casex (sel_a)   // synopsys parallel_case infer_mux
`else
        casex (sel_a)   // synopsys parallel_case
`endif
                `OR1200_SEL_EX_FORW:
                        muxed_a = ex_forw;
                `OR1200_SEL_WB_FORW:
                        muxed_a = wb_forw;
                default:
                        muxed_a = rf_dataa;
        endcase
end
 
//
// Forwarding logic for operand B register
//
always @(simm or ex_forw or wb_forw or rf_datab or sel_b) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
        casex (sel_b)   // synopsys parallel_case infer_mux
`else
        casex (sel_b)   // synopsys parallel_case
`endif
                `OR1200_SEL_IMM:
                        muxed_b = simm;
                `OR1200_SEL_EX_FORW:
                        muxed_b = ex_forw;
                `OR1200_SEL_WB_FORW:
                        muxed_b = wb_forw;
                default:
                        muxed_b = rf_datab;
        endcase
end
 
endmodule

Line No.	Rev	Author	Line
1	12	xianfeng	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's register file read operands mux ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Mux for two register file read operands. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: or1200_operandmuxes.v,v $`
47			`// Revision 1.2 2002/03/29 15:16:56 lampret`
48			`// Some of the warnings fixed.`
49			`//`
50			`// Revision 1.1 2002/01/03 08:16:15 lampret`
51			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
52			`//`
53			`// Revision 1.9 2001/11/12 01:45:40 lampret`
54			`// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.`
55			`//`
56			`// Revision 1.8 2001/10/21 17:57:16 lampret`
57			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
58			`//`
59			`// Revision 1.7 2001/10/14 13:12:09 lampret`
60			`// MP3 version.`
61			`//`
62			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
63			`// no message`
64			`//`
65			`// Revision 1.2 2001/08/09 13:39:33 lampret`
66			`// Major clean-up.`
67			`//`
68			`// Revision 1.1 2001/07/20 00:46:05 lampret`
69			`// Development version of RTL. Libraries are missing.`
70			`//`
71			`//`
72
73			`// synopsys translate_off`
74			`include "timescale.v"
75			`// synopsys translate_on`
76			`include "or1200_defines.v"
77
78			`module or1200_operandmuxes(`
79			`// Clock and reset`
80			`clk, rst,`
81
82			`// Internal i/f`
83			`id_freeze, ex_freeze, rf_dataa, rf_datab, ex_forw, wb_forw,`
84			`simm, sel_a, sel_b, operand_a, operand_b, muxed_b`
85			`);`
86
87			parameter width = `OR1200_OPERAND_WIDTH;
88
89			`//`
90			`// I/O`
91			`//`
92			`input clk;`
93			`input rst;`
94			`input id_freeze;`
95			`input ex_freeze;`
96			`input [width-1:0] rf_dataa;`
97			`input [width-1:0] rf_datab;`
98			`input [width-1:0] ex_forw;`
99			`input [width-1:0] wb_forw;`
100			`input [width-1:0] simm;`
101			input [`OR1200_SEL_WIDTH-1:0] sel_a;
102			input [`OR1200_SEL_WIDTH-1:0] sel_b;
103			`output [width-1:0] operand_a;`
104			`output [width-1:0] operand_b;`
105			`output [width-1:0] muxed_b;`
106
107			`//`
108			`// Internal wires and regs`
109			`//`
110			`reg [width-1:0] operand_a;`
111			`reg [width-1:0] operand_b;`
112			`reg [width-1:0] muxed_a;`
113			`reg [width-1:0] muxed_b;`
114			`reg saved_a;`
115			`reg saved_b;`
116
117			`//`
118			`// Operand A register`
119			`//`
120			`always @(posedge clk or posedge rst) begin`
121			`if (rst) begin`
122			`operand_a <= #1 32'd0;`
123			`saved_a <= #1 1'b0;`
124			`end else if (!ex_freeze && id_freeze && !saved_a) begin`
125			`operand_a <= #1 muxed_a;`
126			`saved_a <= #1 1'b1;`
127			`end else if (!ex_freeze && !saved_a) begin`
128			`operand_a <= #1 muxed_a;`
129			`end else if (!ex_freeze && !id_freeze)`
130			`saved_a <= #1 1'b0;`
131			`end`
132
133			`//`
134			`// Operand B register`
135			`//`
136			`always @(posedge clk or posedge rst) begin`
137			`if (rst) begin`
138			`operand_b <= #1 32'd0;`
139			`saved_b <= #1 1'b0;`
140			`end else if (!ex_freeze && id_freeze && !saved_b) begin`
141			`operand_b <= #1 muxed_b;`
142			`saved_b <= #1 1'b1;`
143			`end else if (!ex_freeze && !saved_b) begin`
144			`operand_b <= #1 muxed_b;`
145			`end else if (!ex_freeze && !id_freeze)`
146			`saved_b <= #1 1'b0;`
147			`end`
148
149			`//`
150			`// Forwarding logic for operand A register`
151			`//`
152			`always @(ex_forw or wb_forw or rf_dataa or sel_a) begin`
153			`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
154			`casex (sel_a) // synopsys parallel_case infer_mux`
155			`else
156			`casex (sel_a) // synopsys parallel_case`
157			`endif
158			`OR1200_SEL_EX_FORW:
159			`muxed_a = ex_forw;`
160			`OR1200_SEL_WB_FORW:
161			`muxed_a = wb_forw;`
162			`default:`
163			`muxed_a = rf_dataa;`
164			`endcase`
165			`end`
166
167			`//`
168			`// Forwarding logic for operand B register`
169			`//`
170			`always @(simm or ex_forw or wb_forw or rf_datab or sel_b) begin`
171			`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
172			`casex (sel_b) // synopsys parallel_case infer_mux`
173			`else
174			`casex (sel_b) // synopsys parallel_case`
175			`endif
176			`OR1200_SEL_IMM:
177			`muxed_b = simm;`
178			`OR1200_SEL_EX_FORW:
179			`muxed_b = ex_forw;`
180			`OR1200_SEL_WB_FORW:
181			`muxed_b = wb_forw;`
182			`default:`
183			`muxed_b = rf_datab;`
184			`endcase`
185			`end`
186
187			`endmodule`

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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [or1200/] [rtl/] [verilog/] [or1200_operandmuxes.v] - Blame information for rev 12