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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [or1200/] [rtl/] [verilog/] [or1200_pic.v] - Blame information for rev 12

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Programmable Interrupt Controller                  ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  PIC according to OR1K architectural specification.          ////
////                                                              ////
////  To Do:                                                      ////
////   None                                                       ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_pic.v,v $
// Revision 1.4  2004/06/08 18:17:36  lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.3  2002/03/29 15:16:56  lampret
// Some of the warnings fixed.
//
// Revision 1.2  2002/01/18 07:56:00  lampret
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7  2001/10/14 13:12:10  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:21  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_pic(
        // RISC Internal Interface
        clk, rst, spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
        pic_wakeup, intr,
 
        // PIC Interface
        pic_int
);
 
//
// RISC Internal Interface
//
input           clk;            // Clock
input           rst;            // Reset
input           spr_cs;         // SPR CS
input           spr_write;      // SPR Write
input   [31:0]   spr_addr;       // SPR Address
input   [31:0]   spr_dat_i;      // SPR Write Data
output  [31:0]   spr_dat_o;      // SPR Read Data
output          pic_wakeup;     // Wakeup to the PM
output          intr;           // interrupt
                                // exception request
 
//
// PIC Interface
//
input   [`OR1200_PIC_INTS-1:0]   pic_int;// Interrupt inputs
 
`ifdef OR1200_PIC_IMPLEMENTED
 
//
// PIC Mask Register bits (or no register)
//
`ifdef OR1200_PIC_PICMR
reg     [`OR1200_PIC_INTS-1:2]  picmr;  // PICMR bits
`else
wire    [`OR1200_PIC_INTS-1:2]  picmr;  // No PICMR register
`endif
 
//
// PIC Status Register bits (or no register)
//
`ifdef OR1200_PIC_PICSR
reg     [`OR1200_PIC_INTS-1:0]   picsr;  // PICSR bits
`else
wire    [`OR1200_PIC_INTS-1:0]   picsr;  // No PICSR register
`endif
 
//
// Internal wires & regs
//
wire            picmr_sel;      // PICMR select
wire            picsr_sel;      // PICSR select
wire    [`OR1200_PIC_INTS-1:0] um_ints;// Unmasked interrupts
reg     [31:0]   spr_dat_o;      // SPR data out
 
//
// PIC registers address decoder
//
assign picmr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICMR)) ? 1'b1 : 1'b0;
assign picsr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICSR)) ? 1'b1 : 1'b0;
 
//
// Write to PICMR
//
`ifdef OR1200_PIC_PICMR
always @(posedge clk or posedge rst)
        if (rst)
                picmr <= {1'b1, {`OR1200_PIC_INTS-3{1'b0}}};
        else if (picmr_sel && spr_write) begin
                picmr <= #1 spr_dat_i[`OR1200_PIC_INTS-1:2];
        end
`else
assign picmr = (`OR1200_PIC_INTS)'b1;
`endif
 
//
// Write to PICSR, both CPU and external ints
//
`ifdef OR1200_PIC_PICSR
always @(posedge clk or posedge rst)
        if (rst)
                picsr <= {`OR1200_PIC_INTS{1'b0}};
        else if (picsr_sel && spr_write) begin
                picsr <= #1 spr_dat_i[`OR1200_PIC_INTS-1:0] | um_ints;
        end else
                picsr <= #1 picsr | um_ints;
`else
assign picsr = pic_int;
`endif
 
//
// Read PIC registers
//
always @(spr_addr or picmr or picsr)
        case (spr_addr[`OR1200_PICOFS_BITS])    // synopsys parallel_case
`ifdef OR1200_PIC_READREGS
                `OR1200_PIC_OFS_PICMR: begin
                                        spr_dat_o[`OR1200_PIC_INTS-1:0] = {picmr, 2'b0};
`ifdef OR1200_PIC_UNUSED_ZERO
                                        spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}};
`endif
                                end
`endif
                default: begin
                                spr_dat_o[`OR1200_PIC_INTS-1:0] = picsr;
`ifdef OR1200_PIC_UNUSED_ZERO
                                spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}};
`endif
                        end
        endcase
 
//
// Unmasked interrupts
//
assign um_ints = pic_int & {picmr, 2'b11};
 
//
// Generate intr
//
assign intr = |um_ints;
 
//
// Assert pic_wakeup when intr is asserted
//
assign pic_wakeup = intr;
 
`else
 
//
// When PIC is not implemented, drive all outputs as would when PIC is disabled
//
assign intr = pic_int[1] | pic_int[0];
assign pic_wakeup= intr;
 
//
// Read PIC registers
//
`ifdef OR1200_PIC_READREGS
assign spr_dat_o[`OR1200_PIC_INTS-1:0] = `OR1200_PIC_INTS'b0;
`ifdef OR1200_PIC_UNUSED_ZERO
assign spr_dat_o[31:`OR1200_PIC_INTS] = 32-`OR1200_PIC_INTS'b0;
`endif
`endif
 
`endif
 
endmodule

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Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [or1200/] [rtl/] [verilog/] [or1200_pic.v] - Blame information for rev 12

Line No.	Rev	Author	Line
1	12	xianfeng	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Programmable Interrupt Controller ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// PIC according to OR1K architectural specification. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// None ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: or1200_pic.v,v $`
47			`// Revision 1.4 2004/06/08 18:17:36 lampret`
48			`// Non-functional changes. Coding style fixes.`
49			`//`
50			`// Revision 1.3 2002/03/29 15:16:56 lampret`
51			`// Some of the warnings fixed.`
52			`//`
53			`// Revision 1.2 2002/01/18 07:56:00 lampret`
54			`// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.`
55			`//`
56			`// Revision 1.1 2002/01/03 08:16:15 lampret`
57			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
58			`//`
59			`// Revision 1.8 2001/10/21 17:57:16 lampret`
60			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
61			`//`
62			`// Revision 1.7 2001/10/14 13:12:10 lampret`
63			`// MP3 version.`
64			`//`
65			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
66			`// no message`
67			`//`
68			`// Revision 1.2 2001/08/09 13:39:33 lampret`
69			`// Major clean-up.`
70			`//`
71			`// Revision 1.1 2001/07/20 00:46:21 lampret`
72			`// Development version of RTL. Libraries are missing.`
73			`//`
74			`//`
75
76			`// synopsys translate_off`
77			`include "timescale.v"
78			`// synopsys translate_on`
79			`include "or1200_defines.v"
80
81			`module or1200_pic(`
82			`// RISC Internal Interface`
83			`clk, rst, spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,`
84			`pic_wakeup, intr,`
85
86			`// PIC Interface`
87			`pic_int`
88			`);`
89
90			`//`
91			`// RISC Internal Interface`
92			`//`
93			`input clk; // Clock`
94			`input rst; // Reset`
95			`input spr_cs; // SPR CS`
96			`input spr_write; // SPR Write`
97			`input [31:0] spr_addr; // SPR Address`
98			`input [31:0] spr_dat_i; // SPR Write Data`
99			`output [31:0] spr_dat_o; // SPR Read Data`
100			`output pic_wakeup; // Wakeup to the PM`
101			`output intr; // interrupt`
102			`// exception request`
103
104			`//`
105			`// PIC Interface`
106			`//`
107			input [`OR1200_PIC_INTS-1:0] pic_int;// Interrupt inputs
108
109			`ifdef OR1200_PIC_IMPLEMENTED
110
111			`//`
112			`// PIC Mask Register bits (or no register)`
113			`//`
114			`ifdef OR1200_PIC_PICMR
115			reg [`OR1200_PIC_INTS-1:2] picmr; // PICMR bits
116			`else
117			wire [`OR1200_PIC_INTS-1:2] picmr; // No PICMR register
118			`endif
119
120			`//`
121			`// PIC Status Register bits (or no register)`
122			`//`
123			`ifdef OR1200_PIC_PICSR
124			reg [`OR1200_PIC_INTS-1:0] picsr; // PICSR bits
125			`else
126			wire [`OR1200_PIC_INTS-1:0] picsr; // No PICSR register
127			`endif
128
129			`//`
130			`// Internal wires & regs`
131			`//`
132			`wire picmr_sel; // PICMR select`
133			`wire picsr_sel; // PICSR select`
134			wire [`OR1200_PIC_INTS-1:0] um_ints;// Unmasked interrupts
135			`reg [31:0] spr_dat_o; // SPR data out`
136
137			`//`
138			`// PIC registers address decoder`
139			`//`
140			assign picmr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICMR)) ? 1'b1 : 1'b0;
141			assign picsr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICSR)) ? 1'b1 : 1'b0;
142
143			`//`
144			`// Write to PICMR`
145			`//`
146			`ifdef OR1200_PIC_PICMR
147			`always @(posedge clk or posedge rst)`
148			`if (rst)`
149			picmr <= {1'b1, {`OR1200_PIC_INTS-3{1'b0}}};
150			`else if (picmr_sel && spr_write) begin`
151			picmr <= #1 spr_dat_i[`OR1200_PIC_INTS-1:2];
152			`end`
153			`else
154			assign picmr = (`OR1200_PIC_INTS)'b1;
155			`endif
156
157			`//`
158			`// Write to PICSR, both CPU and external ints`
159			`//`
160			`ifdef OR1200_PIC_PICSR
161			`always @(posedge clk or posedge rst)`
162			`if (rst)`
163			picsr <= {`OR1200_PIC_INTS{1'b0}};
164			`else if (picsr_sel && spr_write) begin`
165			picsr <= #1 spr_dat_i[`OR1200_PIC_INTS-1:0] \| um_ints;
166			`end else`
167			`picsr <= #1 picsr \| um_ints;`
168			`else
169			`assign picsr = pic_int;`
170			`endif
171
172			`//`
173			`// Read PIC registers`
174			`//`
175			`always @(spr_addr or picmr or picsr)`
176			case (spr_addr[`OR1200_PICOFS_BITS]) // synopsys parallel_case
177			`ifdef OR1200_PIC_READREGS
178			`OR1200_PIC_OFS_PICMR: begin
179			spr_dat_o[`OR1200_PIC_INTS-1:0] = {picmr, 2'b0};
180			`ifdef OR1200_PIC_UNUSED_ZERO
181			spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}};
182			`endif
183			`end`
184			`endif
185			`default: begin`
186			spr_dat_o[`OR1200_PIC_INTS-1:0] = picsr;
187			`ifdef OR1200_PIC_UNUSED_ZERO
188			spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}};
189			`endif
190			`end`
191			`endcase`
192
193			`//`
194			`// Unmasked interrupts`
195			`//`
196			`assign um_ints = pic_int & {picmr, 2'b11};`
197
198			`//`
199			`// Generate intr`
200			`//`
201			`assign intr = \|um_ints;`
202
203			`//`
204			`// Assert pic_wakeup when intr is asserted`
205			`//`
206			`assign pic_wakeup = intr;`
207
208			`else
209
210			`//`
211			`// When PIC is not implemented, drive all outputs as would when PIC is disabled`
212			`//`
213			`assign intr = pic_int[1] \| pic_int[0];`
214			`assign pic_wakeup= intr;`
215
216			`//`
217			`// Read PIC registers`
218			`//`
219			`ifdef OR1200_PIC_READREGS
220			assign spr_dat_o[`OR1200_PIC_INTS-1:0] = `OR1200_PIC_INTS'b0;
221			`ifdef OR1200_PIC_UNUSED_ZERO
222			assign spr_dat_o[31:`OR1200_PIC_INTS] = 32-`OR1200_PIC_INTS'b0;
223			`endif
224			`endif
225
226			`endif
227
228			`endmodule`