OpenCores
URL https://opencores.org/ocsvn/or1k_soc_on_altera_embedded_dev_kit/or1k_soc_on_altera_embedded_dev_kit/trunk

Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [or1200/] [rtl/] [verilog/] [or1200_reg2mem.v] - Blame information for rev 12

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 12 xianfeng
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200's reg2mem aligner                                    ////
4
////                                                              ////
5
////  This file is part of the OpenRISC 1200 project              ////
6
////  http://www.opencores.org/cores/or1k/                        ////
7
////                                                              ////
8
////  Description                                                 ////
9
////  Aligns register data to memory alignment.                   ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////   - make it smaller and faster                               ////
13
////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Damjan Lampret, lampret@opencores.org                 ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44
// CVS Revision History
45
//
46
// $Log: or1200_reg2mem.v,v $
47
// Revision 1.2  2002/03/29 15:16:56  lampret
48
// Some of the warnings fixed.
49
//
50
// Revision 1.1  2002/01/03 08:16:15  lampret
51
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
52
//
53
// Revision 1.9  2001/10/21 17:57:16  lampret
54
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
55
//
56
// Revision 1.8  2001/10/19 23:28:46  lampret
57
// Fixed some synthesis warnings. Configured with caches and MMUs.
58
//
59
// Revision 1.7  2001/10/14 13:12:10  lampret
60
// MP3 version.
61
//
62
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
63
// no message
64
//
65
// Revision 1.2  2001/08/09 13:39:33  lampret
66
// Major clean-up.
67
//
68
// Revision 1.1  2001/07/20 00:46:21  lampret
69
// Development version of RTL. Libraries are missing.
70
//
71
//
72
 
73
// synopsys translate_off
74
`include "timescale.v"
75
// synopsys translate_on
76
`include "or1200_defines.v"
77
 
78
module or1200_reg2mem(addr, lsu_op, regdata, memdata);
79
 
80
parameter width = `OR1200_OPERAND_WIDTH;
81
 
82
//
83
// I/O
84
//
85
input   [1:0]                    addr;
86
input   [`OR1200_LSUOP_WIDTH-1:0]        lsu_op;
87
input   [width-1:0]              regdata;
88
output  [width-1:0]              memdata;
89
 
90
//
91
// Internal regs and wires
92
//
93
reg     [7:0]                    memdata_hh;
94
reg     [7:0]                    memdata_hl;
95
reg     [7:0]                    memdata_lh;
96
reg     [7:0]                    memdata_ll;
97
 
98
assign memdata = {memdata_hh, memdata_hl, memdata_lh, memdata_ll};
99
 
100
//
101
// Mux to memdata[31:24]
102
//
103
always @(lsu_op or addr or regdata) begin
104
        casex({lsu_op, addr[1:0]})       // synopsys parallel_case
105
                {`OR1200_LSUOP_SB, 2'b00} : memdata_hh = regdata[7:0];
106
                {`OR1200_LSUOP_SH, 2'b00} : memdata_hh = regdata[15:8];
107
                default : memdata_hh = regdata[31:24];
108
        endcase
109
end
110
 
111
//
112
// Mux to memdata[23:16]
113
//
114
always @(lsu_op or addr or regdata) begin
115
        casex({lsu_op, addr[1:0]})       // synopsys parallel_case
116
                {`OR1200_LSUOP_SW, 2'b00} : memdata_hl = regdata[23:16];
117
                default : memdata_hl = regdata[7:0];
118
        endcase
119
end
120
 
121
//
122
// Mux to memdata[15:8]
123
//
124
always @(lsu_op or addr or regdata) begin
125
        casex({lsu_op, addr[1:0]})       // synopsys parallel_case
126
                {`OR1200_LSUOP_SB, 2'b10} : memdata_lh = regdata[7:0];
127
                default : memdata_lh = regdata[15:8];
128
        endcase
129
end
130
 
131
//
132
// Mux to memdata[7:0]
133
//
134
always @(regdata)
135
        memdata_ll = regdata[7:0];
136
 
137
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.