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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [or1200/] [rtl/] [verilog/] [or1200_spram_1024x32_bw.v] - Blame information for rev 12

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Single-Port Synchronous RAM with byte write signals ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common single-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  single-port synchronous RAM.                                ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Single-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage Single-Port Sync RAM                               ////
////  - Virtual Silicon Single-Port Sync RAM                      ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB16                                      ////
////  - Xilinx Virtex RAMB4                                       ////
////                                                              ////
////  To Do:                                                      ////
////   - xilinx rams need external tri-state logic                ////
////   - fix avant! two-port ram                                  ////
////   - add additional RAMs                                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_spram_1024x32_bw.v,v $
// Revision 1.4  2005/10/19 11:37:56  jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
// Revision 1.3  2004/06/08 18:15:32  lampret
// Changed behavior of the simulation generic models
//
// Revision 1.2  2003/10/17 07:59:44  markom
// mbist signals updated according to newest convention
//
// Revision 1.1  2003/08/27 08:38:36  simons
// Added support for rams with byte write access.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_spram_1024x32_bw(
`ifdef OR1200_BIST
        // RAM BIST
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
        // Generic synchronous single-port RAM interface
        clk, rst, ce, we, oe, addr, di, doq
);
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input                   mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control
output                  mbist_so_o;
`endif
 
//
// Generic synchronous single-port RAM interface
//
input                   clk;    // Clock
input                   rst;    // Reset
input                   ce;     // Chip enable input
input   [3:0]           we;     // Write enable input
input                   oe;     // Output enable input
input   [9:0]           addr;   // address bus inputs
input   [31:0]          di;     // input data bus
output  [31:0]          doq;     // output data bus
 
//
// Internal wires and registers
//
 
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
 
 
`ifdef OR1200_ARTISAN_SSP
 
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_1024x32_bw artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_1024x32_bw_bist artisan_ssp(
`else
art_hssp_1024x32_bw artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i),
        .mbist_so_o(mbist_so_o),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CLK(clk),
        .CEN(~ce),
        .WEN(~we),
        .A(addr),
        .D(di),
        .OEN(~oe),
        .Q(doq)
);
 
`else
 
`ifdef OR1200_AVANT_ATP
 
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
        .web(~we),
        .reb(),
        .oeb(~oe),
        .rcsb(),
        .wcsb(),
        .ra(addr),
        .wa(addr),
        .di(di),
        .doq(doq)
);
 
`else
 
`ifdef OR1200_VIRAGE_SSP
 
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
        .clk(clk),
        .adr(addr),
        .d(di),
        .we(we),
        .oe(oe),
        .me(ce),
        .q(doq)
);
 
`else
 
`ifdef OR1200_VIRTUALSILICON_SSP
 
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef OR1200_BIST
wire mbist_si_i_ram_0;
wire mbist_si_i_ram_1;
wire mbist_si_i_ram_2;
wire mbist_si_i_ram_3;
wire mbist_so_o_ram_0;
wire mbist_so_o_ram_1;
wire mbist_so_o_ram_2;
wire mbist_so_o_ram_3;
assign mbist_si_i_ram_0 = mbist_si_i;
assign mbist_si_i_ram_1 = mbist_so_o_ram_0;
assign mbist_si_i_ram_2 = mbist_so_o_ram_1;
assign mbist_si_i_ram_3 = mbist_so_o_ram_2;
assign mbist_so_o = mbist_so_o_ram_3;
`endif
 
`ifdef UNUSED
vs_hdsp_1024x8 vs_ssp_0(
`else
`ifdef OR1200_BIST
vs_hdsp_1024x8_bist vs_ssp_0(
`else
vs_hdsp_1024x8 vs_ssp_0(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i_ram_0),
        .mbist_so_o(mbist_so_o_ram_0),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di[7:0]),
        .WEN(~we[0]),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(doq[7:0])
);
 
`ifdef UNUSED
vs_hdsp_1024x8 vs_ssp_1(
`else
`ifdef OR1200_BIST
vs_hdsp_1024x8_bist vs_ssp_1(
`else
vs_hdsp_1024x8 vs_ssp_1(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i_ram_1),
        .mbist_so_o(mbist_so_o_ram_1),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di[15:8]),
        .WEN(~we[1]),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(doq[15:8])
);
 
`ifdef UNUSED
vs_hdsp_1024x8 vs_ssp_2(
`else
`ifdef OR1200_BIST
vs_hdsp_1024x8_bist vs_ssp_2(
`else
vs_hdsp_1024x8 vs_ssp_2(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i_ram_2),
        .mbist_so_o(mbist_so_o_ram_2),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di[23:16]),
        .WEN(~we[2]),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(doq[23:16])
);
 
`ifdef UNUSED
vs_hdsp_1024x8 vs_ssp_3(
`else
`ifdef OR1200_BIST
vs_hdsp_1024x8_bist vs_ssp_3(
`else
vs_hdsp_1024x8 vs_ssp_3(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i_ram_3),
        .mbist_so_o(mbist_so_o_ram_3),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di[31:24]),
        .WEN(~we[3]),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(doq[31:24])
);
 
`else
 
`ifdef OR1200_XILINX_RAMB4
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
RAMB4_S4 ramb4_s4_0(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[3:0]),
        .EN(ce),
        .WE(we[0]),
        .DO(doq[3:0])
);
 
//
// Block 1
//
RAMB4_S4 ramb4_s4_1(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[7:4]),
        .EN(ce),
        .WE(we[0]),
        .DO(doq[7:4])
);
 
//
// Block 2
//
RAMB4_S4 ramb4_s4_2(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[11:8]),
        .EN(ce),
        .WE(we[1]),
        .DO(doq[11:8])
);
 
//
// Block 3
//
RAMB4_S4 ramb4_s4_3(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[15:12]),
        .EN(ce),
        .WE(we[1]),
        .DO(doq[15:12])
);
 
//
// Block 4
//
RAMB4_S4 ramb4_s4_4(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[19:16]),
        .EN(ce),
        .WE(we[2]),
        .DO(doq[19:16])
);
 
//
// Block 5
//
RAMB4_S4 ramb4_s4_5(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[23:20]),
        .EN(ce),
        .WE(we[2]),
        .DO(doq[23:20])
);
 
//
// Block 6
//
RAMB4_S4 ramb4_s4_6(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[27:24]),
        .EN(ce),
        .WE(we[3]),
        .DO(doq[27:24])
);
 
//
// Block 7
//
RAMB4_S4 ramb4_s4_7(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[31:28]),
        .EN(ce),
        .WE(we[3]),
        .DO(doq[31:28])
);
 
`else
 
`ifdef OR1200_XILINX_RAMB16
 
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
// Added By Nir Mor
//
 
//
// Block 0
//
RAMB16_S9 ramb16_s9_0(
        .CLK(clk),
        .SSR(rst),
        .ADDR({1'b0,addr}),
        .DI(di[7:0]),
        .DIP(1'b0),
        .EN(ce),
        .WE(we[0]),
        .DO(doq[7:0]),
        .DOP()
);
 
//
// Block 1
//
RAMB16_S9 ramb16_s9_1(
        .CLK(clk),
        .SSR(rst),
        .ADDR({1'b0,addr}),
        .DI(di[15:8]),
        .DIP(1'b0),
        .EN(ce),
        .WE(we[1]),
        .DO(doq[15:8]),
        .DOP()
);
 
//
// Block 2
//
RAMB16_S9 ramb16_s9_2(
        .CLK(clk),
        .SSR(rst),
        .ADDR({1'b0,addr}),
        .DI(di[23:16]),
        .DIP(1'b0),
        .EN(ce),
        .WE(we[2]),
        .DO(doq[23:16]),
        .DOP()
);
 
//
// Block 3
//
RAMB16_S9 ramb16_s9_3(
        .CLK(clk),
        .SSR(rst),
        .ADDR({1'b0,addr}),
        .DI(di[31:24]),
        .DIP(1'b0),
        .EN(ce),
        .WE(we[3]),
        .DO(doq[31:24]),
        .DOP()
);
 
`else
 
//
// Generic single-port synchronous RAM model
//
 
//
// Generic RAM's registers and wires
//
reg     [7:0]        mem_0 [1023:0];              // RAM content
reg     [7:0]        mem_1 [1023:0];              // RAM content
reg     [7:0]        mem_2 [1023:0];              // RAM content
reg     [7:0]        mem_3 [1023:0];              // RAM content
reg     [9:0]        addr_reg;                 // RAM address register
 
//
// Data output drivers
//
assign doq = (oe) ? {mem_3[addr_reg], mem_2[addr_reg], mem_1[addr_reg], mem_0[addr_reg]} : {32{1'b0}};
 
//
// RAM address register
//
always @(posedge clk or posedge rst)
        if (rst)
                addr_reg <= #1 10'h000;
        else if (ce)
                addr_reg <= #1 addr;
 
//
// RAM write byte 0
//
always @(posedge clk)
        if (ce && we[0])
                mem_0[addr] <= #1 di[7:0];
 
//
// RAM write byte 1
//
always @(posedge clk)
        if (ce && we[1])
                mem_1[addr] <= #1 di[15:8];
 
//
// RAM write byte 2
//
always @(posedge clk)
        if (ce && we[2])
                mem_2[addr] <= #1 di[23:16];
 
//
// RAM write byte 3
//
always @(posedge clk)
        if (ce && we[3])
                mem_3[addr] <= #1 di[31:24];
 
 
`endif  // !OR1200_XILINX_RAMB16
`endif  // !OR1200_XILINX_RAMB4
`endif  // !OR1200_VIRTUALSILICON_SSP
`endif  // !OR1200_VIRAGE_SSP
`endif  // !OR1200_AVANT_ATP
`endif  // !OR1200_ARTISAN_SSP
 
endmodule

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Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [or1200/] [rtl/] [verilog/] [or1200_spram_1024x32_bw.v] - Blame information for rev 12

Line No.	Rev	Author	Line
1	12	xianfeng	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Single-Port Synchronous RAM with byte write signals ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common single-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// single-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// - Artisan Single-Port Sync RAM ////`
20			`//// - Avant! Two-Port Sync RAM (*) ////`
21			`//// - Virage Single-Port Sync RAM ////`
22			`//// - Virtual Silicon Single-Port Sync RAM ////`
23			`//// ////`
24			`//// Supported FPGA RAMs are: ////`
25			`//// - Xilinx Virtex RAMB16 ////`
26			`//// - Xilinx Virtex RAMB4 ////`
27			`//// ////`
28			`//// To Do: ////`
29			`//// - xilinx rams need external tri-state logic ////`
30			`//// - fix avant! two-port ram ////`
31			`//// - add additional RAMs ////`
32			`//// ////`
33			`//// Author(s): ////`
34			`//// - Damjan Lampret, lampret@opencores.org ////`
35			`//// ////`
36			`//////////////////////////////////////////////////////////////////////`
37			`//// ////`
38			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
39			`//// ////`
40			`//// This source file may be used and distributed without ////`
41			`//// restriction provided that this copyright statement is not ////`
42			`//// removed from the file and that any derivative work contains ////`
43			`//// the original copyright notice and the associated disclaimer. ////`
44			`//// ////`
45			`//// This source file is free software; you can redistribute it ////`
46			`//// and/or modify it under the terms of the GNU Lesser General ////`
47			`//// Public License as published by the Free Software Foundation; ////`
48			`//// either version 2.1 of the License, or (at your option) any ////`
49			`//// later version. ////`
50			`//// ////`
51			`//// This source is distributed in the hope that it will be ////`
52			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
53			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
54			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
55			`//// details. ////`
56			`//// ////`
57			`//// You should have received a copy of the GNU Lesser General ////`
58			`//// Public License along with this source; if not, download it ////`
59			`//// from http://www.opencores.org/lgpl.shtml ////`
60			`//// ////`
61			`//////////////////////////////////////////////////////////////////////`
62			`//`
63			`// CVS Revision History`
64			`//`
65			`// $Log: or1200_spram_1024x32_bw.v,v $`
66			`// Revision 1.4 2005/10/19 11:37:56 jcastillo`
67			`// Added support for RAMB16 Xilinx4/Spartan3 primitives`
68			`//`
69			`// Revision 1.3 2004/06/08 18:15:32 lampret`
70			`// Changed behavior of the simulation generic models`
71			`//`
72			`// Revision 1.2 2003/10/17 07:59:44 markom`
73			`// mbist signals updated according to newest convention`
74			`//`
75			`// Revision 1.1 2003/08/27 08:38:36 simons`
76			`// Added support for rams with byte write access.`
77			`//`
78			`//`
79
80			`// synopsys translate_off`
81			`include "timescale.v"
82			`// synopsys translate_on`
83			`include "or1200_defines.v"
84
85			`module or1200_spram_1024x32_bw(`
86			`ifdef OR1200_BIST
87			`// RAM BIST`
88			`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
89			`endif
90			`// Generic synchronous single-port RAM interface`
91			`clk, rst, ce, we, oe, addr, di, doq`
92			`);`
93
94			`ifdef OR1200_BIST
95			`//`
96			`// RAM BIST`
97			`//`
98			`input mbist_si_i;`
99			input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
100			`output mbist_so_o;`
101			`endif
102
103			`//`
104			`// Generic synchronous single-port RAM interface`
105			`//`
106			`input clk; // Clock`
107			`input rst; // Reset`
108			`input ce; // Chip enable input`
109			`input [3:0] we; // Write enable input`
110			`input oe; // Output enable input`
111			`input [9:0] addr; // address bus inputs`
112			`input [31:0] di; // input data bus`
113			`output [31:0] doq; // output data bus`
114
115			`//`
116			`// Internal wires and registers`
117			`//`
118
119			`ifdef OR1200_ARTISAN_SSP
120			`else
121			`ifdef OR1200_VIRTUALSILICON_SSP
122			`else
123			`ifdef OR1200_BIST
124			`assign mbist_so_o = mbist_si_i;`
125			`endif
126			`endif
127			`endif
128
129
130			`ifdef OR1200_ARTISAN_SSP
131
132			`//`
133			`// Instantiation of ASIC memory:`
134			`//`
135			`// Artisan Synchronous Single-Port RAM (ra1sh)`
136			`//`
137			`ifdef UNUSED
138			`art_hssp_1024x32_bw artisan_ssp(`
139			`else
140			`ifdef OR1200_BIST
141			`art_hssp_1024x32_bw_bist artisan_ssp(`
142			`else
143			`art_hssp_1024x32_bw artisan_ssp(`
144			`endif
145			`endif
146			`ifdef OR1200_BIST
147			`// RAM BIST`
148			`.mbist_si_i(mbist_si_i),`
149			`.mbist_so_o(mbist_so_o),`
150			`.mbist_ctrl_i(mbist_ctrl_i),`
151			`endif
152			`.CLK(clk),`
153			`.CEN(~ce),`
154			`.WEN(~we),`
155			`.A(addr),`
156			`.D(di),`
157			`.OEN(~oe),`
158			`.Q(doq)`
159			`);`
160
161			`else
162
163			`ifdef OR1200_AVANT_ATP
164
165			`//`
166			`// Instantiation of ASIC memory:`
167			`//`
168			`// Avant! Asynchronous Two-Port RAM`
169			`//`
170			`avant_atp avant_atp(`
171			`.web(~we),`
172			`.reb(),`
173			`.oeb(~oe),`
174			`.rcsb(),`
175			`.wcsb(),`
176			`.ra(addr),`
177			`.wa(addr),`
178			`.di(di),`
179			`.doq(doq)`
180			`);`
181
182			`else
183
184			`ifdef OR1200_VIRAGE_SSP
185
186			`//`
187			`// Instantiation of ASIC memory:`
188			`//`
189			`// Virage Synchronous 1-port R/W RAM`
190			`//`
191			`virage_ssp virage_ssp(`
192			`.clk(clk),`
193			`.adr(addr),`
194			`.d(di),`
195			`.we(we),`
196			`.oe(oe),`
197			`.me(ce),`
198			`.q(doq)`
199			`);`
200
201			`else
202
203			`ifdef OR1200_VIRTUALSILICON_SSP
204
205			`//`
206			`// Instantiation of ASIC memory:`
207			`//`
208			`// Virtual Silicon Single-Port Synchronous SRAM`
209			`//`
210			`ifdef OR1200_BIST
211			`wire mbist_si_i_ram_0;`
212			`wire mbist_si_i_ram_1;`
213			`wire mbist_si_i_ram_2;`
214			`wire mbist_si_i_ram_3;`
215			`wire mbist_so_o_ram_0;`
216			`wire mbist_so_o_ram_1;`
217			`wire mbist_so_o_ram_2;`
218			`wire mbist_so_o_ram_3;`
219			`assign mbist_si_i_ram_0 = mbist_si_i;`
220			`assign mbist_si_i_ram_1 = mbist_so_o_ram_0;`
221			`assign mbist_si_i_ram_2 = mbist_so_o_ram_1;`
222			`assign mbist_si_i_ram_3 = mbist_so_o_ram_2;`
223			`assign mbist_so_o = mbist_so_o_ram_3;`
224			`endif
225
226			`ifdef UNUSED
227			`vs_hdsp_1024x8 vs_ssp_0(`
228			`else
229			`ifdef OR1200_BIST
230			`vs_hdsp_1024x8_bist vs_ssp_0(`
231			`else
232			`vs_hdsp_1024x8 vs_ssp_0(`
233			`endif
234			`endif
235			`ifdef OR1200_BIST
236			`// RAM BIST`
237			`.mbist_si_i(mbist_si_i_ram_0),`
238			`.mbist_so_o(mbist_so_o_ram_0),`
239			`.mbist_ctrl_i(mbist_ctrl_i),`
240			`endif
241			`.CK(clk),`
242			`.ADR(addr),`
243			`.DI(di[7:0]),`
244			`.WEN(~we[0]),`
245			`.CEN(~ce),`
246			`.OEN(~oe),`
247			`.DOUT(doq[7:0])`
248			`);`
249
250			`ifdef UNUSED
251			`vs_hdsp_1024x8 vs_ssp_1(`
252			`else
253			`ifdef OR1200_BIST
254			`vs_hdsp_1024x8_bist vs_ssp_1(`
255			`else
256			`vs_hdsp_1024x8 vs_ssp_1(`
257			`endif
258			`endif
259			`ifdef OR1200_BIST
260			`// RAM BIST`
261			`.mbist_si_i(mbist_si_i_ram_1),`
262			`.mbist_so_o(mbist_so_o_ram_1),`
263			`.mbist_ctrl_i(mbist_ctrl_i),`
264			`endif
265			`.CK(clk),`
266			`.ADR(addr),`
267			`.DI(di[15:8]),`
268			`.WEN(~we[1]),`
269			`.CEN(~ce),`
270			`.OEN(~oe),`
271			`.DOUT(doq[15:8])`
272			`);`
273
274			`ifdef UNUSED
275			`vs_hdsp_1024x8 vs_ssp_2(`
276			`else
277			`ifdef OR1200_BIST
278			`vs_hdsp_1024x8_bist vs_ssp_2(`
279			`else
280			`vs_hdsp_1024x8 vs_ssp_2(`
281			`endif
282			`endif
283			`ifdef OR1200_BIST
284			`// RAM BIST`
285			`.mbist_si_i(mbist_si_i_ram_2),`
286			`.mbist_so_o(mbist_so_o_ram_2),`
287			`.mbist_ctrl_i(mbist_ctrl_i),`
288			`endif
289			`.CK(clk),`
290			`.ADR(addr),`
291			`.DI(di[23:16]),`
292			`.WEN(~we[2]),`
293			`.CEN(~ce),`
294			`.OEN(~oe),`
295			`.DOUT(doq[23:16])`
296			`);`
297
298			`ifdef UNUSED
299			`vs_hdsp_1024x8 vs_ssp_3(`
300			`else
301			`ifdef OR1200_BIST
302			`vs_hdsp_1024x8_bist vs_ssp_3(`
303			`else
304			`vs_hdsp_1024x8 vs_ssp_3(`
305			`endif
306			`endif
307			`ifdef OR1200_BIST
308			`// RAM BIST`
309			`.mbist_si_i(mbist_si_i_ram_3),`
310			`.mbist_so_o(mbist_so_o_ram_3),`
311			`.mbist_ctrl_i(mbist_ctrl_i),`
312			`endif
313			`.CK(clk),`
314			`.ADR(addr),`
315			`.DI(di[31:24]),`
316			`.WEN(~we[3]),`
317			`.CEN(~ce),`
318			`.OEN(~oe),`
319			`.DOUT(doq[31:24])`
320			`);`
321
322			`else
323
324			`ifdef OR1200_XILINX_RAMB4
325
326			`//`
327			`// Instantiation of FPGA memory:`
328			`//`
329			`// Virtex/Spartan2`
330			`//`
331
332			`//`
333			`// Block 0`
334			`//`
335			`RAMB4_S4 ramb4_s4_0(`
336			`.CLK(clk),`
337			`.RST(rst),`
338			`.ADDR(addr),`
339			`.DI(di[3:0]),`
340			`.EN(ce),`
341			`.WE(we[0]),`
342			`.DO(doq[3:0])`
343			`);`
344
345			`//`
346			`// Block 1`
347			`//`
348			`RAMB4_S4 ramb4_s4_1(`
349			`.CLK(clk),`
350			`.RST(rst),`
351			`.ADDR(addr),`
352			`.DI(di[7:4]),`
353			`.EN(ce),`
354			`.WE(we[0]),`
355			`.DO(doq[7:4])`
356			`);`
357
358			`//`
359			`// Block 2`
360			`//`
361			`RAMB4_S4 ramb4_s4_2(`
362			`.CLK(clk),`
363			`.RST(rst),`
364			`.ADDR(addr),`
365			`.DI(di[11:8]),`
366			`.EN(ce),`
367			`.WE(we[1]),`
368			`.DO(doq[11:8])`
369			`);`
370
371			`//`
372			`// Block 3`
373			`//`
374			`RAMB4_S4 ramb4_s4_3(`
375			`.CLK(clk),`
376			`.RST(rst),`
377			`.ADDR(addr),`
378			`.DI(di[15:12]),`
379			`.EN(ce),`
380			`.WE(we[1]),`
381			`.DO(doq[15:12])`
382			`);`
383
384			`//`
385			`// Block 4`
386			`//`
387			`RAMB4_S4 ramb4_s4_4(`
388			`.CLK(clk),`
389			`.RST(rst),`
390			`.ADDR(addr),`
391			`.DI(di[19:16]),`
392			`.EN(ce),`
393			`.WE(we[2]),`
394			`.DO(doq[19:16])`
395			`);`
396
397			`//`
398			`// Block 5`
399			`//`
400			`RAMB4_S4 ramb4_s4_5(`
401			`.CLK(clk),`
402			`.RST(rst),`
403			`.ADDR(addr),`
404			`.DI(di[23:20]),`
405			`.EN(ce),`
406			`.WE(we[2]),`
407			`.DO(doq[23:20])`
408			`);`
409
410			`//`
411			`// Block 6`
412			`//`
413			`RAMB4_S4 ramb4_s4_6(`
414			`.CLK(clk),`
415			`.RST(rst),`
416			`.ADDR(addr),`
417			`.DI(di[27:24]),`
418			`.EN(ce),`
419			`.WE(we[3]),`
420			`.DO(doq[27:24])`
421			`);`
422
423			`//`
424			`// Block 7`
425			`//`
426			`RAMB4_S4 ramb4_s4_7(`
427			`.CLK(clk),`
428			`.RST(rst),`
429			`.ADDR(addr),`
430			`.DI(di[31:28]),`
431			`.EN(ce),`
432			`.WE(we[3]),`
433			`.DO(doq[31:28])`
434			`);`
435
436			`else
437
438			`ifdef OR1200_XILINX_RAMB16
439
440			`//`
441			`// Instantiation of FPGA memory:`
442			`//`
443			`// Virtex4/Spartan3E`
444			`//`
445			`// Added By Nir Mor`
446			`//`
447
448			`//`
449			`// Block 0`
450			`//`
451			`RAMB16_S9 ramb16_s9_0(`
452			`.CLK(clk),`
453			`.SSR(rst),`
454			`.ADDR({1'b0,addr}),`
455			`.DI(di[7:0]),`
456			`.DIP(1'b0),`
457			`.EN(ce),`
458			`.WE(we[0]),`
459			`.DO(doq[7:0]),`
460			`.DOP()`
461			`);`
462
463			`//`
464			`// Block 1`
465			`//`
466			`RAMB16_S9 ramb16_s9_1(`
467			`.CLK(clk),`
468			`.SSR(rst),`
469			`.ADDR({1'b0,addr}),`
470			`.DI(di[15:8]),`
471			`.DIP(1'b0),`
472			`.EN(ce),`
473			`.WE(we[1]),`
474			`.DO(doq[15:8]),`
475			`.DOP()`
476			`);`
477
478			`//`
479			`// Block 2`
480			`//`
481			`RAMB16_S9 ramb16_s9_2(`
482			`.CLK(clk),`
483			`.SSR(rst),`
484			`.ADDR({1'b0,addr}),`
485			`.DI(di[23:16]),`
486			`.DIP(1'b0),`
487			`.EN(ce),`
488			`.WE(we[2]),`
489			`.DO(doq[23:16]),`
490			`.DOP()`
491			`);`
492
493			`//`
494			`// Block 3`
495			`//`
496			`RAMB16_S9 ramb16_s9_3(`
497			`.CLK(clk),`
498			`.SSR(rst),`
499			`.ADDR({1'b0,addr}),`
500			`.DI(di[31:24]),`
501			`.DIP(1'b0),`
502			`.EN(ce),`
503			`.WE(we[3]),`
504			`.DO(doq[31:24]),`
505			`.DOP()`
506			`);`
507
508			`else
509
510			`//`
511			`// Generic single-port synchronous RAM model`
512			`//`
513
514			`//`
515			`// Generic RAM's registers and wires`
516			`//`
517			`reg [7:0] mem_0 [1023:0]; // RAM content`
518			`reg [7:0] mem_1 [1023:0]; // RAM content`
519			`reg [7:0] mem_2 [1023:0]; // RAM content`
520			`reg [7:0] mem_3 [1023:0]; // RAM content`
521			`reg [9:0] addr_reg; // RAM address register`
522
523			`//`
524			`// Data output drivers`
525			`//`
526			`assign doq = (oe) ? {mem_3[addr_reg], mem_2[addr_reg], mem_1[addr_reg], mem_0[addr_reg]} : {32{1'b0}};`
527
528			`//`
529			`// RAM address register`
530			`//`
531			`always @(posedge clk or posedge rst)`
532			`if (rst)`
533			`addr_reg <= #1 10'h000;`
534			`else if (ce)`
535			`addr_reg <= #1 addr;`
536
537			`//`
538			`// RAM write byte 0`
539			`//`
540			`always @(posedge clk)`
541			`if (ce && we[0])`
542			`mem_0[addr] <= #1 di[7:0];`
543
544			`//`
545			`// RAM write byte 1`
546			`//`
547			`always @(posedge clk)`
548			`if (ce && we[1])`
549			`mem_1[addr] <= #1 di[15:8];`
550
551			`//`
552			`// RAM write byte 2`
553			`//`
554			`always @(posedge clk)`
555			`if (ce && we[2])`
556			`mem_2[addr] <= #1 di[23:16];`
557
558			`//`
559			`// RAM write byte 3`
560			`//`
561			`always @(posedge clk)`
562			`if (ce && we[3])`
563			`mem_3[addr] <= #1 di[31:24];`
564
565
566			`endif // !OR1200_XILINX_RAMB16
567			`endif // !OR1200_XILINX_RAMB4
568			`endif // !OR1200_VIRTUALSILICON_SSP
569			`endif // !OR1200_VIRAGE_SSP
570			`endif // !OR1200_AVANT_ATP
571			`endif // !OR1200_ARTISAN_SSP
572
573			`endmodule`