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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [or1200/] [rtl/] [verilog/] [or1200_spram_2048x32.v] - Blame information for rev 12

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Single-Port Synchronous RAM                         ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common single-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  single-port synchronous RAM.                                ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Single-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage Single-Port Sync RAM                               ////
////  - Virtual Silicon Single-Port Sync RAM                      ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB16                                      ////
////  - Xilinx Virtex RAMB4                                       ////
////  - Altera LPM                                                ////
////                                                              ////
////  To Do:                                                      ////
////   - xilinx rams need external tri-state logic                ////
////   - fix avant! two-port ram                                  ////
////   - add additional RAMs                                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_spram_2048x32.v,v $
// Revision 1.10  2005/10/19 11:37:56  jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
// Revision 1.9  2004/06/08 18:15:32  lampret
// Changed behavior of the simulation generic models
//
// Revision 1.8  2004/04/05 08:29:57  lampret
// Merged branch_qmem into main tree.
//
// Revision 1.4.4.1  2003/12/09 11:46:48  simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.4  2003/04/07 01:19:07  lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.3  2002/10/28 15:03:50  mohor
// Signal scanb_sen renamed to scanb_en.
//
// Revision 1.2  2002/10/17 20:04:40  lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8  2001/11/02 18:57:14  lampret
// Modified virtual silicon instantiations.
//
// Revision 1.7  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/30 05:38:02  lampret
// Adding empty directories required by HDL coding guidelines
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_spram_2048x32(
`ifdef OR1200_BIST
        // RAM BIST
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
        // Generic synchronous single-port RAM interface
        clk, rst, ce, we, oe, addr, di, doq
);
 
//
// Default address and data buses width
//
parameter aw = 11;
parameter dw = 32;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
//
// Generic synchronous single-port RAM interface
//
input                   clk;    // Clock
input                   rst;    // Reset
input                   ce;     // Chip enable input
input                   we;     // Write enable input
input                   oe;     // Output enable input
input   [aw-1:0] addr;   // address bus inputs
input   [dw-1:0] di;     // input data bus
output  [dw-1:0] doq;    // output data bus
 
//
// Internal wires and registers
//
 
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
 
`ifdef OR1200_ARTISAN_SSP
 
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hdsp_2048x32 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_2048x32_bist artisan_ssp(
`else
art_hssp_2048x32 artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i),
        .mbist_so_o(mbist_so_o),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CLK(clk),
        .CEN(~ce),
        .WEN(~we),
        .A(addr),
        .D(di),
        .OEN(~oe),
        .Q(doq)
);
 
`else
 
`ifdef OR1200_AVANT_ATP
 
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
        .web(~we),
        .reb(),
        .oeb(~oe),
        .rcsb(),
        .wcsb(),
        .ra(addr),
        .wa(addr),
        .di(di),
        .doq(doq)
);
 
`else
 
`ifdef OR1200_VIRAGE_SSP
 
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
        .clk(clk),
        .adr(addr),
        .d(di),
        .we(we),
        .oe(oe),
        .me(ce),
        .q(doq)
);
 
`else
 
`ifdef OR1200_VIRTUALSILICON_SSP
 
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_2048x32 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_2048x32_bist vs_ssp(
`else
vs_hdsp_2048x32 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i),
        .mbist_so_o(mbist_so_o),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di),
        .WEN(~we),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(doq)
);
 
`else
 
`ifdef OR1200_XILINX_RAMB4
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
RAMB4_S2 ramb4_s2_0(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[1:0]),
        .EN(ce),
        .WE(we),
        .DO(doq[1:0])
);
 
//
// Block 1
//
RAMB4_S2 ramb4_s2_1(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[3:2]),
        .EN(ce),
        .WE(we),
        .DO(doq[3:2])
);
 
//
// Block 2
//
RAMB4_S2 ramb4_s2_2(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[5:4]),
        .EN(ce),
        .WE(we),
        .DO(doq[5:4])
);
 
//
// Block 3
//
RAMB4_S2 ramb4_s2_3(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[7:6]),
        .EN(ce),
        .WE(we),
        .DO(doq[7:6])
);
 
//
// Block 4
//
RAMB4_S2 ramb4_s2_4(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[9:8]),
        .EN(ce),
        .WE(we),
        .DO(doq[9:8])
);
 
//
// Block 5
//
RAMB4_S2 ramb4_s2_5(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[11:10]),
        .EN(ce),
        .WE(we),
        .DO(doq[11:10])
);
 
//
// Block 6
//
RAMB4_S2 ramb4_s2_6(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[13:12]),
        .EN(ce),
        .WE(we),
        .DO(doq[13:12])
);
 
//
// Block 7
//
RAMB4_S2 ramb4_s2_7(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[15:14]),
        .EN(ce),
        .WE(we),
        .DO(doq[15:14])
);
 
//
// Block 8
//
RAMB4_S2 ramb4_s2_8(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[17:16]),
        .EN(ce),
        .WE(we),
        .DO(doq[17:16])
);
 
//
// Block 9
//
RAMB4_S2 ramb4_s2_9(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[19:18]),
        .EN(ce),
        .WE(we),
        .DO(doq[19:18])
);
 
//
// Block 10
//
RAMB4_S2 ramb4_s2_10(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[21:20]),
        .EN(ce),
        .WE(we),
        .DO(doq[21:20])
);
 
//
// Block 11
//
RAMB4_S2 ramb4_s2_11(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[23:22]),
        .EN(ce),
        .WE(we),
        .DO(doq[23:22])
);
 
//
// Block 12
//
RAMB4_S2 ramb4_s2_12(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[25:24]),
        .EN(ce),
        .WE(we),
        .DO(doq[25:24])
);
 
//
// Block 13
//
RAMB4_S2 ramb4_s2_13(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[27:26]),
        .EN(ce),
        .WE(we),
        .DO(doq[27:26])
);
 
//
// Block 14
//
RAMB4_S2 ramb4_s2_14(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[29:28]),
        .EN(ce),
        .WE(we),
        .DO(doq[29:28])
);
 
//
// Block 15
//
RAMB4_S2 ramb4_s2_15(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[31:30]),
        .EN(ce),
        .WE(we),
        .DO(doq[31:30])
);
 
`else
 
`ifdef OR1200_XILINX_RAMB16
 
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
// Added By Nir Mor
//
 
//
// Block 0
//
RAMB16_S9 ramb16_s9_0(
        .CLK(clk),
        .SSR(rst),
        .ADDR(addr),
        .DI(di[7:0]),
        .DIP(1'b0),
        .EN(ce),
        .WE(we),
        .DO(doq[7:0]),
        .DOP()
);
 
//
// Block 1
//
RAMB16_S9 ramb16_s9_1(
        .CLK(clk),
        .SSR(rst),
        .ADDR(addr),
        .DI(di[15:8]),
        .DIP(1'b0),
        .EN(ce),
        .WE(we),
        .DO(doq[15:8]),
        .DOP()
);
 
//
// Block 2
//
RAMB16_S9 ramb16_s9_2(
        .CLK(clk),
        .SSR(rst),
        .ADDR(addr),
        .DI(di[23:16]),
        .DIP(1'b0),
        .EN(ce),
        .WE(we),
        .DO(doq[23:16]),
        .DOP()
);
 
//
// Block 3
//
RAMB16_S9 ramb16_s9_3(
        .CLK(clk),
        .SSR(rst),
        .ADDR(addr),
        .DI(di[31:24]),
        .DIP(1'b0),
        .EN(ce),
        .WE(we),
        .DO(doq[31:24]),
        .DOP()
);
 
`else
 
`ifdef OR1200_ALTERA_LPM
 
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
 
wire    wr;
 
assign  wr = ce & we;
 
initial $display("Using Altera LPM.");
 
lpm_ram_dq lpm_ram_dq_component (
        .address(addr),
        .inclock(clk),
        .outclock(clk),
        .data(di),
        .we(wr),
        .q(doq)
);
 
defparam lpm_ram_dq_component.lpm_width = dw,
        lpm_ram_dq_component.lpm_widthad = aw,
        lpm_ram_dq_component.lpm_indata = "REGISTERED",
        lpm_ram_dq_component.lpm_address_control = "REGISTERED",
        lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
        lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
        // examplar attribute lpm_ram_dq_component NOOPT TRUE
 
`else
 
//
// Generic single-port synchronous RAM model
//
 
//
// Generic RAM's registers and wires
//
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
reg     [aw-1:0] addr_reg;               // RAM address register
 
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
 
//
// RAM address register
//
always @(posedge clk or posedge rst)
        if (rst)
                addr_reg <= #1 {aw{1'b0}};
        else if (ce)
                addr_reg <= #1 addr;
 
//
// RAM write
//
always @(posedge clk)
        if (ce && we)
                mem[addr] <= #1 di;
 
`endif  // !OR1200_ALTERA_LPM
`endif  // !OR1200_XILINX_RAMB16
`endif  // !OR1200_XILINX_RAMB4
`endif  // !OR1200_VIRTUALSILICON_SSP
`endif  // !OR1200_VIRAGE_SSP
`endif  // !OR1200_AVANT_ATP
`endif  // !OR1200_ARTISAN_SSP
 
endmodule

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Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [or1200/] [rtl/] [verilog/] [or1200_spram_2048x32.v] - Blame information for rev 12

Line No.	Rev	Author	Line
1	12	xianfeng	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Single-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common single-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// single-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// - Artisan Single-Port Sync RAM ////`
20			`//// - Avant! Two-Port Sync RAM (*) ////`
21			`//// - Virage Single-Port Sync RAM ////`
22			`//// - Virtual Silicon Single-Port Sync RAM ////`
23			`//// ////`
24			`//// Supported FPGA RAMs are: ////`
25			`//// - Xilinx Virtex RAMB16 ////`
26			`//// - Xilinx Virtex RAMB4 ////`
27			`//// - Altera LPM ////`
28			`//// ////`
29			`//// To Do: ////`
30			`//// - xilinx rams need external tri-state logic ////`
31			`//// - fix avant! two-port ram ////`
32			`//// - add additional RAMs ////`
33			`//// ////`
34			`//// Author(s): ////`
35			`//// - Damjan Lampret, lampret@opencores.org ////`
36			`//// ////`
37			`//////////////////////////////////////////////////////////////////////`
38			`//// ////`
39			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
40			`//// ////`
41			`//// This source file may be used and distributed without ////`
42			`//// restriction provided that this copyright statement is not ////`
43			`//// removed from the file and that any derivative work contains ////`
44			`//// the original copyright notice and the associated disclaimer. ////`
45			`//// ////`
46			`//// This source file is free software; you can redistribute it ////`
47			`//// and/or modify it under the terms of the GNU Lesser General ////`
48			`//// Public License as published by the Free Software Foundation; ////`
49			`//// either version 2.1 of the License, or (at your option) any ////`
50			`//// later version. ////`
51			`//// ////`
52			`//// This source is distributed in the hope that it will be ////`
53			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
54			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
55			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
56			`//// details. ////`
57			`//// ////`
58			`//// You should have received a copy of the GNU Lesser General ////`
59			`//// Public License along with this source; if not, download it ////`
60			`//// from http://www.opencores.org/lgpl.shtml ////`
61			`//// ////`
62			`//////////////////////////////////////////////////////////////////////`
63			`//`
64			`// CVS Revision History`
65			`//`
66			`// $Log: or1200_spram_2048x32.v,v $`
67			`// Revision 1.10 2005/10/19 11:37:56 jcastillo`
68			`// Added support for RAMB16 Xilinx4/Spartan3 primitives`
69			`//`
70			`// Revision 1.9 2004/06/08 18:15:32 lampret`
71			`// Changed behavior of the simulation generic models`
72			`//`
73			`// Revision 1.8 2004/04/05 08:29:57 lampret`
74			`// Merged branch_qmem into main tree.`
75			`//`
76			`// Revision 1.4.4.1 2003/12/09 11:46:48 simons`
77			`// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.`
78			`//`
79			`// Revision 1.4 2003/04/07 01:19:07 lampret`
80			`// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.`
81			`//`
82			`// Revision 1.3 2002/10/28 15:03:50 mohor`
83			`// Signal scanb_sen renamed to scanb_en.`
84			`//`
85			`// Revision 1.2 2002/10/17 20:04:40 lampret`
86			`// Added BIST scan. Special VS RAMs need to be used to implement BIST.`
87			`//`
88			`// Revision 1.1 2002/01/03 08:16:15 lampret`
89			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
90			`//`
91			`// Revision 1.8 2001/11/02 18:57:14 lampret`
92			`// Modified virtual silicon instantiations.`
93			`//`
94			`// Revision 1.7 2001/10/21 17:57:16 lampret`
95			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
96			`//`
97			`// Revision 1.6 2001/10/14 13:12:09 lampret`
98			`// MP3 version.`
99			`//`
100			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
101			`// no message`
102			`//`
103			`// Revision 1.1 2001/08/09 13:39:33 lampret`
104			`// Major clean-up.`
105			`//`
106			`// Revision 1.2 2001/07/30 05:38:02 lampret`
107			`// Adding empty directories required by HDL coding guidelines`
108			`//`
109			`//`
110
111			`// synopsys translate_off`
112			`include "timescale.v"
113			`// synopsys translate_on`
114			`include "or1200_defines.v"
115
116			`module or1200_spram_2048x32(`
117			`ifdef OR1200_BIST
118			`// RAM BIST`
119			`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
120			`endif
121			`// Generic synchronous single-port RAM interface`
122			`clk, rst, ce, we, oe, addr, di, doq`
123			`);`
124
125			`//`
126			`// Default address and data buses width`
127			`//`
128			`parameter aw = 11;`
129			`parameter dw = 32;`
130
131			`ifdef OR1200_BIST
132			`//`
133			`// RAM BIST`
134			`//`
135			`input mbist_si_i;`
136			input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
137			`output mbist_so_o;`
138			`endif
139
140			`//`
141			`// Generic synchronous single-port RAM interface`
142			`//`
143			`input clk; // Clock`
144			`input rst; // Reset`
145			`input ce; // Chip enable input`
146			`input we; // Write enable input`
147			`input oe; // Output enable input`
148			`input [aw-1:0] addr; // address bus inputs`
149			`input [dw-1:0] di; // input data bus`
150			`output [dw-1:0] doq; // output data bus`
151
152			`//`
153			`// Internal wires and registers`
154			`//`
155
156			`ifdef OR1200_ARTISAN_SSP
157			`else
158			`ifdef OR1200_VIRTUALSILICON_SSP
159			`else
160			`ifdef OR1200_BIST
161			`assign mbist_so_o = mbist_si_i;`
162			`endif
163			`endif
164			`endif
165
166			`ifdef OR1200_ARTISAN_SSP
167
168			`//`
169			`// Instantiation of ASIC memory:`
170			`//`
171			`// Artisan Synchronous Single-Port RAM (ra1sh)`
172			`//`
173			`ifdef UNUSED
174			`art_hdsp_2048x32 #(dw, 1<<aw, aw) artisan_ssp(`
175			`else
176			`ifdef OR1200_BIST
177			`art_hssp_2048x32_bist artisan_ssp(`
178			`else
179			`art_hssp_2048x32 artisan_ssp(`
180			`endif
181			`endif
182			`ifdef OR1200_BIST
183			`// RAM BIST`
184			`.mbist_si_i(mbist_si_i),`
185			`.mbist_so_o(mbist_so_o),`
186			`.mbist_ctrl_i(mbist_ctrl_i),`
187			`endif
188			`.CLK(clk),`
189			`.CEN(~ce),`
190			`.WEN(~we),`
191			`.A(addr),`
192			`.D(di),`
193			`.OEN(~oe),`
194			`.Q(doq)`
195			`);`
196
197			`else
198
199			`ifdef OR1200_AVANT_ATP
200
201			`//`
202			`// Instantiation of ASIC memory:`
203			`//`
204			`// Avant! Asynchronous Two-Port RAM`
205			`//`
206			`avant_atp avant_atp(`
207			`.web(~we),`
208			`.reb(),`
209			`.oeb(~oe),`
210			`.rcsb(),`
211			`.wcsb(),`
212			`.ra(addr),`
213			`.wa(addr),`
214			`.di(di),`
215			`.doq(doq)`
216			`);`
217
218			`else
219
220			`ifdef OR1200_VIRAGE_SSP
221
222			`//`
223			`// Instantiation of ASIC memory:`
224			`//`
225			`// Virage Synchronous 1-port R/W RAM`
226			`//`
227			`virage_ssp virage_ssp(`
228			`.clk(clk),`
229			`.adr(addr),`
230			`.d(di),`
231			`.we(we),`
232			`.oe(oe),`
233			`.me(ce),`
234			`.q(doq)`
235			`);`
236
237			`else
238
239			`ifdef OR1200_VIRTUALSILICON_SSP
240
241			`//`
242			`// Instantiation of ASIC memory:`
243			`//`
244			`// Virtual Silicon Single-Port Synchronous SRAM`
245			`//`
246			`ifdef UNUSED
247			`vs_hdsp_2048x32 #(1<<aw, aw-1, dw-1) vs_ssp(`
248			`else
249			`ifdef OR1200_BIST
250			`vs_hdsp_2048x32_bist vs_ssp(`
251			`else
252			`vs_hdsp_2048x32 vs_ssp(`
253			`endif
254			`endif
255			`ifdef OR1200_BIST
256			`// RAM BIST`
257			`.mbist_si_i(mbist_si_i),`
258			`.mbist_so_o(mbist_so_o),`
259			`.mbist_ctrl_i(mbist_ctrl_i),`
260			`endif
261			`.CK(clk),`
262			`.ADR(addr),`
263			`.DI(di),`
264			`.WEN(~we),`
265			`.CEN(~ce),`
266			`.OEN(~oe),`
267			`.DOUT(doq)`
268			`);`
269
270			`else
271
272			`ifdef OR1200_XILINX_RAMB4
273
274			`//`
275			`// Instantiation of FPGA memory:`
276			`//`
277			`// Virtex/Spartan2`
278			`//`
279
280			`//`
281			`// Block 0`
282			`//`
283			`RAMB4_S2 ramb4_s2_0(`
284			`.CLK(clk),`
285			`.RST(rst),`
286			`.ADDR(addr),`
287			`.DI(di[1:0]),`
288			`.EN(ce),`
289			`.WE(we),`
290			`.DO(doq[1:0])`
291			`);`
292
293			`//`
294			`// Block 1`
295			`//`
296			`RAMB4_S2 ramb4_s2_1(`
297			`.CLK(clk),`
298			`.RST(rst),`
299			`.ADDR(addr),`
300			`.DI(di[3:2]),`
301			`.EN(ce),`
302			`.WE(we),`
303			`.DO(doq[3:2])`
304			`);`
305
306			`//`
307			`// Block 2`
308			`//`
309			`RAMB4_S2 ramb4_s2_2(`
310			`.CLK(clk),`
311			`.RST(rst),`
312			`.ADDR(addr),`
313			`.DI(di[5:4]),`
314			`.EN(ce),`
315			`.WE(we),`
316			`.DO(doq[5:4])`
317			`);`
318
319			`//`
320			`// Block 3`
321			`//`
322			`RAMB4_S2 ramb4_s2_3(`
323			`.CLK(clk),`
324			`.RST(rst),`
325			`.ADDR(addr),`
326			`.DI(di[7:6]),`
327			`.EN(ce),`
328			`.WE(we),`
329			`.DO(doq[7:6])`
330			`);`
331
332			`//`
333			`// Block 4`
334			`//`
335			`RAMB4_S2 ramb4_s2_4(`
336			`.CLK(clk),`
337			`.RST(rst),`
338			`.ADDR(addr),`
339			`.DI(di[9:8]),`
340			`.EN(ce),`
341			`.WE(we),`
342			`.DO(doq[9:8])`
343			`);`
344
345			`//`
346			`// Block 5`
347			`//`
348			`RAMB4_S2 ramb4_s2_5(`
349			`.CLK(clk),`
350			`.RST(rst),`
351			`.ADDR(addr),`
352			`.DI(di[11:10]),`
353			`.EN(ce),`
354			`.WE(we),`
355			`.DO(doq[11:10])`
356			`);`
357
358			`//`
359			`// Block 6`
360			`//`
361			`RAMB4_S2 ramb4_s2_6(`
362			`.CLK(clk),`
363			`.RST(rst),`
364			`.ADDR(addr),`
365			`.DI(di[13:12]),`
366			`.EN(ce),`
367			`.WE(we),`
368			`.DO(doq[13:12])`
369			`);`
370
371			`//`
372			`// Block 7`
373			`//`
374			`RAMB4_S2 ramb4_s2_7(`
375			`.CLK(clk),`
376			`.RST(rst),`
377			`.ADDR(addr),`
378			`.DI(di[15:14]),`
379			`.EN(ce),`
380			`.WE(we),`
381			`.DO(doq[15:14])`
382			`);`
383
384			`//`
385			`// Block 8`
386			`//`
387			`RAMB4_S2 ramb4_s2_8(`
388			`.CLK(clk),`
389			`.RST(rst),`
390			`.ADDR(addr),`
391			`.DI(di[17:16]),`
392			`.EN(ce),`
393			`.WE(we),`
394			`.DO(doq[17:16])`
395			`);`
396
397			`//`
398			`// Block 9`
399			`//`
400			`RAMB4_S2 ramb4_s2_9(`
401			`.CLK(clk),`
402			`.RST(rst),`
403			`.ADDR(addr),`
404			`.DI(di[19:18]),`
405			`.EN(ce),`
406			`.WE(we),`
407			`.DO(doq[19:18])`
408			`);`
409
410			`//`
411			`// Block 10`
412			`//`
413			`RAMB4_S2 ramb4_s2_10(`
414			`.CLK(clk),`
415			`.RST(rst),`
416			`.ADDR(addr),`
417			`.DI(di[21:20]),`
418			`.EN(ce),`
419			`.WE(we),`
420			`.DO(doq[21:20])`
421			`);`
422
423			`//`
424			`// Block 11`
425			`//`
426			`RAMB4_S2 ramb4_s2_11(`
427			`.CLK(clk),`
428			`.RST(rst),`
429			`.ADDR(addr),`
430			`.DI(di[23:22]),`
431			`.EN(ce),`
432			`.WE(we),`
433			`.DO(doq[23:22])`
434			`);`
435
436			`//`
437			`// Block 12`
438			`//`
439			`RAMB4_S2 ramb4_s2_12(`
440			`.CLK(clk),`
441			`.RST(rst),`
442			`.ADDR(addr),`
443			`.DI(di[25:24]),`
444			`.EN(ce),`
445			`.WE(we),`
446			`.DO(doq[25:24])`
447			`);`
448
449			`//`
450			`// Block 13`
451			`//`
452			`RAMB4_S2 ramb4_s2_13(`
453			`.CLK(clk),`
454			`.RST(rst),`
455			`.ADDR(addr),`
456			`.DI(di[27:26]),`
457			`.EN(ce),`
458			`.WE(we),`
459			`.DO(doq[27:26])`
460			`);`
461
462			`//`
463			`// Block 14`
464			`//`
465			`RAMB4_S2 ramb4_s2_14(`
466			`.CLK(clk),`
467			`.RST(rst),`
468			`.ADDR(addr),`
469			`.DI(di[29:28]),`
470			`.EN(ce),`
471			`.WE(we),`
472			`.DO(doq[29:28])`
473			`);`
474
475			`//`
476			`// Block 15`
477			`//`
478			`RAMB4_S2 ramb4_s2_15(`
479			`.CLK(clk),`
480			`.RST(rst),`
481			`.ADDR(addr),`
482			`.DI(di[31:30]),`
483			`.EN(ce),`
484			`.WE(we),`
485			`.DO(doq[31:30])`
486			`);`
487
488			`else
489
490			`ifdef OR1200_XILINX_RAMB16
491
492			`//`
493			`// Instantiation of FPGA memory:`
494			`//`
495			`// Virtex4/Spartan3E`
496			`//`
497			`// Added By Nir Mor`
498			`//`
499
500			`//`
501			`// Block 0`
502			`//`
503			`RAMB16_S9 ramb16_s9_0(`
504			`.CLK(clk),`
505			`.SSR(rst),`
506			`.ADDR(addr),`
507			`.DI(di[7:0]),`
508			`.DIP(1'b0),`
509			`.EN(ce),`
510			`.WE(we),`
511			`.DO(doq[7:0]),`
512			`.DOP()`
513			`);`
514
515			`//`
516			`// Block 1`
517			`//`
518			`RAMB16_S9 ramb16_s9_1(`
519			`.CLK(clk),`
520			`.SSR(rst),`
521			`.ADDR(addr),`
522			`.DI(di[15:8]),`
523			`.DIP(1'b0),`
524			`.EN(ce),`
525			`.WE(we),`
526			`.DO(doq[15:8]),`
527			`.DOP()`
528			`);`
529
530			`//`
531			`// Block 2`
532			`//`
533			`RAMB16_S9 ramb16_s9_2(`
534			`.CLK(clk),`
535			`.SSR(rst),`
536			`.ADDR(addr),`
537			`.DI(di[23:16]),`
538			`.DIP(1'b0),`
539			`.EN(ce),`
540			`.WE(we),`
541			`.DO(doq[23:16]),`
542			`.DOP()`
543			`);`
544
545			`//`
546			`// Block 3`
547			`//`
548			`RAMB16_S9 ramb16_s9_3(`
549			`.CLK(clk),`
550			`.SSR(rst),`
551			`.ADDR(addr),`
552			`.DI(di[31:24]),`
553			`.DIP(1'b0),`
554			`.EN(ce),`
555			`.WE(we),`
556			`.DO(doq[31:24]),`
557			`.DOP()`
558			`);`
559
560			`else
561
562			`ifdef OR1200_ALTERA_LPM
563
564			`//`
565			`// Instantiation of FPGA memory:`
566			`//`
567			`// Altera LPM`
568			`//`
569			`// Added By Jamil Khatib`
570			`//`
571
572			`wire wr;`
573
574			`assign wr = ce & we;`
575
576			`initial $display("Using Altera LPM.");`
577
578			`lpm_ram_dq lpm_ram_dq_component (`
579			`.address(addr),`
580			`.inclock(clk),`
581			`.outclock(clk),`
582			`.data(di),`
583			`.we(wr),`
584			`.q(doq)`
585			`);`
586
587			`defparam lpm_ram_dq_component.lpm_width = dw,`
588			`lpm_ram_dq_component.lpm_widthad = aw,`
589			`lpm_ram_dq_component.lpm_indata = "REGISTERED",`
590			`lpm_ram_dq_component.lpm_address_control = "REGISTERED",`
591			`lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",`
592			`lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";`
593			`// examplar attribute lpm_ram_dq_component NOOPT TRUE`
594
595			`else
596
597			`//`
598			`// Generic single-port synchronous RAM model`
599			`//`
600
601			`//`
602			`// Generic RAM's registers and wires`
603			`//`
604			`reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content`
605			`reg [aw-1:0] addr_reg; // RAM address register`
606
607			`//`
608			`// Data output drivers`
609			`//`
610			`assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};`
611
612			`//`
613			`// RAM address register`
614			`//`
615			`always @(posedge clk or posedge rst)`
616			`if (rst)`
617			`addr_reg <= #1 {aw{1'b0}};`
618			`else if (ce)`
619			`addr_reg <= #1 addr;`
620
621			`//`
622			`// RAM write`
623			`//`
624			`always @(posedge clk)`
625			`if (ce && we)`
626			`mem[addr] <= #1 di;`
627
628			`endif // !OR1200_ALTERA_LPM
629			`endif // !OR1200_XILINX_RAMB16
630			`endif // !OR1200_XILINX_RAMB4
631			`endif // !OR1200_VIRTUALSILICON_SSP
632			`endif // !OR1200_VIRAGE_SSP
633			`endif // !OR1200_AVANT_ATP
634			`endif // !OR1200_ARTISAN_SSP
635
636			`endmodule`