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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [or1200/] [rtl/] [verilog/] [or1200_spram_2048x32_bw.v] - Blame information for rev 12

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Single-Port Synchronous RAM with byte write signals ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common single-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  single-port synchronous RAM.                                ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Single-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage Single-Port Sync RAM                               ////
////  - Virtual Silicon Single-Port Sync RAM                      ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB16                                      ////
////  - Xilinx Virtex RAMB4                                       ////
////                                                              ////
////  To Do:                                                      ////
////   - xilinx rams need external tri-state logic                ////
////   - fix avant! two-port ram                                  ////
////   - add additional RAMs                                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_spram_2048x32_bw.v,v $
// Revision 1.5  2005/10/19 11:37:56  jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
// Revision 1.4  2004/06/08 18:15:32  lampret
// Changed behavior of the simulation generic models
//
// Revision 1.3  2003/10/17 07:59:44  markom
// mbist signals updated according to newest convention
//
// Revision 1.2  2003/09/12 09:03:54  dries
// correct all the syntax errors
//
// Revision 1.1  2003/08/26 09:37:02  simons
// Added support for rams with byte write access.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_spram_2048x32_bw(
`ifdef OR1200_BIST
        // RAM BIST
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
        // Generic synchronous single-port RAM interface
        clk, rst, ce, we, oe, addr, di, doq
);
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input                   mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control
output                  mbist_so_o;
`endif
 
//
// Generic synchronous single-port RAM interface
//
input                   clk;    // Clock
input                   rst;    // Reset
input                   ce;     // Chip enable input
input   [3:0]           we;     // Write enable input
input                   oe;     // Output enable input
input   [10:0]          addr;   // address bus inputs
input   [31:0]          di;     // input data bus
output  [31:0]          doq;     // output data bus
 
//
// Internal wires and registers
//
 
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
 
 
`ifdef OR1200_ARTISAN_SSP
 
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_2048x32_bw artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_2048x32_bw_bist artisan_ssp(
`else
art_hssp_2048x32_bw artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i),
        .mbist_so_o(mbist_so_o),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CLK(clk),
        .CEN(~ce),
        .WEN(~we),
        .A(addr),
        .D(di),
        .OEN(~oe),
        .Q(doq)
);
 
`else
 
`ifdef OR1200_AVANT_ATP
 
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
        .web(~we),
        .reb(),
        .oeb(~oe),
        .rcsb(),
        .wcsb(),
        .ra(addr),
        .wa(addr),
        .di(di),
        .doq(doq)
);
 
`else
 
`ifdef OR1200_VIRAGE_SSP
 
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
        .clk(clk),
        .adr(addr),
        .d(di),
        .we(we),
        .oe(oe),
        .me(ce),
        .q(doq)
);
 
`else
 
`ifdef OR1200_VIRTUALSILICON_SSP
 
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef OR1200_BIST
wire mbist_si_i_ram_0;
wire mbist_si_i_ram_1;
wire mbist_si_i_ram_2;
wire mbist_si_i_ram_3;
wire mbist_so_o_ram_0;
wire mbist_so_o_ram_1;
wire mbist_so_o_ram_2;
wire mbist_so_o_ram_3;
assign mbist_si_i_ram_0 = mbist_si_i;
assign mbist_si_i_ram_1 = mbist_so_o_ram_0;
assign mbist_si_i_ram_2 = mbist_so_o_ram_1;
assign mbist_si_i_ram_3 = mbist_so_o_ram_2;
assign mbist_so_o = mbist_so_o_ram_3;
`endif
 
`ifdef UNUSED
vs_hdsp_2048x8 vs_ssp_0(
`else
`ifdef OR1200_BIST
vs_hdsp_2048x8_bist vs_ssp_0(
`else
vs_hdsp_2048x8 vs_ssp_0(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i_ram_0),
        .mbist_so_o(mbist_so_o_ram_0),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di[7:0]),
        .WEN(~we[0]),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(doq[7:0])
);
 
`ifdef UNUSED
vs_hdsp_2048x8 vs_ssp_1(
`else
`ifdef OR1200_BIST
vs_hdsp_2048x8_bist vs_ssp_1(
`else
vs_hdsp_2048x8 vs_ssp_1(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i_ram_1),
        .mbist_so_o(mbist_so_o_ram_1),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di[15:8]),
        .WEN(~we[1]),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(doq[15:8])
);
 
`ifdef UNUSED
vs_hdsp_2048x8 vs_ssp_2(
`else
`ifdef OR1200_BIST
vs_hdsp_2048x8_bist vs_ssp_2(
`else
vs_hdsp_2048x8 vs_ssp_2(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i_ram_2),
        .mbist_so_o(mbist_so_o_ram_2),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di[23:16]),
        .WEN(~we[2]),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(doq[23:16])
);
 
`ifdef UNUSED
vs_hdsp_2048x8 vs_ssp_3(
`else
`ifdef OR1200_BIST
vs_hdsp_2048x8_bist vs_ssp_3(
`else
vs_hdsp_2048x8 vs_ssp_3(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i_ram_3),
        .mbist_so_o(mbist_so_o_ram_3),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di[31:24]),
        .WEN(~we[3]),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(doq[31:24])
);
 
`else
 
`ifdef OR1200_XILINX_RAMB4
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
RAMB4_S2 ramb4_s2_0(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[1:0]),
        .EN(ce),
        .WE(we[0]),
        .DO(doq[1:0])
);
 
//
// Block 1
//
RAMB4_S2 ramb4_s2_1(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[3:2]),
        .EN(ce),
        .WE(we[0]),
        .DO(doq[3:2])
);
 
//
// Block 2
//
RAMB4_S2 ramb4_s2_2(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[5:4]),
        .EN(ce),
        .WE(we[0]),
        .DO(doq[5:4])
);
 
//
// Block 3
//
RAMB4_S2 ramb4_s2_3(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[7:6]),
        .EN(ce),
        .WE(we[0]),
        .DO(doq[7:6])
);
//
// Block 4
//
RAMB4_S2 ramb4_s2_4(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[9:8]),
        .EN(ce),
        .WE(we[1]),
        .DO(doq[9:8])
);
 
//
// Block 5
//
RAMB4_S2 ramb4_s2_5(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[11:10]),
        .EN(ce),
        .WE(we[1]),
        .DO(doq[11:10])
);
 
//
// Block 6
//
RAMB4_S2 ramb4_s2_6(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[13:12]),
        .EN(ce),
        .WE(we[1]),
        .DO(doq[13:12])
);
 
//
// Block 7
//
RAMB4_S2 ramb4_s2_7(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[15:14]),
        .EN(ce),
        .WE(we[1]),
        .DO(doq[15:14])
);
//
// Block 8
//
RAMB4_S2 ramb4_s2_8(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[17:16]),
        .EN(ce),
        .WE(we[2]),
        .DO(doq[17:16])
);
 
//
// Block 9
//
RAMB4_S2 ramb4_s2_9(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[19:18]),
        .EN(ce),
        .WE(we[2]),
        .DO(doq[19:18])
);
 
//
// Block 10
//
RAMB4_S2 ramb4_s2_10(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[21:20]),
        .EN(ce),
        .WE(we[2]),
        .DO(doq[21:20])
);
 
//
// Block 11
//
RAMB4_S2 ramb4_s2_11(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[23:22]),
        .EN(ce),
        .WE(we[2]),
        .DO(doq[23:22])
);
//
// Block 12
//
RAMB4_S2 ramb4_s2_12(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[25:24]),
        .EN(ce),
        .WE(we[3]),
        .DO(doq[25:24])
);
 
//
// Block 13
//
RAMB4_S2 ramb4_s2_13(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[27:26]),
        .EN(ce),
        .WE(we[3]),
        .DO(doq[27:26])
);
 
//
// Block 14
//
RAMB4_S2 ramb4_s2_14(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[29:28]),
        .EN(ce),
        .WE(we[3]),
        .DO(doq[29:28])
);
 
//
// Block 15
//
RAMB4_S2 ramb4_s2_15(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[31:30]),
        .EN(ce),
        .WE(we[3]),
        .DO(doq[31:30])
);
 
`else
 
`ifdef OR1200_XILINX_RAMB16
 
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
// Added By Nir Mor
//
 
//
// Block 0
//
RAMB16_S9 ramb16_s9_0(
        .CLK(clk),
        .SSR(rst),
        .ADDR(addr),
        .DI(di[7:0]),
        .DIP(1'b0),
        .EN(ce),
        .WE(we[0]),
        .DO(doq[7:0]),
        .DOP()
);
 
//
// Block 1
//
RAMB16_S9 ramb16_s9_1(
        .CLK(clk),
        .SSR(rst),
        .ADDR(addr),
        .DI(di[15:8]),
        .DIP(1'b0),
        .EN(ce),
        .WE(we[1]),
        .DO(doq[15:8]),
        .DOP()
);
 
//
// Block 2
//
RAMB16_S9 ramb16_s9_2(
        .CLK(clk),
        .SSR(rst),
        .ADDR(addr),
        .DI(di[23:16]),
        .DIP(1'b0),
        .EN(ce),
        .WE(we[2]),
        .DO(doq[23:16]),
        .DOP()
);
 
//
// Block 3
//
RAMB16_S9 ramb16_s9_3(
        .CLK(clk),
        .SSR(rst),
        .ADDR(addr),
        .DI(di[31:24]),
        .DIP(1'b0),
        .EN(ce),
        .WE(we[3]),
        .DO(doq[31:24]),
        .DOP()
);
 
`else
 
//
// Generic single-port synchronous RAM model
//
 
//
// Generic RAM's registers and wires
//
reg     [7:0]        mem_0 [2047:0];              // RAM content
reg     [7:0]        mem_1 [2047:0];              // RAM content
reg     [7:0]        mem_2 [2047:0];              // RAM content
reg     [7:0]        mem_3 [2047:0];              // RAM content
reg     [10:0]       addr_reg;                    // RAM address register
 
//
// Data output drivers
//
assign doq = (oe) ? {mem_3[addr_reg], mem_2[addr_reg], mem_1[addr_reg], mem_0[addr_reg]} : {32{1'b0}};
 
//
// RAM address register
//
always @(posedge clk or posedge rst)
        if (rst)
                addr_reg <= #1 11'h000;
        else if (ce)
                addr_reg <= #1 addr;
 
//
// RAM write byte 0
//
always @(posedge clk)
        if (ce && we[0])
                mem_0[addr] <= #1 di[7:0];
 
//
// RAM write byte 1
//
always @(posedge clk)
        if (ce && we[1])
                mem_1[addr] <= #1 di[15:8];
 
//
// RAM write byte 2
//
always @(posedge clk)
        if (ce && we[2])
                mem_2[addr] <= #1 di[23:16];
 
//
// RAM write byte 3
//
always @(posedge clk)
        if (ce && we[3])
                mem_3[addr] <= #1 di[31:24];
 
`endif  // !OR1200_XILINX_RAMB16
`endif  // !OR1200_XILINX_RAMB4
`endif  // !OR1200_VIRTUALSILICON_SSP
`endif  // !OR1200_VIRAGE_SSP
`endif  // !OR1200_AVANT_ATP
`endif  // !OR1200_ARTISAN_SSP
 
endmodule

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Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [or1200/] [rtl/] [verilog/] [or1200_spram_2048x32_bw.v] - Blame information for rev 12

Line No.	Rev	Author	Line
1	12	xianfeng	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Single-Port Synchronous RAM with byte write signals ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common single-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// single-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// - Artisan Single-Port Sync RAM ////`
20			`//// - Avant! Two-Port Sync RAM (*) ////`
21			`//// - Virage Single-Port Sync RAM ////`
22			`//// - Virtual Silicon Single-Port Sync RAM ////`
23			`//// ////`
24			`//// Supported FPGA RAMs are: ////`
25			`//// - Xilinx Virtex RAMB16 ////`
26			`//// - Xilinx Virtex RAMB4 ////`
27			`//// ////`
28			`//// To Do: ////`
29			`//// - xilinx rams need external tri-state logic ////`
30			`//// - fix avant! two-port ram ////`
31			`//// - add additional RAMs ////`
32			`//// ////`
33			`//// Author(s): ////`
34			`//// - Damjan Lampret, lampret@opencores.org ////`
35			`//// ////`
36			`//////////////////////////////////////////////////////////////////////`
37			`//// ////`
38			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
39			`//// ////`
40			`//// This source file may be used and distributed without ////`
41			`//// restriction provided that this copyright statement is not ////`
42			`//// removed from the file and that any derivative work contains ////`
43			`//// the original copyright notice and the associated disclaimer. ////`
44			`//// ////`
45			`//// This source file is free software; you can redistribute it ////`
46			`//// and/or modify it under the terms of the GNU Lesser General ////`
47			`//// Public License as published by the Free Software Foundation; ////`
48			`//// either version 2.1 of the License, or (at your option) any ////`
49			`//// later version. ////`
50			`//// ////`
51			`//// This source is distributed in the hope that it will be ////`
52			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
53			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
54			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
55			`//// details. ////`
56			`//// ////`
57			`//// You should have received a copy of the GNU Lesser General ////`
58			`//// Public License along with this source; if not, download it ////`
59			`//// from http://www.opencores.org/lgpl.shtml ////`
60			`//// ////`
61			`//////////////////////////////////////////////////////////////////////`
62			`//`
63			`// CVS Revision History`
64			`//`
65			`// $Log: or1200_spram_2048x32_bw.v,v $`
66			`// Revision 1.5 2005/10/19 11:37:56 jcastillo`
67			`// Added support for RAMB16 Xilinx4/Spartan3 primitives`
68			`//`
69			`// Revision 1.4 2004/06/08 18:15:32 lampret`
70			`// Changed behavior of the simulation generic models`
71			`//`
72			`// Revision 1.3 2003/10/17 07:59:44 markom`
73			`// mbist signals updated according to newest convention`
74			`//`
75			`// Revision 1.2 2003/09/12 09:03:54 dries`
76			`// correct all the syntax errors`
77			`//`
78			`// Revision 1.1 2003/08/26 09:37:02 simons`
79			`// Added support for rams with byte write access.`
80			`//`
81			`//`
82
83			`// synopsys translate_off`
84			`include "timescale.v"
85			`// synopsys translate_on`
86			`include "or1200_defines.v"
87
88			`module or1200_spram_2048x32_bw(`
89			`ifdef OR1200_BIST
90			`// RAM BIST`
91			`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
92			`endif
93			`// Generic synchronous single-port RAM interface`
94			`clk, rst, ce, we, oe, addr, di, doq`
95			`);`
96
97			`ifdef OR1200_BIST
98			`//`
99			`// RAM BIST`
100			`//`
101			`input mbist_si_i;`
102			input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
103			`output mbist_so_o;`
104			`endif
105
106			`//`
107			`// Generic synchronous single-port RAM interface`
108			`//`
109			`input clk; // Clock`
110			`input rst; // Reset`
111			`input ce; // Chip enable input`
112			`input [3:0] we; // Write enable input`
113			`input oe; // Output enable input`
114			`input [10:0] addr; // address bus inputs`
115			`input [31:0] di; // input data bus`
116			`output [31:0] doq; // output data bus`
117
118			`//`
119			`// Internal wires and registers`
120			`//`
121
122			`ifdef OR1200_ARTISAN_SSP
123			`else
124			`ifdef OR1200_VIRTUALSILICON_SSP
125			`else
126			`ifdef OR1200_BIST
127			`assign mbist_so_o = mbist_si_i;`
128			`endif
129			`endif
130			`endif
131
132
133			`ifdef OR1200_ARTISAN_SSP
134
135			`//`
136			`// Instantiation of ASIC memory:`
137			`//`
138			`// Artisan Synchronous Single-Port RAM (ra1sh)`
139			`//`
140			`ifdef UNUSED
141			`art_hssp_2048x32_bw artisan_ssp(`
142			`else
143			`ifdef OR1200_BIST
144			`art_hssp_2048x32_bw_bist artisan_ssp(`
145			`else
146			`art_hssp_2048x32_bw artisan_ssp(`
147			`endif
148			`endif
149			`ifdef OR1200_BIST
150			`// RAM BIST`
151			`.mbist_si_i(mbist_si_i),`
152			`.mbist_so_o(mbist_so_o),`
153			`.mbist_ctrl_i(mbist_ctrl_i),`
154			`endif
155			`.CLK(clk),`
156			`.CEN(~ce),`
157			`.WEN(~we),`
158			`.A(addr),`
159			`.D(di),`
160			`.OEN(~oe),`
161			`.Q(doq)`
162			`);`
163
164			`else
165
166			`ifdef OR1200_AVANT_ATP
167
168			`//`
169			`// Instantiation of ASIC memory:`
170			`//`
171			`// Avant! Asynchronous Two-Port RAM`
172			`//`
173			`avant_atp avant_atp(`
174			`.web(~we),`
175			`.reb(),`
176			`.oeb(~oe),`
177			`.rcsb(),`
178			`.wcsb(),`
179			`.ra(addr),`
180			`.wa(addr),`
181			`.di(di),`
182			`.doq(doq)`
183			`);`
184
185			`else
186
187			`ifdef OR1200_VIRAGE_SSP
188
189			`//`
190			`// Instantiation of ASIC memory:`
191			`//`
192			`// Virage Synchronous 1-port R/W RAM`
193			`//`
194			`virage_ssp virage_ssp(`
195			`.clk(clk),`
196			`.adr(addr),`
197			`.d(di),`
198			`.we(we),`
199			`.oe(oe),`
200			`.me(ce),`
201			`.q(doq)`
202			`);`
203
204			`else
205
206			`ifdef OR1200_VIRTUALSILICON_SSP
207
208			`//`
209			`// Instantiation of ASIC memory:`
210			`//`
211			`// Virtual Silicon Single-Port Synchronous SRAM`
212			`//`
213			`ifdef OR1200_BIST
214			`wire mbist_si_i_ram_0;`
215			`wire mbist_si_i_ram_1;`
216			`wire mbist_si_i_ram_2;`
217			`wire mbist_si_i_ram_3;`
218			`wire mbist_so_o_ram_0;`
219			`wire mbist_so_o_ram_1;`
220			`wire mbist_so_o_ram_2;`
221			`wire mbist_so_o_ram_3;`
222			`assign mbist_si_i_ram_0 = mbist_si_i;`
223			`assign mbist_si_i_ram_1 = mbist_so_o_ram_0;`
224			`assign mbist_si_i_ram_2 = mbist_so_o_ram_1;`
225			`assign mbist_si_i_ram_3 = mbist_so_o_ram_2;`
226			`assign mbist_so_o = mbist_so_o_ram_3;`
227			`endif
228
229			`ifdef UNUSED
230			`vs_hdsp_2048x8 vs_ssp_0(`
231			`else
232			`ifdef OR1200_BIST
233			`vs_hdsp_2048x8_bist vs_ssp_0(`
234			`else
235			`vs_hdsp_2048x8 vs_ssp_0(`
236			`endif
237			`endif
238			`ifdef OR1200_BIST
239			`// RAM BIST`
240			`.mbist_si_i(mbist_si_i_ram_0),`
241			`.mbist_so_o(mbist_so_o_ram_0),`
242			`.mbist_ctrl_i(mbist_ctrl_i),`
243			`endif
244			`.CK(clk),`
245			`.ADR(addr),`
246			`.DI(di[7:0]),`
247			`.WEN(~we[0]),`
248			`.CEN(~ce),`
249			`.OEN(~oe),`
250			`.DOUT(doq[7:0])`
251			`);`
252
253			`ifdef UNUSED
254			`vs_hdsp_2048x8 vs_ssp_1(`
255			`else
256			`ifdef OR1200_BIST
257			`vs_hdsp_2048x8_bist vs_ssp_1(`
258			`else
259			`vs_hdsp_2048x8 vs_ssp_1(`
260			`endif
261			`endif
262			`ifdef OR1200_BIST
263			`// RAM BIST`
264			`.mbist_si_i(mbist_si_i_ram_1),`
265			`.mbist_so_o(mbist_so_o_ram_1),`
266			`.mbist_ctrl_i(mbist_ctrl_i),`
267			`endif
268			`.CK(clk),`
269			`.ADR(addr),`
270			`.DI(di[15:8]),`
271			`.WEN(~we[1]),`
272			`.CEN(~ce),`
273			`.OEN(~oe),`
274			`.DOUT(doq[15:8])`
275			`);`
276
277			`ifdef UNUSED
278			`vs_hdsp_2048x8 vs_ssp_2(`
279			`else
280			`ifdef OR1200_BIST
281			`vs_hdsp_2048x8_bist vs_ssp_2(`
282			`else
283			`vs_hdsp_2048x8 vs_ssp_2(`
284			`endif
285			`endif
286			`ifdef OR1200_BIST
287			`// RAM BIST`
288			`.mbist_si_i(mbist_si_i_ram_2),`
289			`.mbist_so_o(mbist_so_o_ram_2),`
290			`.mbist_ctrl_i(mbist_ctrl_i),`
291			`endif
292			`.CK(clk),`
293			`.ADR(addr),`
294			`.DI(di[23:16]),`
295			`.WEN(~we[2]),`
296			`.CEN(~ce),`
297			`.OEN(~oe),`
298			`.DOUT(doq[23:16])`
299			`);`
300
301			`ifdef UNUSED
302			`vs_hdsp_2048x8 vs_ssp_3(`
303			`else
304			`ifdef OR1200_BIST
305			`vs_hdsp_2048x8_bist vs_ssp_3(`
306			`else
307			`vs_hdsp_2048x8 vs_ssp_3(`
308			`endif
309			`endif
310			`ifdef OR1200_BIST
311			`// RAM BIST`
312			`.mbist_si_i(mbist_si_i_ram_3),`
313			`.mbist_so_o(mbist_so_o_ram_3),`
314			`.mbist_ctrl_i(mbist_ctrl_i),`
315			`endif
316			`.CK(clk),`
317			`.ADR(addr),`
318			`.DI(di[31:24]),`
319			`.WEN(~we[3]),`
320			`.CEN(~ce),`
321			`.OEN(~oe),`
322			`.DOUT(doq[31:24])`
323			`);`
324
325			`else
326
327			`ifdef OR1200_XILINX_RAMB4
328
329			`//`
330			`// Instantiation of FPGA memory:`
331			`//`
332			`// Virtex/Spartan2`
333			`//`
334
335			`//`
336			`// Block 0`
337			`//`
338			`RAMB4_S2 ramb4_s2_0(`
339			`.CLK(clk),`
340			`.RST(rst),`
341			`.ADDR(addr),`
342			`.DI(di[1:0]),`
343			`.EN(ce),`
344			`.WE(we[0]),`
345			`.DO(doq[1:0])`
346			`);`
347
348			`//`
349			`// Block 1`
350			`//`
351			`RAMB4_S2 ramb4_s2_1(`
352			`.CLK(clk),`
353			`.RST(rst),`
354			`.ADDR(addr),`
355			`.DI(di[3:2]),`
356			`.EN(ce),`
357			`.WE(we[0]),`
358			`.DO(doq[3:2])`
359			`);`
360
361			`//`
362			`// Block 2`
363			`//`
364			`RAMB4_S2 ramb4_s2_2(`
365			`.CLK(clk),`
366			`.RST(rst),`
367			`.ADDR(addr),`
368			`.DI(di[5:4]),`
369			`.EN(ce),`
370			`.WE(we[0]),`
371			`.DO(doq[5:4])`
372			`);`
373
374			`//`
375			`// Block 3`
376			`//`
377			`RAMB4_S2 ramb4_s2_3(`
378			`.CLK(clk),`
379			`.RST(rst),`
380			`.ADDR(addr),`
381			`.DI(di[7:6]),`
382			`.EN(ce),`
383			`.WE(we[0]),`
384			`.DO(doq[7:6])`
385			`);`
386			`//`
387			`// Block 4`
388			`//`
389			`RAMB4_S2 ramb4_s2_4(`
390			`.CLK(clk),`
391			`.RST(rst),`
392			`.ADDR(addr),`
393			`.DI(di[9:8]),`
394			`.EN(ce),`
395			`.WE(we[1]),`
396			`.DO(doq[9:8])`
397			`);`
398
399			`//`
400			`// Block 5`
401			`//`
402			`RAMB4_S2 ramb4_s2_5(`
403			`.CLK(clk),`
404			`.RST(rst),`
405			`.ADDR(addr),`
406			`.DI(di[11:10]),`
407			`.EN(ce),`
408			`.WE(we[1]),`
409			`.DO(doq[11:10])`
410			`);`
411
412			`//`
413			`// Block 6`
414			`//`
415			`RAMB4_S2 ramb4_s2_6(`
416			`.CLK(clk),`
417			`.RST(rst),`
418			`.ADDR(addr),`
419			`.DI(di[13:12]),`
420			`.EN(ce),`
421			`.WE(we[1]),`
422			`.DO(doq[13:12])`
423			`);`
424
425			`//`
426			`// Block 7`
427			`//`
428			`RAMB4_S2 ramb4_s2_7(`
429			`.CLK(clk),`
430			`.RST(rst),`
431			`.ADDR(addr),`
432			`.DI(di[15:14]),`
433			`.EN(ce),`
434			`.WE(we[1]),`
435			`.DO(doq[15:14])`
436			`);`
437			`//`
438			`// Block 8`
439			`//`
440			`RAMB4_S2 ramb4_s2_8(`
441			`.CLK(clk),`
442			`.RST(rst),`
443			`.ADDR(addr),`
444			`.DI(di[17:16]),`
445			`.EN(ce),`
446			`.WE(we[2]),`
447			`.DO(doq[17:16])`
448			`);`
449
450			`//`
451			`// Block 9`
452			`//`
453			`RAMB4_S2 ramb4_s2_9(`
454			`.CLK(clk),`
455			`.RST(rst),`
456			`.ADDR(addr),`
457			`.DI(di[19:18]),`
458			`.EN(ce),`
459			`.WE(we[2]),`
460			`.DO(doq[19:18])`
461			`);`
462
463			`//`
464			`// Block 10`
465			`//`
466			`RAMB4_S2 ramb4_s2_10(`
467			`.CLK(clk),`
468			`.RST(rst),`
469			`.ADDR(addr),`
470			`.DI(di[21:20]),`
471			`.EN(ce),`
472			`.WE(we[2]),`
473			`.DO(doq[21:20])`
474			`);`
475
476			`//`
477			`// Block 11`
478			`//`
479			`RAMB4_S2 ramb4_s2_11(`
480			`.CLK(clk),`
481			`.RST(rst),`
482			`.ADDR(addr),`
483			`.DI(di[23:22]),`
484			`.EN(ce),`
485			`.WE(we[2]),`
486			`.DO(doq[23:22])`
487			`);`
488			`//`
489			`// Block 12`
490			`//`
491			`RAMB4_S2 ramb4_s2_12(`
492			`.CLK(clk),`
493			`.RST(rst),`
494			`.ADDR(addr),`
495			`.DI(di[25:24]),`
496			`.EN(ce),`
497			`.WE(we[3]),`
498			`.DO(doq[25:24])`
499			`);`
500
501			`//`
502			`// Block 13`
503			`//`
504			`RAMB4_S2 ramb4_s2_13(`
505			`.CLK(clk),`
506			`.RST(rst),`
507			`.ADDR(addr),`
508			`.DI(di[27:26]),`
509			`.EN(ce),`
510			`.WE(we[3]),`
511			`.DO(doq[27:26])`
512			`);`
513
514			`//`
515			`// Block 14`
516			`//`
517			`RAMB4_S2 ramb4_s2_14(`
518			`.CLK(clk),`
519			`.RST(rst),`
520			`.ADDR(addr),`
521			`.DI(di[29:28]),`
522			`.EN(ce),`
523			`.WE(we[3]),`
524			`.DO(doq[29:28])`
525			`);`
526
527			`//`
528			`// Block 15`
529			`//`
530			`RAMB4_S2 ramb4_s2_15(`
531			`.CLK(clk),`
532			`.RST(rst),`
533			`.ADDR(addr),`
534			`.DI(di[31:30]),`
535			`.EN(ce),`
536			`.WE(we[3]),`
537			`.DO(doq[31:30])`
538			`);`
539
540			`else
541
542			`ifdef OR1200_XILINX_RAMB16
543
544			`//`
545			`// Instantiation of FPGA memory:`
546			`//`
547			`// Virtex4/Spartan3E`
548			`//`
549			`// Added By Nir Mor`
550			`//`
551
552			`//`
553			`// Block 0`
554			`//`
555			`RAMB16_S9 ramb16_s9_0(`
556			`.CLK(clk),`
557			`.SSR(rst),`
558			`.ADDR(addr),`
559			`.DI(di[7:0]),`
560			`.DIP(1'b0),`
561			`.EN(ce),`
562			`.WE(we[0]),`
563			`.DO(doq[7:0]),`
564			`.DOP()`
565			`);`
566
567			`//`
568			`// Block 1`
569			`//`
570			`RAMB16_S9 ramb16_s9_1(`
571			`.CLK(clk),`
572			`.SSR(rst),`
573			`.ADDR(addr),`
574			`.DI(di[15:8]),`
575			`.DIP(1'b0),`
576			`.EN(ce),`
577			`.WE(we[1]),`
578			`.DO(doq[15:8]),`
579			`.DOP()`
580			`);`
581
582			`//`
583			`// Block 2`
584			`//`
585			`RAMB16_S9 ramb16_s9_2(`
586			`.CLK(clk),`
587			`.SSR(rst),`
588			`.ADDR(addr),`
589			`.DI(di[23:16]),`
590			`.DIP(1'b0),`
591			`.EN(ce),`
592			`.WE(we[2]),`
593			`.DO(doq[23:16]),`
594			`.DOP()`
595			`);`
596
597			`//`
598			`// Block 3`
599			`//`
600			`RAMB16_S9 ramb16_s9_3(`
601			`.CLK(clk),`
602			`.SSR(rst),`
603			`.ADDR(addr),`
604			`.DI(di[31:24]),`
605			`.DIP(1'b0),`
606			`.EN(ce),`
607			`.WE(we[3]),`
608			`.DO(doq[31:24]),`
609			`.DOP()`
610			`);`
611
612			`else
613
614			`//`
615			`// Generic single-port synchronous RAM model`
616			`//`
617
618			`//`
619			`// Generic RAM's registers and wires`
620			`//`
621			`reg [7:0] mem_0 [2047:0]; // RAM content`
622			`reg [7:0] mem_1 [2047:0]; // RAM content`
623			`reg [7:0] mem_2 [2047:0]; // RAM content`
624			`reg [7:0] mem_3 [2047:0]; // RAM content`
625			`reg [10:0] addr_reg; // RAM address register`
626
627			`//`
628			`// Data output drivers`
629			`//`
630			`assign doq = (oe) ? {mem_3[addr_reg], mem_2[addr_reg], mem_1[addr_reg], mem_0[addr_reg]} : {32{1'b0}};`
631
632			`//`
633			`// RAM address register`
634			`//`
635			`always @(posedge clk or posedge rst)`
636			`if (rst)`
637			`addr_reg <= #1 11'h000;`
638			`else if (ce)`
639			`addr_reg <= #1 addr;`
640
641			`//`
642			`// RAM write byte 0`
643			`//`
644			`always @(posedge clk)`
645			`if (ce && we[0])`
646			`mem_0[addr] <= #1 di[7:0];`
647
648			`//`
649			`// RAM write byte 1`
650			`//`
651			`always @(posedge clk)`
652			`if (ce && we[1])`
653			`mem_1[addr] <= #1 di[15:8];`
654
655			`//`
656			`// RAM write byte 2`
657			`//`
658			`always @(posedge clk)`
659			`if (ce && we[2])`
660			`mem_2[addr] <= #1 di[23:16];`
661
662			`//`
663			`// RAM write byte 3`
664			`//`
665			`always @(posedge clk)`
666			`if (ce && we[3])`
667			`mem_3[addr] <= #1 di[31:24];`
668
669			`endif // !OR1200_XILINX_RAMB16
670			`endif // !OR1200_XILINX_RAMB4
671			`endif // !OR1200_VIRTUALSILICON_SSP
672			`endif // !OR1200_VIRAGE_SSP
673			`endif // !OR1200_AVANT_ATP
674			`endif // !OR1200_ARTISAN_SSP
675
676			`endmodule`