URL https://opencores.org/ocsvn/or1k_soc_on_altera_embedded_dev_kit/or1k_soc_on_altera_embedded_dev_kit/trunk

Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [or1200/] [rtl/] [verilog/] [or1200_spram_32x24.v] - Blame information for rev 12

Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Single-Port Synchronous RAM                         ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common single-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  single-port synchronous RAM.                                ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Single-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage Single-Port Sync RAM                               ////
////  - Virtual Silicon Single-Port Sync RAM                      ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB16                                      ////
////  - Xilinx Virtex RAMB4                                       ////
////  - Altera LPM                                                ////
////                                                              ////
////  To Do:                                                      ////
////   - xilinx rams need external tri-state logic                ////
////   - fix avant! two-port ram                                  ////
////   - add additional RAMs                                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_spram_32x24.v,v $
// Revision 1.3  2005/10/19 11:37:56  jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
// Revision 1.2  2004/06/08 18:15:32  lampret
// Changed behavior of the simulation generic models
//
// Revision 1.1  2004/04/08 11:00:46  simont
// Add support for 512B instruction cache.
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_spram_32x24(
`ifdef OR1200_BIST
        // RAM BIST
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
        // Generic synchronous single-port RAM interface
        clk, rst, ce, we, oe, addr, di, doq
);
 
//
// Default address and data buses width
//
parameter aw = 5;
parameter dw = 24;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
//
// Generic synchronous single-port RAM interface
//
input                   clk;    // Clock
input                   rst;    // Reset
input                   ce;     // Chip enable input
input                   we;     // Write enable input
input                   oe;     // Output enable input
input   [aw-1:0] addr;   // address bus inputs
input   [dw-1:0] di;     // input data bus
output  [dw-1:0] doq;    // output data bus
 
//
// Internal wires and registers
//
`ifdef OR1200_XILINX_RAMB4
wire [31:24] unconnected;
`else
`ifdef OR1200_XILINX_RAMB16
wire [31:24] unconnected;
`endif  // !OR1200_XILINX_RAMB16
`endif  // !OR1200_XILINX_RAMB4
 
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
`endif
`endif
`endif
 
`ifdef OR1200_ARTISAN_SSP
 
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
`else
`ifdef OR1200_BIST
`else
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
`endif
 
`else
 
`ifdef OR1200_AVANT_ATP
 
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
 
`else
 
`ifdef OR1200_VIRAGE_SSP
 
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
 
`else
 
`ifdef OR1200_VIRTUALSILICON_SSP
 
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
`else
`ifdef OR1200_BIST
`else
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
`endif
 
`else
 
`ifdef OR1200_XILINX_RAMB4
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
RAMB4_S16 ramb4_s16_0(
        .CLK(clk),
        .RST(rst),
        .ADDR({3'h0, addr}),
        .DI(di[15:0]),
        .EN(ce),
        .WE(we),
        .DO(doq[15:0])
);
 
//
// Block 1
//
RAMB4_S16 ramb4_s16_1(
        .CLK(clk),
        .RST(rst),
        .ADDR({3'h0, addr}),
        .DI({8'h00, di[23:16]}),
        .EN(ce),
        .WE(we),
        .DO({unconnected, doq[23:16]})
);
 
`else
 
`ifdef OR1200_XILINX_RAMB16
 
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
// Added By Nir Mor
//
 
RAMB16_S36 ramb16_s36(
        .CLK(clk),
        .SSR(rst),
        .ADDR({4'b0000, addr}),
        .DI({8'h00, di}),
        .DIP(4'h0),
        .EN(ce),
        .WE(we),
        .DO({unconnected, doq}),
        .DOP()
);
 
`else
 
`ifdef OR1200_ALTERA_LPM
 
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
 
 
`else
 
//
// Generic single-port synchronous RAM model
//
 
//
// Generic RAM's registers and wires
//
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
reg     [aw-1:0] addr_reg;               // RAM address register
 
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
 
//
// RAM address register
//
always @(posedge clk or posedge rst)
        if (rst)
                addr_reg <= #1 {aw{1'b0}};
        else if (ce)
                addr_reg <= #1 addr;
 
//
// RAM write
//
always @(posedge clk)
        if (ce && we)
                mem[addr] <= #1 di;
 
`endif  // !OR1200_ALTERA_LPM
`endif  // !OR1200_XILINX_RAMB16
`endif  // !OR1200_XILINX_RAMB4
`endif  // !OR1200_VIRTUALSILICON_SSP
`endif  // !OR1200_VIRAGE_SSP
`endif  // !OR1200_AVANT_ATP
`endif  // !OR1200_ARTISAN_SSP
 
endmodule

Browse

Tools

Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [or1200/] [rtl/] [verilog/] [or1200_spram_32x24.v] - Blame information for rev 12

Line No.	Rev	Author	Line
1	12	xianfeng	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Single-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common single-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// single-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// - Artisan Single-Port Sync RAM ////`
20			`//// - Avant! Two-Port Sync RAM (*) ////`
21			`//// - Virage Single-Port Sync RAM ////`
22			`//// - Virtual Silicon Single-Port Sync RAM ////`
23			`//// ////`
24			`//// Supported FPGA RAMs are: ////`
25			`//// - Xilinx Virtex RAMB16 ////`
26			`//// - Xilinx Virtex RAMB4 ////`
27			`//// - Altera LPM ////`
28			`//// ////`
29			`//// To Do: ////`
30			`//// - xilinx rams need external tri-state logic ////`
31			`//// - fix avant! two-port ram ////`
32			`//// - add additional RAMs ////`
33			`//// ////`
34			`//// Author(s): ////`
35			`//// - Damjan Lampret, lampret@opencores.org ////`
36			`//// ////`
37			`//////////////////////////////////////////////////////////////////////`
38			`//// ////`
39			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
40			`//// ////`
41			`//// This source file may be used and distributed without ////`
42			`//// restriction provided that this copyright statement is not ////`
43			`//// removed from the file and that any derivative work contains ////`
44			`//// the original copyright notice and the associated disclaimer. ////`
45			`//// ////`
46			`//// This source file is free software; you can redistribute it ////`
47			`//// and/or modify it under the terms of the GNU Lesser General ////`
48			`//// Public License as published by the Free Software Foundation; ////`
49			`//// either version 2.1 of the License, or (at your option) any ////`
50			`//// later version. ////`
51			`//// ////`
52			`//// This source is distributed in the hope that it will be ////`
53			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
54			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
55			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
56			`//// details. ////`
57			`//// ////`
58			`//// You should have received a copy of the GNU Lesser General ////`
59			`//// Public License along with this source; if not, download it ////`
60			`//// from http://www.opencores.org/lgpl.shtml ////`
61			`//// ////`
62			`//////////////////////////////////////////////////////////////////////`
63			`//`
64			`// CVS Revision History`
65			`//`
66			`// $Log: or1200_spram_32x24.v,v $`
67			`// Revision 1.3 2005/10/19 11:37:56 jcastillo`
68			`// Added support for RAMB16 Xilinx4/Spartan3 primitives`
69			`//`
70			`// Revision 1.2 2004/06/08 18:15:32 lampret`
71			`// Changed behavior of the simulation generic models`
72			`//`
73			`// Revision 1.1 2004/04/08 11:00:46 simont`
74			`// Add support for 512B instruction cache.`
75			`//`
76			`//`
77			`//`
78
79			`// synopsys translate_off`
80			`include "timescale.v"
81			`// synopsys translate_on`
82			`include "or1200_defines.v"
83
84			`module or1200_spram_32x24(`
85			`ifdef OR1200_BIST
86			`// RAM BIST`
87			`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
88			`endif
89			`// Generic synchronous single-port RAM interface`
90			`clk, rst, ce, we, oe, addr, di, doq`
91			`);`
92
93			`//`
94			`// Default address and data buses width`
95			`//`
96			`parameter aw = 5;`
97			`parameter dw = 24;`
98
99			`ifdef OR1200_BIST
100			`//`
101			`// RAM BIST`
102			`//`
103			`input mbist_si_i;`
104			input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
105			`output mbist_so_o;`
106			`endif
107
108			`//`
109			`// Generic synchronous single-port RAM interface`
110			`//`
111			`input clk; // Clock`
112			`input rst; // Reset`
113			`input ce; // Chip enable input`
114			`input we; // Write enable input`
115			`input oe; // Output enable input`
116			`input [aw-1:0] addr; // address bus inputs`
117			`input [dw-1:0] di; // input data bus`
118			`output [dw-1:0] doq; // output data bus`
119
120			`//`
121			`// Internal wires and registers`
122			`//`
123			`ifdef OR1200_XILINX_RAMB4
124			`wire [31:24] unconnected;`
125			`else
126			`ifdef OR1200_XILINX_RAMB16
127			`wire [31:24] unconnected;`
128			`endif // !OR1200_XILINX_RAMB16
129			`endif // !OR1200_XILINX_RAMB4
130
131			`ifdef OR1200_ARTISAN_SSP
132			`else
133			`ifdef OR1200_VIRTUALSILICON_SSP
134			`else
135			`ifdef OR1200_BIST
136			`endif
137			`endif
138			`endif
139
140			`ifdef OR1200_ARTISAN_SSP
141
142			`//`
143			`// Instantiation of ASIC memory:`
144			`//`
145			`// Artisan Synchronous Single-Port RAM (ra1sh)`
146			`//`
147			`ifdef UNUSED
148			`else
149			`ifdef OR1200_BIST
150			`else
151			`endif
152			`endif
153			`ifdef OR1200_BIST
154			`// RAM BIST`
155			`endif
156
157			`else
158
159			`ifdef OR1200_AVANT_ATP
160
161			`//`
162			`// Instantiation of ASIC memory:`
163			`//`
164			`// Avant! Asynchronous Two-Port RAM`
165			`//`
166
167			`else
168
169			`ifdef OR1200_VIRAGE_SSP
170
171			`//`
172			`// Instantiation of ASIC memory:`
173			`//`
174			`// Virage Synchronous 1-port R/W RAM`
175			`//`
176
177			`else
178
179			`ifdef OR1200_VIRTUALSILICON_SSP
180
181			`//`
182			`// Instantiation of ASIC memory:`
183			`//`
184			`// Virtual Silicon Single-Port Synchronous SRAM`
185			`//`
186			`ifdef UNUSED
187			`else
188			`ifdef OR1200_BIST
189			`else
190			`endif
191			`endif
192			`ifdef OR1200_BIST
193			`// RAM BIST`
194			`endif
195
196			`else
197
198			`ifdef OR1200_XILINX_RAMB4
199
200			`//`
201			`// Instantiation of FPGA memory:`
202			`//`
203			`// Virtex/Spartan2`
204			`//`
205
206			`//`
207			`// Block 0`
208			`//`
209			`RAMB4_S16 ramb4_s16_0(`
210			`.CLK(clk),`
211			`.RST(rst),`
212			`.ADDR({3'h0, addr}),`
213			`.DI(di[15:0]),`
214			`.EN(ce),`
215			`.WE(we),`
216			`.DO(doq[15:0])`
217			`);`
218
219			`//`
220			`// Block 1`
221			`//`
222			`RAMB4_S16 ramb4_s16_1(`
223			`.CLK(clk),`
224			`.RST(rst),`
225			`.ADDR({3'h0, addr}),`
226			`.DI({8'h00, di[23:16]}),`
227			`.EN(ce),`
228			`.WE(we),`
229			`.DO({unconnected, doq[23:16]})`
230			`);`
231
232			`else
233
234			`ifdef OR1200_XILINX_RAMB16
235
236			`//`
237			`// Instantiation of FPGA memory:`
238			`//`
239			`// Virtex4/Spartan3E`
240			`//`
241			`// Added By Nir Mor`
242			`//`
243
244			`RAMB16_S36 ramb16_s36(`
245			`.CLK(clk),`
246			`.SSR(rst),`
247			`.ADDR({4'b0000, addr}),`
248			`.DI({8'h00, di}),`
249			`.DIP(4'h0),`
250			`.EN(ce),`
251			`.WE(we),`
252			`.DO({unconnected, doq}),`
253			`.DOP()`
254			`);`
255
256			`else
257
258			`ifdef OR1200_ALTERA_LPM
259
260			`//`
261			`// Instantiation of FPGA memory:`
262			`//`
263			`// Altera LPM`
264			`//`
265			`// Added By Jamil Khatib`
266			`//`
267
268
269			`else
270
271			`//`
272			`// Generic single-port synchronous RAM model`
273			`//`
274
275			`//`
276			`// Generic RAM's registers and wires`
277			`//`
278			`reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content`
279			`reg [aw-1:0] addr_reg; // RAM address register`
280
281			`//`
282			`// Data output drivers`
283			`//`
284			`assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};`
285
286			`//`
287			`// RAM address register`
288			`//`
289			`always @(posedge clk or posedge rst)`
290			`if (rst)`
291			`addr_reg <= #1 {aw{1'b0}};`
292			`else if (ce)`
293			`addr_reg <= #1 addr;`
294
295			`//`
296			`// RAM write`
297			`//`
298			`always @(posedge clk)`
299			`if (ce && we)`
300			`mem[addr] <= #1 di;`
301
302			`endif // !OR1200_ALTERA_LPM
303			`endif // !OR1200_XILINX_RAMB16
304			`endif // !OR1200_XILINX_RAMB4
305			`endif // !OR1200_VIRTUALSILICON_SSP
306			`endif // !OR1200_VIRAGE_SSP
307			`endif // !OR1200_AVANT_ATP
308			`endif // !OR1200_ARTISAN_SSP
309
310			`endmodule`