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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [or1200/] [rtl/] [verilog/] [or1200_xcv_ram32x8d.v] - Blame information for rev 12

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Xilinx Virtex RAM 32x8D                                     ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Virtex dual-port memory                                     ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_xcv_ram32x8d.v,v $
// Revision 1.2  2002/07/14 22:17:17  lampret
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.7  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6  2001/10/14 13:12:10  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
`ifdef OR1200_XILINX_RAM32X1D
`ifdef OR1200_USE_RAM16X1D_FOR_RAM32X1D
module or1200_xcv_ram32x8d
(
    DPO,
    SPO,
    A,
    D,
    DPRA,
    WCLK,
    WE
);
output  [7:0]   DPO;
output  [7:0]   SPO;
input   [4:0]   A;
input   [4:0]   DPRA;
input   [7:0]   D;
input           WCLK;
input           WE;
 
wire    [7:0]   DPO_0;
wire    [7:0]   SPO_0;
 
wire    [7:0]   DPO_1;
wire    [7:0]   SPO_1;
 
wire            WE_0 ;
wire            WE_1 ;
 
assign DPO = DPRA[4] ? DPO_1 : DPO_0 ;
assign SPO = A[4] ? SPO_1 : SPO_0 ;
 
assign WE_0 = !A[4] && WE ;
assign WE_1 =  A[4] && WE ;
 
RAM16X1D ram32x1d_0_0(
        .DPO(DPO_0[0]),
        .SPO(SPO_0[0]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[0]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_0)
);
 
//
// Instantiation of block 1
//
RAM16X1D ram32x1d_0_1(
        .DPO(DPO_0[1]),
        .SPO(SPO_0[1]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[1]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_0)
);
 
//
// Instantiation of block 2
//
RAM16X1D ram32x1d_0_2(
        .DPO(DPO_0[2]),
        .SPO(SPO_0[2]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[2]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_0)
);
 
//
// Instantiation of block 3
//
RAM16X1D ram32x1d_0_3(
        .DPO(DPO_0[3]),
        .SPO(SPO_0[3]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[3]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_0)
);
 
//
// Instantiation of block 4
//
RAM16X1D ram32x1d_0_4(
        .DPO(DPO_0[4]),
        .SPO(SPO_0[4]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[4]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_0)
);
 
//
// Instantiation of block 5
//
RAM16X1D ram32x1d_0_5(
        .DPO(DPO_0[5]),
        .SPO(SPO_0[5]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[5]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_0)
);
 
//
// Instantiation of block 6
//
RAM16X1D ram32x1d_0_6(
        .DPO(DPO_0[6]),
        .SPO(SPO_0[6]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[6]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_0)
);
 
//
// Instantiation of block 7
//
RAM16X1D ram32x1d_0_7(
        .DPO(DPO_0[7]),
        .SPO(SPO_0[7]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[7]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_0)
);
 
RAM16X1D ram32x1d_1_0(
        .DPO(DPO_1[0]),
        .SPO(SPO_1[0]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[0]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_1)
);
 
//
// Instantiation of block 1
//
RAM16X1D ram32x1d_1_1(
        .DPO(DPO_1[1]),
        .SPO(SPO_1[1]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[1]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_1)
);
 
//
// Instantiation of block 2
//
RAM16X1D ram32x1d_1_2(
        .DPO(DPO_1[2]),
        .SPO(SPO_1[2]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[2]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_1)
);
 
//
// Instantiation of block 3
//
RAM16X1D ram32x1d_1_3(
        .DPO(DPO_1[3]),
        .SPO(SPO_1[3]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[3]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_1)
);
 
//
// Instantiation of block 4
//
RAM16X1D ram32x1d_1_4(
        .DPO(DPO_1[4]),
        .SPO(SPO_1[4]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[4]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_1)
);
 
//
// Instantiation of block 5
//
RAM16X1D ram32x1d_1_5(
        .DPO(DPO_1[5]),
        .SPO(SPO_1[5]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[5]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_1)
);
 
//
// Instantiation of block 6
//
RAM16X1D ram32x1d_1_6(
        .DPO(DPO_1[6]),
        .SPO(SPO_1[6]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[6]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_1)
);
 
//
// Instantiation of block 7
//
RAM16X1D ram32x1d_1_7(
        .DPO(DPO_1[7]),
        .SPO(SPO_1[7]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[7]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_1)
);
endmodule
 
`else
 
module or1200_xcv_ram32x8d (DPO, SPO, A, D, DPRA, WCLK, WE);
 
//
// I/O
//
output [7:0]     DPO;
output [7:0]     SPO;
input [4:0]      A;
input [4:0]      DPRA;
input [7:0]      D;
input           WCLK;
input           WE;
 
//
// Instantiation of block 0
//
RAM32X1D ram32x1d_0(
        .DPO(DPO[0]),
        .SPO(SPO[0]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[0]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 1
//
RAM32X1D ram32x1d_1(
        .DPO(DPO[1]),
        .SPO(SPO[1]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[1]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 2
//
RAM32X1D ram32x1d_2(
        .DPO(DPO[2]),
        .SPO(SPO[2]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[2]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 3
//
RAM32X1D ram32x1d_3(
        .DPO(DPO[3]),
        .SPO(SPO[3]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[3]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 4
//
RAM32X1D ram32x1d_4(
        .DPO(DPO[4]),
        .SPO(SPO[4]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[4]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 5
//
RAM32X1D ram32x1d_5(
        .DPO(DPO[5]),
        .SPO(SPO[5]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[5]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 6
//
RAM32X1D ram32x1d_6(
        .DPO(DPO[6]),
        .SPO(SPO[6]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[6]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 7
//
RAM32X1D ram32x1d_7(
        .DPO(DPO[7]),
        .SPO(SPO[7]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[7]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
endmodule
`endif
`endif

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Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [or1200/] [rtl/] [verilog/] [or1200_xcv_ram32x8d.v] - Blame information for rev 12

Line No.	Rev	Author	Line
1	12	xianfeng	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Xilinx Virtex RAM 32x8D ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Virtex dual-port memory ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: or1200_xcv_ram32x8d.v,v $`
47			`// Revision 1.2 2002/07/14 22:17:17 lampret`
48			`// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.`
49			`//`
50			`// Revision 1.1 2002/01/03 08:16:15 lampret`
51			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
52			`//`
53			`// Revision 1.7 2001/10/21 17:57:16 lampret`
54			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
55			`//`
56			`// Revision 1.6 2001/10/14 13:12:10 lampret`
57			`// MP3 version.`
58			`//`
59			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
60			`// no message`
61			`//`
62			`// Revision 1.1 2001/08/09 13:39:33 lampret`
63			`// Major clean-up.`
64			`//`
65			`//`
66
67			`// synopsys translate_off`
68			`include "timescale.v"
69			`// synopsys translate_on`
70			`include "or1200_defines.v"
71
72			`ifdef OR1200_XILINX_RAM32X1D
73			`ifdef OR1200_USE_RAM16X1D_FOR_RAM32X1D
74			`module or1200_xcv_ram32x8d`
75			`(`
76			`DPO,`
77			`SPO,`
78			`A,`
79			`D,`
80			`DPRA,`
81			`WCLK,`
82			`WE`
83			`);`
84			`output [7:0] DPO;`
85			`output [7:0] SPO;`
86			`input [4:0] A;`
87			`input [4:0] DPRA;`
88			`input [7:0] D;`
89			`input WCLK;`
90			`input WE;`
91
92			`wire [7:0] DPO_0;`
93			`wire [7:0] SPO_0;`
94
95			`wire [7:0] DPO_1;`
96			`wire [7:0] SPO_1;`
97
98			`wire WE_0 ;`
99			`wire WE_1 ;`
100
101			`assign DPO = DPRA[4] ? DPO_1 : DPO_0 ;`
102			`assign SPO = A[4] ? SPO_1 : SPO_0 ;`
103
104			`assign WE_0 = !A[4] && WE ;`
105			`assign WE_1 = A[4] && WE ;`
106
107			`RAM16X1D ram32x1d_0_0(`
108			`.DPO(DPO_0[0]),`
109			`.SPO(SPO_0[0]),`
110			`.A0(A[0]),`
111			`.A1(A[1]),`
112			`.A2(A[2]),`
113			`.A3(A[3]),`
114			`.D(D[0]),`
115			`.DPRA0(DPRA[0]),`
116			`.DPRA1(DPRA[1]),`
117			`.DPRA2(DPRA[2]),`
118			`.DPRA3(DPRA[3]),`
119			`.WCLK(WCLK),`
120			`.WE(WE_0)`
121			`);`
122
123			`//`
124			`// Instantiation of block 1`
125			`//`
126			`RAM16X1D ram32x1d_0_1(`
127			`.DPO(DPO_0[1]),`
128			`.SPO(SPO_0[1]),`
129			`.A0(A[0]),`
130			`.A1(A[1]),`
131			`.A2(A[2]),`
132			`.A3(A[3]),`
133			`.D(D[1]),`
134			`.DPRA0(DPRA[0]),`
135			`.DPRA1(DPRA[1]),`
136			`.DPRA2(DPRA[2]),`
137			`.DPRA3(DPRA[3]),`
138			`.WCLK(WCLK),`
139			`.WE(WE_0)`
140			`);`
141
142			`//`
143			`// Instantiation of block 2`
144			`//`
145			`RAM16X1D ram32x1d_0_2(`
146			`.DPO(DPO_0[2]),`
147			`.SPO(SPO_0[2]),`
148			`.A0(A[0]),`
149			`.A1(A[1]),`
150			`.A2(A[2]),`
151			`.A3(A[3]),`
152			`.D(D[2]),`
153			`.DPRA0(DPRA[0]),`
154			`.DPRA1(DPRA[1]),`
155			`.DPRA2(DPRA[2]),`
156			`.DPRA3(DPRA[3]),`
157			`.WCLK(WCLK),`
158			`.WE(WE_0)`
159			`);`
160
161			`//`
162			`// Instantiation of block 3`
163			`//`
164			`RAM16X1D ram32x1d_0_3(`
165			`.DPO(DPO_0[3]),`
166			`.SPO(SPO_0[3]),`
167			`.A0(A[0]),`
168			`.A1(A[1]),`
169			`.A2(A[2]),`
170			`.A3(A[3]),`
171			`.D(D[3]),`
172			`.DPRA0(DPRA[0]),`
173			`.DPRA1(DPRA[1]),`
174			`.DPRA2(DPRA[2]),`
175			`.DPRA3(DPRA[3]),`
176			`.WCLK(WCLK),`
177			`.WE(WE_0)`
178			`);`
179
180			`//`
181			`// Instantiation of block 4`
182			`//`
183			`RAM16X1D ram32x1d_0_4(`
184			`.DPO(DPO_0[4]),`
185			`.SPO(SPO_0[4]),`
186			`.A0(A[0]),`
187			`.A1(A[1]),`
188			`.A2(A[2]),`
189			`.A3(A[3]),`
190			`.D(D[4]),`
191			`.DPRA0(DPRA[0]),`
192			`.DPRA1(DPRA[1]),`
193			`.DPRA2(DPRA[2]),`
194			`.DPRA3(DPRA[3]),`
195			`.WCLK(WCLK),`
196			`.WE(WE_0)`
197			`);`
198
199			`//`
200			`// Instantiation of block 5`
201			`//`
202			`RAM16X1D ram32x1d_0_5(`
203			`.DPO(DPO_0[5]),`
204			`.SPO(SPO_0[5]),`
205			`.A0(A[0]),`
206			`.A1(A[1]),`
207			`.A2(A[2]),`
208			`.A3(A[3]),`
209			`.D(D[5]),`
210			`.DPRA0(DPRA[0]),`
211			`.DPRA1(DPRA[1]),`
212			`.DPRA2(DPRA[2]),`
213			`.DPRA3(DPRA[3]),`
214			`.WCLK(WCLK),`
215			`.WE(WE_0)`
216			`);`
217
218			`//`
219			`// Instantiation of block 6`
220			`//`
221			`RAM16X1D ram32x1d_0_6(`
222			`.DPO(DPO_0[6]),`
223			`.SPO(SPO_0[6]),`
224			`.A0(A[0]),`
225			`.A1(A[1]),`
226			`.A2(A[2]),`
227			`.A3(A[3]),`
228			`.D(D[6]),`
229			`.DPRA0(DPRA[0]),`
230			`.DPRA1(DPRA[1]),`
231			`.DPRA2(DPRA[2]),`
232			`.DPRA3(DPRA[3]),`
233			`.WCLK(WCLK),`
234			`.WE(WE_0)`
235			`);`
236
237			`//`
238			`// Instantiation of block 7`
239			`//`
240			`RAM16X1D ram32x1d_0_7(`
241			`.DPO(DPO_0[7]),`
242			`.SPO(SPO_0[7]),`
243			`.A0(A[0]),`
244			`.A1(A[1]),`
245			`.A2(A[2]),`
246			`.A3(A[3]),`
247			`.D(D[7]),`
248			`.DPRA0(DPRA[0]),`
249			`.DPRA1(DPRA[1]),`
250			`.DPRA2(DPRA[2]),`
251			`.DPRA3(DPRA[3]),`
252			`.WCLK(WCLK),`
253			`.WE(WE_0)`
254			`);`
255
256			`RAM16X1D ram32x1d_1_0(`
257			`.DPO(DPO_1[0]),`
258			`.SPO(SPO_1[0]),`
259			`.A0(A[0]),`
260			`.A1(A[1]),`
261			`.A2(A[2]),`
262			`.A3(A[3]),`
263			`.D(D[0]),`
264			`.DPRA0(DPRA[0]),`
265			`.DPRA1(DPRA[1]),`
266			`.DPRA2(DPRA[2]),`
267			`.DPRA3(DPRA[3]),`
268			`.WCLK(WCLK),`
269			`.WE(WE_1)`
270			`);`
271
272			`//`
273			`// Instantiation of block 1`
274			`//`
275			`RAM16X1D ram32x1d_1_1(`
276			`.DPO(DPO_1[1]),`
277			`.SPO(SPO_1[1]),`
278			`.A0(A[0]),`
279			`.A1(A[1]),`
280			`.A2(A[2]),`
281			`.A3(A[3]),`
282			`.D(D[1]),`
283			`.DPRA0(DPRA[0]),`
284			`.DPRA1(DPRA[1]),`
285			`.DPRA2(DPRA[2]),`
286			`.DPRA3(DPRA[3]),`
287			`.WCLK(WCLK),`
288			`.WE(WE_1)`
289			`);`
290
291			`//`
292			`// Instantiation of block 2`
293			`//`
294			`RAM16X1D ram32x1d_1_2(`
295			`.DPO(DPO_1[2]),`
296			`.SPO(SPO_1[2]),`
297			`.A0(A[0]),`
298			`.A1(A[1]),`
299			`.A2(A[2]),`
300			`.A3(A[3]),`
301			`.D(D[2]),`
302			`.DPRA0(DPRA[0]),`
303			`.DPRA1(DPRA[1]),`
304			`.DPRA2(DPRA[2]),`
305			`.DPRA3(DPRA[3]),`
306			`.WCLK(WCLK),`
307			`.WE(WE_1)`
308			`);`
309
310			`//`
311			`// Instantiation of block 3`
312			`//`
313			`RAM16X1D ram32x1d_1_3(`
314			`.DPO(DPO_1[3]),`
315			`.SPO(SPO_1[3]),`
316			`.A0(A[0]),`
317			`.A1(A[1]),`
318			`.A2(A[2]),`
319			`.A3(A[3]),`
320			`.D(D[3]),`
321			`.DPRA0(DPRA[0]),`
322			`.DPRA1(DPRA[1]),`
323			`.DPRA2(DPRA[2]),`
324			`.DPRA3(DPRA[3]),`
325			`.WCLK(WCLK),`
326			`.WE(WE_1)`
327			`);`
328
329			`//`
330			`// Instantiation of block 4`
331			`//`
332			`RAM16X1D ram32x1d_1_4(`
333			`.DPO(DPO_1[4]),`
334			`.SPO(SPO_1[4]),`
335			`.A0(A[0]),`
336			`.A1(A[1]),`
337			`.A2(A[2]),`
338			`.A3(A[3]),`
339			`.D(D[4]),`
340			`.DPRA0(DPRA[0]),`
341			`.DPRA1(DPRA[1]),`
342			`.DPRA2(DPRA[2]),`
343			`.DPRA3(DPRA[3]),`
344			`.WCLK(WCLK),`
345			`.WE(WE_1)`
346			`);`
347
348			`//`
349			`// Instantiation of block 5`
350			`//`
351			`RAM16X1D ram32x1d_1_5(`
352			`.DPO(DPO_1[5]),`
353			`.SPO(SPO_1[5]),`
354			`.A0(A[0]),`
355			`.A1(A[1]),`
356			`.A2(A[2]),`
357			`.A3(A[3]),`
358			`.D(D[5]),`
359			`.DPRA0(DPRA[0]),`
360			`.DPRA1(DPRA[1]),`
361			`.DPRA2(DPRA[2]),`
362			`.DPRA3(DPRA[3]),`
363			`.WCLK(WCLK),`
364			`.WE(WE_1)`
365			`);`
366
367			`//`
368			`// Instantiation of block 6`
369			`//`
370			`RAM16X1D ram32x1d_1_6(`
371			`.DPO(DPO_1[6]),`
372			`.SPO(SPO_1[6]),`
373			`.A0(A[0]),`
374			`.A1(A[1]),`
375			`.A2(A[2]),`
376			`.A3(A[3]),`
377			`.D(D[6]),`
378			`.DPRA0(DPRA[0]),`
379			`.DPRA1(DPRA[1]),`
380			`.DPRA2(DPRA[2]),`
381			`.DPRA3(DPRA[3]),`
382			`.WCLK(WCLK),`
383			`.WE(WE_1)`
384			`);`
385
386			`//`
387			`// Instantiation of block 7`
388			`//`
389			`RAM16X1D ram32x1d_1_7(`
390			`.DPO(DPO_1[7]),`
391			`.SPO(SPO_1[7]),`
392			`.A0(A[0]),`
393			`.A1(A[1]),`
394			`.A2(A[2]),`
395			`.A3(A[3]),`
396			`.D(D[7]),`
397			`.DPRA0(DPRA[0]),`
398			`.DPRA1(DPRA[1]),`
399			`.DPRA2(DPRA[2]),`
400			`.DPRA3(DPRA[3]),`
401			`.WCLK(WCLK),`
402			`.WE(WE_1)`
403			`);`
404			`endmodule`
405
406			`else
407
408			`module or1200_xcv_ram32x8d (DPO, SPO, A, D, DPRA, WCLK, WE);`
409
410			`//`
411			`// I/O`
412			`//`
413			`output [7:0] DPO;`
414			`output [7:0] SPO;`
415			`input [4:0] A;`
416			`input [4:0] DPRA;`
417			`input [7:0] D;`
418			`input WCLK;`
419			`input WE;`
420
421			`//`
422			`// Instantiation of block 0`
423			`//`
424			`RAM32X1D ram32x1d_0(`
425			`.DPO(DPO[0]),`
426			`.SPO(SPO[0]),`
427			`.A0(A[0]),`
428			`.A1(A[1]),`
429			`.A2(A[2]),`
430			`.A3(A[3]),`
431			`.A4(A[4]),`
432			`.D(D[0]),`
433			`.DPRA0(DPRA[0]),`
434			`.DPRA1(DPRA[1]),`
435			`.DPRA2(DPRA[2]),`
436			`.DPRA3(DPRA[3]),`
437			`.DPRA4(DPRA[4]),`
438			`.WCLK(WCLK),`
439			`.WE(WE)`
440			`);`
441
442			`//`
443			`// Instantiation of block 1`
444			`//`
445			`RAM32X1D ram32x1d_1(`
446			`.DPO(DPO[1]),`
447			`.SPO(SPO[1]),`
448			`.A0(A[0]),`
449			`.A1(A[1]),`
450			`.A2(A[2]),`
451			`.A3(A[3]),`
452			`.A4(A[4]),`
453			`.D(D[1]),`
454			`.DPRA0(DPRA[0]),`
455			`.DPRA1(DPRA[1]),`
456			`.DPRA2(DPRA[2]),`
457			`.DPRA3(DPRA[3]),`
458			`.DPRA4(DPRA[4]),`
459			`.WCLK(WCLK),`
460			`.WE(WE)`
461			`);`
462
463			`//`
464			`// Instantiation of block 2`
465			`//`
466			`RAM32X1D ram32x1d_2(`
467			`.DPO(DPO[2]),`
468			`.SPO(SPO[2]),`
469			`.A0(A[0]),`
470			`.A1(A[1]),`
471			`.A2(A[2]),`
472			`.A3(A[3]),`
473			`.A4(A[4]),`
474			`.D(D[2]),`
475			`.DPRA0(DPRA[0]),`
476			`.DPRA1(DPRA[1]),`
477			`.DPRA2(DPRA[2]),`
478			`.DPRA3(DPRA[3]),`
479			`.DPRA4(DPRA[4]),`
480			`.WCLK(WCLK),`
481			`.WE(WE)`
482			`);`
483
484			`//`
485			`// Instantiation of block 3`
486			`//`
487			`RAM32X1D ram32x1d_3(`
488			`.DPO(DPO[3]),`
489			`.SPO(SPO[3]),`
490			`.A0(A[0]),`
491			`.A1(A[1]),`
492			`.A2(A[2]),`
493			`.A3(A[3]),`
494			`.A4(A[4]),`
495			`.D(D[3]),`
496			`.DPRA0(DPRA[0]),`
497			`.DPRA1(DPRA[1]),`
498			`.DPRA2(DPRA[2]),`
499			`.DPRA3(DPRA[3]),`
500			`.DPRA4(DPRA[4]),`
501			`.WCLK(WCLK),`
502			`.WE(WE)`
503			`);`
504
505			`//`
506			`// Instantiation of block 4`
507			`//`
508			`RAM32X1D ram32x1d_4(`
509			`.DPO(DPO[4]),`
510			`.SPO(SPO[4]),`
511			`.A0(A[0]),`
512			`.A1(A[1]),`
513			`.A2(A[2]),`
514			`.A3(A[3]),`
515			`.A4(A[4]),`
516			`.D(D[4]),`
517			`.DPRA0(DPRA[0]),`
518			`.DPRA1(DPRA[1]),`
519			`.DPRA2(DPRA[2]),`
520			`.DPRA3(DPRA[3]),`
521			`.DPRA4(DPRA[4]),`
522			`.WCLK(WCLK),`
523			`.WE(WE)`
524			`);`
525
526			`//`
527			`// Instantiation of block 5`
528			`//`
529			`RAM32X1D ram32x1d_5(`
530			`.DPO(DPO[5]),`
531			`.SPO(SPO[5]),`
532			`.A0(A[0]),`
533			`.A1(A[1]),`
534			`.A2(A[2]),`
535			`.A3(A[3]),`
536			`.A4(A[4]),`
537			`.D(D[5]),`
538			`.DPRA0(DPRA[0]),`
539			`.DPRA1(DPRA[1]),`
540			`.DPRA2(DPRA[2]),`
541			`.DPRA3(DPRA[3]),`
542			`.DPRA4(DPRA[4]),`
543			`.WCLK(WCLK),`
544			`.WE(WE)`
545			`);`
546
547			`//`
548			`// Instantiation of block 6`
549			`//`
550			`RAM32X1D ram32x1d_6(`
551			`.DPO(DPO[6]),`
552			`.SPO(SPO[6]),`
553			`.A0(A[0]),`
554			`.A1(A[1]),`
555			`.A2(A[2]),`
556			`.A3(A[3]),`
557			`.A4(A[4]),`
558			`.D(D[6]),`
559			`.DPRA0(DPRA[0]),`
560			`.DPRA1(DPRA[1]),`
561			`.DPRA2(DPRA[2]),`
562			`.DPRA3(DPRA[3]),`
563			`.DPRA4(DPRA[4]),`
564			`.WCLK(WCLK),`
565			`.WE(WE)`
566			`);`
567
568			`//`
569			`// Instantiation of block 7`
570			`//`
571			`RAM32X1D ram32x1d_7(`
572			`.DPO(DPO[7]),`
573			`.SPO(SPO[7]),`
574			`.A0(A[0]),`
575			`.A1(A[1]),`
576			`.A2(A[2]),`
577			`.A3(A[3]),`
578			`.A4(A[4]),`
579			`.D(D[7]),`
580			`.DPRA0(DPRA[0]),`
581			`.DPRA1(DPRA[1]),`
582			`.DPRA2(DPRA[2]),`
583			`.DPRA3(DPRA[3]),`
584			`.DPRA4(DPRA[4]),`
585			`.WCLK(WCLK),`
586			`.WE(WE)`
587			`);`
588
589			`endmodule`
590			`endif
591			`endif