URL https://opencores.org/ocsvn/or1k_soc_on_altera_embedded_dev_kit/or1k_soc_on_altera_embedded_dev_kit/trunk

Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [or1k_soc_defines.v] - Blame information for rev 12

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//
// Interrupts
//
`define APP_INT_RES1    1:0
`define APP_INT_UART    2
`define APP_INT_GPIO    3
`define APP_INT_ETH     4
`define APP_INT_SPI0    5
`define APP_INT_RES3    19:6
 
//`define SRAM_GENERIC
`define CONFIG_USE_SRAM

Line No.	Rev	Author	Line
1	12	xianfeng	`//`
2			`// Interrupts`
3			`//`
4			`define APP_INT_RES1 1:0
5			`define APP_INT_UART 2
6			`define APP_INT_GPIO 3
7			`define APP_INT_ETH 4
8			`define APP_INT_SPI0 5
9			`define APP_INT_RES3 19:6
10
11			//`define SRAM_GENERIC
12			`define CONFIG_USE_SRAM

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Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [or1k_soc_defines.v] - Blame information for rev 12