Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

//===============================================================================

//

//          FILE:  or1k_sco_top.v

// 

//         USAGE:  ./or1k_sco_top.v 

// 

//   DESCRIPTION:  Top of the soc

// 

//       OPTIONS:  ---

//  REQUIREMENTS:  ---

//          BUGS:  ---

//         NOTES:  ---

//        AUTHOR:  Xianfeng Zeng (ZXF), xianfeng.zeng@gmail.com

//                                      Xianfeng.zeng@SierraAtlantic.com

//       COMPANY:  

//       VERSION:  1.0

//       CREATED:  04/05/2009 12:59:12 PM HKT

//      REVISION:  ---

//===============================================================================

// synopsys translate_off

// `include "timescale.v"

// synopsys translate_on

`include "or1200/rtl/verilog/or1200_defines.v"

`include "or1k_soc_defines.v"

module or1k_soc_top(

        // CLK and RESET

        wb_clk_pad_i,           // 50 MHz to pll for cpu and other logic

        ddr_pll_clk_pad_i,      // 50 Mhz to ddr core

        rst_n_pad_i,            // to ddr core that will generate out globle reset

/*

        // Flash chip

        flash_rstn, flash_cen, flash_oen, flash_wen,

        flash_rdy, flash_d, flash_a, flash_clk_pad_i,

        // SDRAM

        mc_clk_pad_i,

        mem_dat_pad_io,

        mem_adr_pad_o,

        mem_dqm_pad_o,

        mem_ba_pad_o,

        mem_cs_pad_o,

        mem_ras_pad_o,

        mem_cas_pad_o,

        mem_we_pad_o,

        mem_cke_pad_o,

*/

        //DDR SDRAM

        ddr_mem_cs_n_o,

        ddr_mem_cke_o,

        ddr_mem_addr_o,

        ddr_mem_ba_o,

        ddr_mem_ras_n_o,

        ddr_mem_cas_n_o,

        ddr_mem_we_n_o,

        ddr_mem_dm_o,

        ddr_mem_clk_io,

        ddr_mem_clk_n_io,

        ddr_mem_dq_io,

        ddr_mem_dqs_io,

        // Ethernet

        eth_reset_n_pad_o,

        eth_tx_er_pad_o,

        eth_tx_clk_pad_i,

        eth_tx_en_pad_o,

        eth_txd_pad_o,

        eth_rx_er_pad_i,

        eth_rx_clk_pad_i,

        eth_rx_dv_pad_i,

        eth_rxd_pad_i,

        eth_col_pad_i,

        eth_crs_pad_i,

        eth_mdio_pad_io,

        eth_mdc_pad_o,

        // UART

        uart_stx_pad_o,

        uart_srx_pad_i,

        // GPIO

        gpio_a_pad_io,

/*

        // SPI_FLASH

        spi_flash_sclk_pad_o,

        spi_flash_ss_pad_o,

        spi_flash_miso_pad_i,

        spi_flash_mosi_pad_o,

        spi_flash_w_n_pad_o,

        spi_flash_hold_n_pad_o

*/

        // MMC/SD Card 

        sd_card_clk_pad_o,

        sd_card_data_pad_i,

        sd_card_data_pad_o,

        sd_card_cs_n_pad_o,

        // LEDs

        led3_pad_o

);

// System pads

input   wb_clk_pad_i;

input   ddr_pll_clk_pad_i;

input   rst_n_pad_i;

/*

//

// Flash

//

input   flash_clk_pad_i;

output          flash_rstn;

output          flash_cen;

output          flash_oen;

output          flash_wen;

input           flash_rdy;

inout   [7:0]   flash_d;

inout   [20:0]  flash_a;

// Memory controller pads

input           mc_clk_pad_i;

//

// SDR SDRAM

//

inout   [31:0]  mem_dat_pad_io;

output  [12:0]  mem_adr_pad_o;

output  [3:0]   mem_dqm_pad_o;

output  [1:0]   mem_ba_pad_o;

output          mem_cs_pad_o;

output          mem_ras_pad_o;

output          mem_cas_pad_o;

output          mem_we_pad_o;

output          mem_cke_pad_o;

*/

//DDR SDRAM

output  [0:0]     ddr_mem_cs_n_o;

output  [0:0]     ddr_mem_cke_o;

output  [12:0]   ddr_mem_addr_o;

output  [1:0]    ddr_mem_ba_o;

output          ddr_mem_ras_n_o;

output          ddr_mem_cas_n_o;

output          ddr_mem_we_n_o;

output  [1:0]    ddr_mem_dm_o;

inout   [0:0]     ddr_mem_clk_io;

inout   [0:0]     ddr_mem_clk_n_io;

inout   [15:0]   ddr_mem_dq_io;

inout   [1:0]    ddr_mem_dqs_io;

//

// Ethernet

//

output          eth_reset_n_pad_o;

output          eth_tx_er_pad_o;

input           eth_tx_clk_pad_i;

output          eth_tx_en_pad_o;

output  [3:0]    eth_txd_pad_o;

input           eth_rx_er_pad_i;

input           eth_rx_clk_pad_i;

input           eth_rx_dv_pad_i;

input   [3:0]    eth_rxd_pad_i;

input           eth_col_pad_i;

input           eth_crs_pad_i;

inout           eth_mdio_pad_io;

output          eth_mdc_pad_o;

//

// UART external i/f wires

//

output          uart_stx_pad_o;

input           uart_srx_pad_i;

// GPIO

inout [31:0]     gpio_a_pad_io;

/*

// SPI_FLASH

output          spi_flash_sclk_pad_o;

output          spi_flash_ss_pad_o;

input           spi_flash_miso_pad_i;

output          spi_flash_mosi_pad_o;

output          spi_flash_w_n_pad_o;

output          spi_flash_hold_n_pad_o;

*/

//

// spiMaster for MMC/SD Card

output sd_card_clk_pad_o;

input  sd_card_data_pad_i;

output sd_card_data_pad_o;

output sd_card_cs_n_pad_o;

//

// LEDs output

//

output led3_pad_o;

//

//---------------------------------------

// Internal Signals

//---------------------------------------

//

parameter dw = `OR1200_OPERAND_WIDTH;

parameter aw = `OR1200_OPERAND_WIDTH;

parameter ppic_ints = `OR1200_PIC_INTS;

//

// Signals for OR1200

//

wire    [1:0]            or1k_clmode_i = 2'd0;   // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4

//

// RISC misc

//

wire    [ppic_ints-1:0]  pic_ints;

//

// Instruction WISHBONE interface for OR1200

//

wire                    or1k_iwb_clk_i; // clock input

wire                    or1k_iwb_rst_i; // reset input

wire                    or1k_iwb_ack_i; // normal termination

wire                    or1k_iwb_err_i; // termination w/ error

wire                    or1k_iwb_rty_i; // termination w/ retry

wire    [dw-1:0] or1k_iwb_dat_i; // input data bus

wire                    or1k_iwb_cyc_o; // cycle valid output

wire    [aw-1:0] or1k_iwb_adr_o; // address bus outputs

wire                    or1k_iwb_stb_o; // strobe output

wire                    or1k_iwb_we_o;  // indicates write transfer

wire    [3:0]            or1k_iwb_sel_o; // byte select outputs

wire    [dw-1:0] or1k_iwb_dat_o; // output data bus

`ifdef OR1200_WB_CAB

wire                    or1k_iwb_cab_o; // indicates consecutive address burst

`endif

`ifdef OR1200_WB_B3

wire    [2:0]            or1k_iwb_cti_o; // cycle type identifier

wire    [1:0]            or1k_iwb_bte_o; // burst type extension

`endif

//

// Data WISHBONE interface for OR1200

//

wire                    or1k_dwb_clk_i; // clock input

wire                    or1k_dwb_rst_i; // reset input

wire                    or1k_dwb_ack_i; // normal termination

wire                    or1k_dwb_err_i; // termination w/ error

wire                    or1k_dwb_rty_i; // termination w/ retry

wire    [dw-1:0] or1k_dwb_dat_i; // input data bus

wire                    or1k_dwb_cyc_o; // cycle valid output

wire    [aw-1:0] or1k_dwb_adr_o; // address bus outputs

wire                    or1k_dwb_stb_o; // strobe output

wire                    or1k_dwb_we_o;  // indicates write transfer

wire    [3:0]            or1k_dwb_sel_o; // byte select outputs

wire    [dw-1:0] or1k_dwb_dat_o; // output data bus

`ifdef OR1200_WB_CAB

wire                    or1k_dwb_cab_o; // indicates consecutive address burst

`endif

`ifdef OR1200_WB_B3

wire    [2:0]            or1k_dwb_cti_o; // cycle type identifier

wire    [1:0]            or1k_dwb_bte_o; // burst type extension

`endif

/*

// MEM_IF_WB_SLAVE

wire    [31:0]  mem_if_wb_data_i;

wire    [31:0]  mem_if_wb_data_o;

wire    [31:0]  mem_if_wb_addr_i;

wire    [3:0]   mem_if_wb_sel_i;

wire            mem_if_wb_we_i;

wire            mem_if_wb_cyc_i;

wire            mem_if_wb_stb_i;

wire            mem_if_wb_ack_o;

wire            mem_if_wb_err_o;

//

// Flash controller slave i/f wires

//

wire    [31:0]          wb_fs_dat_i;

wire    [31:0]          wb_fs_dat_o;

wire    [31:0]          wb_fs_adr_i;

wire    [3:0]           wb_fs_sel_i;

wire                    wb_fs_we_i;

wire                    wb_fs_cyc_i;

wire                    wb_fs_stb_i;

wire                    wb_fs_ack_o;

wire                    wb_fs_err_o;

*/

//

// UART16550 core slave i/f wires

//

wire    [31:0]           wb_us_dat_i;

wire    [31:0]           wb_us_dat_o;

wire    [31:0]           wb_us_adr_i;

wire    [3:0]            wb_us_sel_i;

wire                    wb_us_we_i;

wire                    wb_us_cyc_i;

wire                    wb_us_stb_i;

wire                    wb_us_ack_o;

//wire                  wb_us_err_o;

// CPU signals for advanced debug interface

wire    [31:0]   dbg_cpu0_addr_o;

wire    [31:0]   dbg_cpu0_data_i;

wire    [31:0]   dbg_cpu0_data_o;

wire            dbg_cpu0_bp_i;

wire            dbg_cpu0_stall_o;

wire            dbg_cpu0_stb_o;

wire            dbg_cpu0_we_o;

wire            dbg_cpu0_ack_i;

wire            dbg_cpu0_rst_o;

//

// reset_request output from DDR core

//

wire    reset_request_n;

//

// for internal clk

//

wire    clk_cpu_25;     // cpu clk

wire    spiSysClk;      // spiMaster logic clock

//

// SD Loader

//

//wire        sd_loader_rst_o;

//wire        sd_loader_done_o;

//---------------------------------------

//

// Assign wires to pads

//

wire wb_rst_pad_i;

reg [1:0] count;

//

// generate wb_rst_pad_i by sd_loader_rst_o that is 

// from SD Loader 

//

/*

always @(posedge clk_cpu_25 or negedge reset_request_n)

begin

        if (~reset_request_n) begin

                wb_rst_pad_i <= 1'b1;

                count <= 2'b00;

        end

        else if (count != 2'b11) begin

                count <= count + 1;

        end

        else

                wb_rst_pad_i <= 1'b0;

end

*/

assign wb_rst_pad_i = ~reset_request_n; // ~rst_n_pad_i;

assign eth_reset_n_pad_o = ~wb_rst_pad_i;

//

// Unused interrupts

//

assign pic_ints[`APP_INT_RES1] = 'b0;

assign pic_ints[`APP_INT_RES3] = 'b0;

//

//---------------------------------------

// Compoments

//---------------------------------------

//

//

// Altera PLL

//

altera_pll pll (

        .inclk0 (wb_clk_pad_i),

        .c0     (),             // 25MHz for wb

        .c1     (clk_cpu_25),   // 30MHz 

        .c2     (),             // 35Mhz

        .c3     (spiSysClk),    // 50Mhz

        .locked ()

);

//

// OR1K CPU

//

or1200_top cpu(

        // System

        .clk_i          (clk_cpu_25),

        .rst_i          (wb_rst_pad_i | dbg_cpu0_rst_o),

        .clmode_i       (or1k_clmode_i),

        // Interrupts

        .pic_ints_i     (pic_ints),

        // Instruction WISHBONE INTERFACE

        .iwb_clk_i      (clk_cpu_25),

        .iwb_rst_i      (wb_rst_pad_i),

        .iwb_ack_i      (or1k_iwb_ack_i),

        .iwb_err_i      (or1k_iwb_err_i),

        .iwb_rty_i      (or1k_iwb_rty_i),

        .iwb_dat_i      (or1k_iwb_dat_i),

        .iwb_cyc_o      (or1k_iwb_cyc_o),

        .iwb_adr_o      (or1k_iwb_adr_o),

        .iwb_stb_o      (or1k_iwb_stb_o),

        .iwb_we_o       (or1k_iwb_we_o),

        .iwb_sel_o      (or1k_iwb_sel_o),

        .iwb_dat_o      (or1k_iwb_dat_o),

`ifdef NO_USED_CURRENTLY

`ifdef OR1200_WB_CAB

        iwb_cab_o,

`endif

`ifdef OR1200_WB_B3

        iwb_cti_o, iwb_bte_o,

`endif

`endif // NO_USED_CURRENTLY

        // Data WISHBONE INTERFACE

        .dwb_clk_i      (clk_cpu_25),

        .dwb_rst_i      (wb_rst_pad_i),

        .dwb_ack_i      (or1k_dwb_ack_i),

        .dwb_err_i      (or1k_dwb_err_i),

        .dwb_rty_i      (or1k_dwb_rty_i),

        .dwb_dat_i      (or1k_dwb_dat_i),

        .dwb_cyc_o      (or1k_dwb_cyc_o),

        .dwb_adr_o      (or1k_dwb_adr_o),

        .dwb_stb_o      (or1k_dwb_stb_o),

        .dwb_we_o       (or1k_dwb_we_o),

        .dwb_sel_o      (or1k_dwb_sel_o),

        .dwb_dat_o      (or1k_dwb_dat_o),

`ifdef OR1200_WB_CAB

        .dwb_cab_o      (),

`endif

`ifdef OR1200_WB_B3

        .dwb_cti_o      (),

        .dwb_bte_o      (),

`endif

        // External Debug Interface

        .dbg_stall_i    (dbg_cpu0_stall_o),

        .dbg_ewt_i      (1'b0),

        .dbg_lss_o      (),

        .dbg_is_o       (),

        .dbg_wp_o       (),

        .dbg_bp_o       (dbg_cpu0_bp_i),

        .dbg_stb_i      (dbg_cpu0_stb_o),

        .dbg_we_i       (dbg_cpu0_we_o),

        .dbg_adr_i      (dbg_cpu0_addr_o),

        .dbg_dat_i      (dbg_cpu0_data_o),

        .dbg_dat_o      (dbg_cpu0_data_i),

        .dbg_ack_o      (dbg_cpu0_ack_i),

        // Power Management

        .pm_cpustall_i  (1'b0),

        .pm_clksd_o     (),

        .pm_dc_gate_o   (),

        .pm_ic_gate_o   (),

        .pm_dmmu_gate_o (),

        .pm_immu_gate_o (),

        .pm_tt_gate_o   (),

        .pm_cpu_gate_o  (),

        .pm_wakeup_o    (),

        .pm_lvolt_o     ()

);

/*

flash_top flash_top (

        // WISHBONE common

        .wb_clk_i       ( wb_clk_pad_i ),

        .wb_rst_i       ( wb_rst_pad_i ),

        // WISHBONE slave

        .wb_dat_i       ( wb_fs_dat_i ),

        .wb_dat_o       ( wb_fs_dat_o ),

        .wb_adr_i       ( wb_fs_adr_i ),

        .wb_sel_i       ( wb_fs_sel_i ),

        .wb_we_i        ( wb_fs_we_i  ),

        .wb_cyc_i       ( wb_fs_cyc_i ),

        .wb_stb_i       ( wb_fs_stb_i ),

        .wb_ack_o       ( wb_fs_ack_o ),

        .wb_err_o       ( wb_fs_err_o ),

        // Flash external

        .flash_rstn     ( flash_rstn ),

        .cen            ( flash_cen ),

        .oen            ( flash_oen ),

        .wen            ( flash_wen ),

        .rdy            ( flash_rdy ),

        .d              ( flash_d ),

        .a              ( flash_a ),

        .a_oe           ( )

);

*/

`ifdef CONFIG_USE_SRAM

//

// SRAM controller slave i/f wires

//

wire    [31:0]          wb_ss_dat_i;

wire    [31:0]          wb_ss_dat_o;

wire    [31:0]          wb_ss_adr_i;

wire    [3:0]           wb_ss_sel_i;

wire                    wb_ss_we_i;

wire                    wb_ss_cyc_i;

wire                    wb_ss_stb_i;

wire                    wb_ss_ack_o;

wire                    wb_ss_err_o;

altera_ram_top     sram_top (

        // WISHBONE common

        .wb_clk_i       ( clk_cpu_25 ),

        .wb_rst_i       ( wb_rst_pad_i ),

        // WISHBONE slave

        .wb_dat_i       ( wb_ss_dat_i ),

        .wb_dat_o       ( wb_ss_dat_o ),

        .wb_adr_i       ( wb_ss_adr_i ),

        .wb_sel_i       ( wb_ss_sel_i ),

        .wb_we_i        ( wb_ss_we_i  ),

        .wb_cyc_i       ( wb_ss_cyc_i ),

        .wb_stb_i       ( wb_ss_stb_i ),

        .wb_ack_o       ( wb_ss_ack_o ),

        .wb_err_o       ( wb_ss_err_o )

);

`else

//

// memory controller

//

wire            mem_dat_pad_oe,mem_con_pad_oe;

wire [23:0]      mc_addr_wire_o;

wire [31:0]      mem_dat_pad_i, mem_dat_pad_o;// mem_dat_pad_oe is now declared lower! - Julius

//wire [1:0]    mem_dqm_pad_oe;

wire [12:0]      mem_adr_pad_oe;

//wire [1:0]    mem_ba_pad_oe;

wire [7:0]       mem_csi_pad_o;

wire [7:0]       mem_csi_pad_oe;

wire            mem_ras_pad_oe, mem_cas_pad_oe, mem_we_pad_oe, mem_cke_pad_oe;

mc_top mem_if(

        .clk_i          (clk_cpu_25),

        .rst_i          (wb_rst_pad_i), // The reset is asynchronous and an active low signal

        .wb_data_i      (mem_if_wb_data_i),

        .wb_data_o      (mem_if_wb_data_o),

        .wb_addr_i      (mem_if_wb_addr_i),

        .wb_sel_i       (mem_if_wb_sel_i),

        .wb_we_i        (mem_if_wb_we_i),

        .wb_cyc_i       (mem_if_wb_cyc_i),

        .wb_stb_i       (mem_if_wb_stb_i),

        .wb_ack_o       (mem_if_wb_ack_o),

        .wb_err_o       (mem_if_wb_err_o),

        .suspended_o            (),

        .poc_o                  (),

        .mc_bg_pad_o            (),

        .mc_addr_pad_o          (mc_addr_wire_o),

        .mc_data_pad_o          (mem_dat_pad_o),

        .mc_dp_pad_o            (),

        .mc_doe_pad_doe_o       (mem_dat_pad_oe),

        .mc_dqm_pad_o           (mem_dqm_pad_o),

        .mc_oe_pad_o_           (mem_oe_pad_o_),

        .mc_we_pad_o_           (mem_we_pad_o),

        .mc_cas_pad_o_          (mem_cas_pad_o),

        .mc_ras_pad_o_          (mem_ras_pad_o),

        .mc_cke_pad_o_          (mem_cke_pad_o),

        .mc_cs_pad_o_           (mem_csi_pad_o),

        .mc_rp_pad_o_           (),

        .mc_vpen_pad_o          (),

        .mc_adsc_pad_o_         (),

        .mc_adv_pad_o_          (),

        .mc_zz_pad_o            (),

        .mc_coe_pad_coe_o       (mem_con_pad_oe),

        .susp_req_i             (1'b0),

        .resume_req_i           (1'b0),

        .mc_clk_i               (mc_clk_pad_i),

        .mc_br_pad_i            (1'b0),

        .mc_ack_pad_i           (1'b0),

        .mc_data_pad_i          (mem_dat_pad_i),

        .mc_dp_pad_i            (4'h0),

        .mc_sts_pad_i           (1'b0)

);

   assign        mem_dat_pad_io = (wb_rst_pad_i) ? 32'h0000_0000 :  (mem_dat_pad_oe) ? mem_dat_pad_o : {32{1'bz}};

   assign        mem_dat_pad_i = mem_dat_pad_io;

   assign        mem_cs_pad_o = mem_csi_pad_o[0];

   assign        mem_adr_pad_o = (mem_con_pad_oe) ? mc_addr_wire_o[12:0] : {13{1'bz}};

   assign        mem_ba_pad_o = (mem_con_pad_oe) ? mc_addr_wire_o[14:13] : {2{1'bz}};

`endif

//

// DDR SDRAM

//

wire    [31:0]           ddr_wb_dat_i;

wire    [31:0]           ddr_wb_dat_o;

wire    [31:0]           ddr_wb_adr_i;

wire    [3:0]            ddr_wb_sel_i;

wire                    ddr_wb_we_i;

wire                    ddr_wb_cyc_i;

wire                    ddr_wb_stb_i;

wire                    ddr_wb_ack_o;

wire                    ddr_wb_err_o;

altera_ddr_top ddr_sdram (

  // Wishbine interface

        .wb_clk_i       (clk_cpu_25),   // 25MHz

        .wb_rst_i       (wb_rst_pad_i), // for soft_reset

        .wb_dat_i       (ddr_wb_dat_i),

        .wb_dat_o       (ddr_wb_dat_o),

        .wb_adr_i       (ddr_wb_adr_i),

        .wb_sel_i       (ddr_wb_sel_i),

        .wb_we_i        (ddr_wb_we_i),

        .wb_cyc_i       (ddr_wb_cyc_i),

        .wb_stb_i       (ddr_wb_stb_i),

        .wb_ack_o       (ddr_wb_ack_o),

        .wb_err_o       (ddr_wb_err_o),

        // reset to ddr core

        .global_reset_n_i(rst_n_pad_i),

        // global output

        .reset_request_n_o(reset_request_n),

        // to DDR SDRAM

        .ddr_pll_clk_i  (ddr_pll_clk_pad_i),    // 50 MHz

        .mem_cs_n_o     (ddr_mem_cs_n_o),

        .mem_cke_o      (ddr_mem_cke_o),

        .mem_addr_o     (ddr_mem_addr_o),

        .mem_ba_o       (ddr_mem_ba_o),

        .mem_ras_n_o    (ddr_mem_ras_n_o),

        .mem_cas_n_o    (ddr_mem_cas_n_o),

        .mem_we_n_o     (ddr_mem_we_n_o),

        .mem_dm_o       (ddr_mem_dm_o),

        .mem_clk_io     (ddr_mem_clk_io),

        .mem_clk_n_io   (ddr_mem_clk_n_io),

        .mem_dq_io      (ddr_mem_dq_io),

        .mem_dqs_io     (ddr_mem_dqs_io)

);

//

// Instantiation of the UART16550

//

uart_top uart_top (

        // WISHBONE common

        .wb_clk_i       ( clk_cpu_25 ),

        .wb_rst_i       ( wb_rst_pad_i ),

        // WISHBONE slave

        .wb_adr_i       ( wb_us_adr_i[4:0] ),

        .wb_dat_i       ( wb_us_dat_i ),

        .wb_dat_o       ( wb_us_dat_o ),

        .wb_we_i        ( wb_us_we_i  ),

        .wb_stb_i       ( wb_us_stb_i ),

        .wb_cyc_i       ( wb_us_cyc_i ),

        .wb_ack_o       ( wb_us_ack_o ),

        .wb_sel_i       ( wb_us_sel_i ),

        // Interrupt request

        .int_o          ( pic_ints[`APP_INT_UART] ),

        // UART signals

        // serial input/output

        .stx_pad_o      ( uart_stx_pad_o ),

        .srx_pad_i      ( uart_srx_pad_i ),

        // modem signals

        .rts_pad_o      ( ),

        .cts_pad_i      ( 1'b0 ),

        .dtr_pad_o      ( ),

        .dsr_pad_i      ( 1'b0 ),

        .ri_pad_i       ( 1'b0 ),

        .dcd_pad_i      ( 1'b0 )

);

   // GPIO

// wbs_gpio_led

wire [31:0] wbs_gpio_dat_o;

wire [31:0] wbs_gpio_dat_i;

wire [31:0] wbs_gpio_adr_i;

wire [3:0] wbs_gpio_sel_i;

wire wbs_gpio_stb_i;

wire wbs_gpio_cyc_i;

wire wbs_gpio_ack_o;

wire wbs_gpio_err_o;

   // GPIO_0

   wire [31:0]    gpio_a_o, gpio_a_oe, gpio_a_i;

   gpio_top i_gpio_a_top (

                          .wb_dat_o     (wbs_gpio_dat_o),

                          .wb_dat_i     (wbs_gpio_dat_i),

                          .wb_sel_i     (wbs_gpio_sel_i),

                          .wb_adr_i     (wbs_gpio_adr_i[7:0]),

                          .wb_we_i      (wbs_gpio_we_i),

                          .wb_stb_i     (wbs_gpio_stb_i),

                          .wb_cyc_i     (wbs_gpio_cyc_i),

                          .wb_ack_o     (wbs_gpio_ack_o),

                          .wb_err_o     (wbs_gpio_err_o),

                          .wb_clk_i     (clk_cpu_25),

                          .wb_rst_i     (wb_rst_pad_i),

                          .wb_inta_o    (pic_ints[`APP_INT_GPIO]),

                          .ext_pad_i    (gpio_a_i),

                          .ext_pad_o    (gpio_a_o),

                          .ext_padoe_o  (gpio_a_oe)

                          );

   assign        gpio_a_pad_io[ 0] = (gpio_a_oe[ 0]) ? gpio_a_o[ 0] : 1'bz;