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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [spi/] [rtl/] [verilog/] [spi_shift.v] - Blame information for rev 12

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  spi_shift.v                                                 ////
////                                                              ////
////  This file is part of the SPI IP core project                ////
////  http://www.opencores.org/projects/spi/                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Srot (simons@opencores.org)                     ////
////                                                              ////
////  All additional information is avaliable in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
`include "spi_defines.v"
`include "timescale.v"
 
module spi_shift (clk, rst, latch, byte_sel, len, lsb, go,
                  pos_edge, neg_edge, rx_negedge, tx_negedge,
                  tip, last,
                  p_in, p_out, s_clk, s_in, s_out);
 
  parameter Tp = 1;
 
  input                          clk;          // system clock
  input                          rst;          // reset
  input                    [3:0] latch;        // latch signal for storing the data in shift register
  input                    [3:0] byte_sel;     // byte select signals for storing the data in shift register
  input [`SPI_CHAR_LEN_BITS-1:0] len;          // data len in bits (minus one)
  input                          lsb;          // lbs first on the line
  input                          go;           // start stansfer
  input                          pos_edge;     // recognize posedge of sclk
  input                          neg_edge;     // recognize negedge of sclk
  input                          rx_negedge;   // s_in is sampled on negative edge 
  input                          tx_negedge;   // s_out is driven on negative edge
  output                         tip;          // transfer in progress
  output                         last;         // last bit
  input                   [31:0] p_in;         // parallel in
  output     [`SPI_MAX_CHAR-1:0] p_out;        // parallel out
  input                          s_clk;        // serial clock
  input                          s_in;         // serial in
  output                         s_out;        // serial out
 
  reg                            s_out;
  reg                            tip;
 
  reg     [`SPI_CHAR_LEN_BITS:0] cnt;          // data bit count
  reg        [`SPI_MAX_CHAR-1:0] data;         // shift register
  wire    [`SPI_CHAR_LEN_BITS:0] tx_bit_pos;   // next bit position
  wire    [`SPI_CHAR_LEN_BITS:0] rx_bit_pos;   // next bit position
  wire                           rx_clk;       // rx clock enable
  wire                           tx_clk;       // tx clock enable
 
  assign p_out = data;
 
  assign tx_bit_pos = lsb ? {!(|len), len} - cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1};
  assign rx_bit_pos = lsb ? {!(|len), len} - (rx_negedge ? cnt + {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1} : cnt) :
                            (rx_negedge ? cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1});
 
  assign last = !(|cnt);
 
  assign rx_clk = (rx_negedge ? neg_edge : pos_edge) && (!last || s_clk);
  assign tx_clk = (tx_negedge ? neg_edge : pos_edge) && !last;
 
  // Character bit counter
  always @(posedge clk or posedge rst)
  begin
    if(rst)
      cnt <= #Tp {`SPI_CHAR_LEN_BITS+1{1'b0}};
    else
      begin
        if(tip)
          cnt <= #Tp pos_edge ? (cnt - {{`SPI_CHAR_LEN_BITS{1'b0}}, 1'b1}) : cnt;
        else
          cnt <= #Tp !(|len) ? {1'b1, {`SPI_CHAR_LEN_BITS{1'b0}}} : {1'b0, len};
      end
  end
 
  // Transfer in progress
  always @(posedge clk or posedge rst)
  begin
    if(rst)
      tip <= #Tp 1'b0;
  else if(go && ~tip)
    tip <= #Tp 1'b1;
  else if(tip && last && pos_edge)
    tip <= #Tp 1'b0;
  end
 
  // Sending bits to the line
  always @(posedge clk or posedge rst)
  begin
    if (rst)
      s_out   <= #Tp 1'b0;
    else
      s_out <= #Tp (tx_clk || !tip) ? data[tx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] : s_out;
  end
 
  // Receiving bits from the line
  always @(posedge clk or posedge rst)
  begin
    if (rst)
      data   <= #Tp {`SPI_MAX_CHAR{1'b0}};
`ifdef SPI_MAX_CHAR_128
    else if (latch[0] && !tip)
      begin
        if (byte_sel[3])
          data[31:24] <= #Tp p_in[31:24];
        if (byte_sel[2])
          data[23:16] <= #Tp p_in[23:16];
        if (byte_sel[1])
          data[15:8] <= #Tp p_in[15:8];
        if (byte_sel[0])
          data[7:0] <= #Tp p_in[7:0];
      end
    else if (latch[1] && !tip)
      begin
        if (byte_sel[3])
          data[63:56] <= #Tp p_in[31:24];
        if (byte_sel[2])
          data[55:48] <= #Tp p_in[23:16];
        if (byte_sel[1])
          data[47:40] <= #Tp p_in[15:8];
        if (byte_sel[0])
          data[39:32] <= #Tp p_in[7:0];
      end
    else if (latch[2] && !tip)
      begin
        if (byte_sel[3])
          data[95:88] <= #Tp p_in[31:24];
        if (byte_sel[2])
          data[87:80] <= #Tp p_in[23:16];
        if (byte_sel[1])
          data[79:72] <= #Tp p_in[15:8];
        if (byte_sel[0])
          data[71:64] <= #Tp p_in[7:0];
      end
    else if (latch[3] && !tip)
      begin
        if (byte_sel[3])
          data[127:120] <= #Tp p_in[31:24];
        if (byte_sel[2])
          data[119:112] <= #Tp p_in[23:16];
        if (byte_sel[1])
          data[111:104] <= #Tp p_in[15:8];
        if (byte_sel[0])
          data[103:96] <= #Tp p_in[7:0];
      end
`else
`ifdef SPI_MAX_CHAR_64
    else if (latch[0] && !tip)
      begin
        if (byte_sel[3])
          data[31:24] <= #Tp p_in[31:24];
        if (byte_sel[2])
          data[23:16] <= #Tp p_in[23:16];
        if (byte_sel[1])
          data[15:8] <= #Tp p_in[15:8];
        if (byte_sel[0])
          data[7:0] <= #Tp p_in[7:0];
      end
    else if (latch[1] && !tip)
      begin
        if (byte_sel[3])
          data[63:56] <= #Tp p_in[31:24];
        if (byte_sel[2])
          data[55:48] <= #Tp p_in[23:16];
        if (byte_sel[1])
          data[47:40] <= #Tp p_in[15:8];
        if (byte_sel[0])
          data[39:32] <= #Tp p_in[7:0];
      end
`else
    else if (latch[0] && !tip)
      begin
      `ifdef SPI_MAX_CHAR_8
        if (byte_sel[0])
          data[`SPI_MAX_CHAR-1:0] <= #Tp p_in[`SPI_MAX_CHAR-1:0];
      `endif
      `ifdef SPI_MAX_CHAR_16
        if (byte_sel[0])
          data[7:0] <= #Tp p_in[7:0];
        if (byte_sel[1])
          data[`SPI_MAX_CHAR-1:8] <= #Tp p_in[`SPI_MAX_CHAR-1:8];
      `endif
      `ifdef SPI_MAX_CHAR_24
        if (byte_sel[0])
          data[7:0] <= #Tp p_in[7:0];
        if (byte_sel[1])
          data[15:8] <= #Tp p_in[15:8];
        if (byte_sel[2])
          data[`SPI_MAX_CHAR-1:16] <= #Tp p_in[`SPI_MAX_CHAR-1:16];
      `endif
      `ifdef SPI_MAX_CHAR_32
        if (byte_sel[0])
          data[7:0] <= #Tp p_in[7:0];
        if (byte_sel[1])
          data[15:8] <= #Tp p_in[15:8];
        if (byte_sel[2])
          data[23:16] <= #Tp p_in[23:16];
        if (byte_sel[3])
          data[`SPI_MAX_CHAR-1:24] <= #Tp p_in[`SPI_MAX_CHAR-1:24];
      `endif
      end
`endif
`endif
    else
      data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <= #Tp rx_clk ? s_in : data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]];
  end
 
endmodule
 

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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [spi/] [rtl/] [verilog/] [spi_shift.v] - Blame information for rev 12

Line No.	Rev	Author	Line
1	12	xianfeng	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// spi_shift.v ////`
4			`//// ////`
5			`//// This file is part of the SPI IP core project ////`
6			`//// http://www.opencores.org/projects/spi/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Simon Srot (simons@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the Readme.txt ////`
12			`//// file. ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// Copyright (C) 2002 Authors ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40
41			`include "spi_defines.v"
42			`include "timescale.v"
43
44			`module spi_shift (clk, rst, latch, byte_sel, len, lsb, go,`
45			`pos_edge, neg_edge, rx_negedge, tx_negedge,`
46			`tip, last,`
47			`p_in, p_out, s_clk, s_in, s_out);`
48
49			`parameter Tp = 1;`
50
51			`input clk; // system clock`
52			`input rst; // reset`
53			`input [3:0] latch; // latch signal for storing the data in shift register`
54			`input [3:0] byte_sel; // byte select signals for storing the data in shift register`
55			input [`SPI_CHAR_LEN_BITS-1:0] len; // data len in bits (minus one)
56			`input lsb; // lbs first on the line`
57			`input go; // start stansfer`
58			`input pos_edge; // recognize posedge of sclk`
59			`input neg_edge; // recognize negedge of sclk`
60			`input rx_negedge; // s_in is sampled on negative edge`
61			`input tx_negedge; // s_out is driven on negative edge`
62			`output tip; // transfer in progress`
63			`output last; // last bit`
64			`input [31:0] p_in; // parallel in`
65			output [`SPI_MAX_CHAR-1:0] p_out; // parallel out
66			`input s_clk; // serial clock`
67			`input s_in; // serial in`
68			`output s_out; // serial out`
69
70			`reg s_out;`
71			`reg tip;`
72
73			reg [`SPI_CHAR_LEN_BITS:0] cnt; // data bit count
74			reg [`SPI_MAX_CHAR-1:0] data; // shift register
75			wire [`SPI_CHAR_LEN_BITS:0] tx_bit_pos; // next bit position
76			wire [`SPI_CHAR_LEN_BITS:0] rx_bit_pos; // next bit position
77			`wire rx_clk; // rx clock enable`
78			`wire tx_clk; // tx clock enable`
79
80			`assign p_out = data;`
81
82			assign tx_bit_pos = lsb ? {!(\|len), len} - cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1};
83			assign rx_bit_pos = lsb ? {!(\|len), len} - (rx_negedge ? cnt + {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1} : cnt) :
84			(rx_negedge ? cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1});
85
86			`assign last = !(\|cnt);`
87
88			`assign rx_clk = (rx_negedge ? neg_edge : pos_edge) && (!last \|\| s_clk);`
89			`assign tx_clk = (tx_negedge ? neg_edge : pos_edge) && !last;`
90
91			`// Character bit counter`
92			`always @(posedge clk or posedge rst)`
93			`begin`
94			`if(rst)`
95			cnt <= #Tp {`SPI_CHAR_LEN_BITS+1{1'b0}};
96			`else`
97			`begin`
98			`if(tip)`
99			cnt <= #Tp pos_edge ? (cnt - {{`SPI_CHAR_LEN_BITS{1'b0}}, 1'b1}) : cnt;
100			`else`
101			cnt <= #Tp !(\|len) ? {1'b1, {`SPI_CHAR_LEN_BITS{1'b0}}} : {1'b0, len};
102			`end`
103			`end`
104
105			`// Transfer in progress`
106			`always @(posedge clk or posedge rst)`
107			`begin`
108			`if(rst)`
109			`tip <= #Tp 1'b0;`
110			`else if(go && ~tip)`
111			`tip <= #Tp 1'b1;`
112			`else if(tip && last && pos_edge)`
113			`tip <= #Tp 1'b0;`
114			`end`
115
116			`// Sending bits to the line`
117			`always @(posedge clk or posedge rst)`
118			`begin`
119			`if (rst)`
120			`s_out <= #Tp 1'b0;`
121			`else`
122			s_out <= #Tp (tx_clk \|\| !tip) ? data[tx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] : s_out;
123			`end`
124
125			`// Receiving bits from the line`
126			`always @(posedge clk or posedge rst)`
127			`begin`
128			`if (rst)`
129			data <= #Tp {`SPI_MAX_CHAR{1'b0}};
130			`ifdef SPI_MAX_CHAR_128
131			`else if (latch[0] && !tip)`
132			`begin`
133			`if (byte_sel[3])`
134			`data[31:24] <= #Tp p_in[31:24];`
135			`if (byte_sel[2])`
136			`data[23:16] <= #Tp p_in[23:16];`
137			`if (byte_sel[1])`
138			`data[15:8] <= #Tp p_in[15:8];`
139			`if (byte_sel[0])`
140			`data[7:0] <= #Tp p_in[7:0];`
141			`end`
142			`else if (latch[1] && !tip)`
143			`begin`
144			`if (byte_sel[3])`
145			`data[63:56] <= #Tp p_in[31:24];`
146			`if (byte_sel[2])`
147			`data[55:48] <= #Tp p_in[23:16];`
148			`if (byte_sel[1])`
149			`data[47:40] <= #Tp p_in[15:8];`
150			`if (byte_sel[0])`
151			`data[39:32] <= #Tp p_in[7:0];`
152			`end`
153			`else if (latch[2] && !tip)`
154			`begin`
155			`if (byte_sel[3])`
156			`data[95:88] <= #Tp p_in[31:24];`
157			`if (byte_sel[2])`
158			`data[87:80] <= #Tp p_in[23:16];`
159			`if (byte_sel[1])`
160			`data[79:72] <= #Tp p_in[15:8];`
161			`if (byte_sel[0])`
162			`data[71:64] <= #Tp p_in[7:0];`
163			`end`
164			`else if (latch[3] && !tip)`
165			`begin`
166			`if (byte_sel[3])`
167			`data[127:120] <= #Tp p_in[31:24];`
168			`if (byte_sel[2])`
169			`data[119:112] <= #Tp p_in[23:16];`
170			`if (byte_sel[1])`
171			`data[111:104] <= #Tp p_in[15:8];`
172			`if (byte_sel[0])`
173			`data[103:96] <= #Tp p_in[7:0];`
174			`end`
175			`else
176			`ifdef SPI_MAX_CHAR_64
177			`else if (latch[0] && !tip)`
178			`begin`
179			`if (byte_sel[3])`
180			`data[31:24] <= #Tp p_in[31:24];`
181			`if (byte_sel[2])`
182			`data[23:16] <= #Tp p_in[23:16];`
183			`if (byte_sel[1])`
184			`data[15:8] <= #Tp p_in[15:8];`
185			`if (byte_sel[0])`
186			`data[7:0] <= #Tp p_in[7:0];`
187			`end`
188			`else if (latch[1] && !tip)`
189			`begin`
190			`if (byte_sel[3])`
191			`data[63:56] <= #Tp p_in[31:24];`
192			`if (byte_sel[2])`
193			`data[55:48] <= #Tp p_in[23:16];`
194			`if (byte_sel[1])`
195			`data[47:40] <= #Tp p_in[15:8];`
196			`if (byte_sel[0])`
197			`data[39:32] <= #Tp p_in[7:0];`
198			`end`
199			`else
200			`else if (latch[0] && !tip)`
201			`begin`
202			`ifdef SPI_MAX_CHAR_8
203			`if (byte_sel[0])`
204			data[`SPI_MAX_CHAR-1:0] <= #Tp p_in[`SPI_MAX_CHAR-1:0];
205			`endif
206			`ifdef SPI_MAX_CHAR_16
207			`if (byte_sel[0])`
208			`data[7:0] <= #Tp p_in[7:0];`
209			`if (byte_sel[1])`
210			data[`SPI_MAX_CHAR-1:8] <= #Tp p_in[`SPI_MAX_CHAR-1:8];
211			`endif
212			`ifdef SPI_MAX_CHAR_24
213			`if (byte_sel[0])`
214			`data[7:0] <= #Tp p_in[7:0];`
215			`if (byte_sel[1])`
216			`data[15:8] <= #Tp p_in[15:8];`
217			`if (byte_sel[2])`
218			data[`SPI_MAX_CHAR-1:16] <= #Tp p_in[`SPI_MAX_CHAR-1:16];
219			`endif
220			`ifdef SPI_MAX_CHAR_32
221			`if (byte_sel[0])`
222			`data[7:0] <= #Tp p_in[7:0];`
223			`if (byte_sel[1])`
224			`data[15:8] <= #Tp p_in[15:8];`
225			`if (byte_sel[2])`
226			`data[23:16] <= #Tp p_in[23:16];`
227			`if (byte_sel[3])`
228			data[`SPI_MAX_CHAR-1:24] <= #Tp p_in[`SPI_MAX_CHAR-1:24];
229			`endif
230			`end`
231			`endif
232			`endif
233			`else`
234			data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <= #Tp rx_clk ? s_in : data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]];
235			`end`
236
237			`endmodule`
238