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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [uart16550/] [rtl/] [verilog-backup/] [uart_fifo.v] - Blame information for rev 12

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  uart_fifo.v                                                 ////
////                                                              ////
////                                                              ////
////  This file is part of the "UART 16550 compatible" project    ////
////  http://www.opencores.org/cores/uart16550/                   ////
////                                                              ////
////  Documentation related to this project:                      ////
////  - http://www.opencores.org/cores/uart16550/                 ////
////                                                              ////
////  Projects compatibility:                                     ////
////  - WISHBONE                                                  ////
////  RS232 Protocol                                              ////
////  16550D uart (mostly supported)                              ////
////                                                              ////
////  Overview (main Features):                                   ////
////  UART core receiver FIFO                                     ////
////                                                              ////
////  Known problems (limits):                                    ////
////  Note that the same FIFO is used for both transmission  and  ////
////  reception but the error bit generation is ignored in tx.    ////
////                                                              ////
////  To Do:                                                      ////
////  Nothing.                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - gorban@opencores.org                                  ////
////      - Jacob Gorban                                          ////
////                                                              ////
////  Created:        2001/05/12                                  ////
////  Last Updated:   2001/05/17                                  ////
////                  (See log for the revision history)          ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Jacob Gorban, gorban@opencores.org        ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: uart_fifo.v,v $
// Revision 1.3  2001/05/31 20:08:01  gorban
// FIFO changes and other corrections.
//
// Revision 1.3  2001/05/27 17:37:48  gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.2  2001/05/17 18:34:18  gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0  2001-05-17 21:27:12+02  jacob
// Initial revision
//
//
 
`include "timescale.v"
`include "uart_defines.v"
 
module uart_fifo (clk,
        wb_rst_i, data_in, data_out,
// Control signals
        push, // push strobe, active high
        pop,   // pop strobe, active high
// status signals
        underrun,
        overrun,
        count,
        error_bit,
        fifo_reset,
        reset_status
        );
 
 
// FIFO parameters
parameter fifo_width = `UART_FIFO_WIDTH;
parameter fifo_depth = `UART_FIFO_DEPTH;
parameter fifo_pointer_w = `UART_FIFO_POINTER_W;
parameter fifo_counter_w = `UART_FIFO_COUNTER_W;
 
input                           clk;
input                           wb_rst_i;
input                           push;
input                           pop;
input   [fifo_width-1:0] data_in;
input                           fifo_reset;
input       reset_status;
 
output  [fifo_width-1:0] data_out;
output                          overrun;
output                          underrun;
output  [fifo_counter_w-1:0]     count;
output                          error_bit;
 
wire    [fifo_width-1:0] data_out;
 
// FIFO itself
reg     [fifo_width-1:0] fifo[fifo_depth-1:0];
 
// FIFO pointers
reg     [fifo_pointer_w-1:0]     top;
reg     [fifo_pointer_w-1:0]     bottom;
 
reg     [fifo_counter_w-1:0]     count;
reg                             overrun;
reg                             underrun;
 
// These registers and signals are to detect rise of of the signals.
// Not that it slows the maximum rate by 2, meaning you must reset the signals and then
// assert them again for the operation to repeat
// This is done to accomodate wait states
reg                             push_delay;
reg                             pop_delay;
 
wire                            push_rise = push_delay & push;
wire                            pop_rise  = pop_delay  & pop;
 
wire [fifo_pointer_w-1:0] top_plus_1 = top + 1;
 
always @(posedge clk or posedge wb_rst_i)
begin
        if (wb_rst_i)
                push_delay <= #1 1'b0;
        else
                push_delay <= #1 ~push;
end
 
always @(posedge clk or posedge wb_rst_i)
begin
        if (wb_rst_i)
                pop_delay <= #1 1'b0;
        else
                pop_delay <= #1 ~pop;
end
 
 
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
begin
        if (wb_rst_i)
        begin
                top             <= #1 0;
//              bottom          <= #1 1; igor
                bottom          <= #1 1'b0;
                underrun        <= #1 1'b0;
                overrun         <= #1 1'b0;
                count           <= #1 0;
                fifo[0]          <= #1 0;
                fifo[1]         <= #1 0;
                fifo[2]         <= #1 0;
                fifo[3]         <= #1 0;
                fifo[4]         <= #1 0;
                fifo[5]         <= #1 0;
                fifo[6]         <= #1 0;
                fifo[7]         <= #1 0;
                fifo[8]         <= #1 0;
                fifo[9]         <= #1 0;
                fifo[10]        <= #1 0;
                fifo[11]        <= #1 0;
                fifo[12]        <= #1 0;
                fifo[13]        <= #1 0;
                fifo[14]        <= #1 0;
                fifo[15]        <= #1 0;
        end
        else
        if (fifo_reset) begin
                top             <= #1 0;
//              bottom          <= #1 1; igor
                bottom          <= #1 1'b0;
                underrun        <= #1 1'b0;
                overrun         <= #1 1'b0;
                count           <= #1 0;
        end
  else
  if(reset_status)
    begin
                underrun        <= #1 1'b0;
                overrun         <= #1 1'b0;
    end
        else
        begin
                case ({push_rise, pop_rise})
                2'b00 : begin
                                underrun <= #1 1'b0;
//                              overrun  <= #1 1'b0;// Igor Ko se postavita ostaneta aktivna tako dolgo, dokler se ne naredi read LSR registra
                        end
                2'b10 : if (count==fifo_depth)  // overrun condition
                        begin
                                overrun   <= #1 1'b1;
                                underrun  <= #1 1'b0;
                        end
                        else
                        begin
                                top       <= #1 top_plus_1;
//                              fifo[top_plus_1] <= #1 data_in; igor
                                fifo[top] <= #1 data_in;
//                              overrun   <= #1 0;// Igor Ko se postavita ostaneta aktivna tako dolgo, dokler se ne naredi read LSR registra
                                overrun   <= #1 0;
                                count     <= #1 count + 1;
                        end
                2'b01 : if (~|count)
                        begin
//                              overrun  <= #1 1'b0;  Igor Ko se postavita ostaneta aktivna tako dolgo, dokler se ne naredi read LSR registra
                                overrun  <= #1 1'b0;
                        end
                        else
                        begin
                                bottom   <= #1 bottom + 1;
//                              overrun  <= #1 1'b0;  Igor Ko se postavita ostaneta aktivna tako dolgo, dokler se ne naredi read LSR registra
                                overrun  <= #1 1'b0;
                                count    <= #1 count - 1;
                        end
                2'b11 : begin
                                bottom   <= #1 bottom + 1;
                                top       <= #1 top_plus_1;
//                              fifo[top_plus_1] <= #1 data_in; igor
                                fifo[top] <= #1 data_in;
                                underrun <= #1 1'b0;
//                              overrun  <= #1 1'b0;  Igor Ko se postavita ostaneta aktivna tako dolgo, dokler se ne naredi read LSR registra
                        end
                endcase
        end
 
end   // always
 
// please note though that data_out is only valid one clock after pop signal
assign data_out = fifo[bottom];
 
// Additional logic for detection of error conditions (parity and framing) inside the FIFO
// for the Line Status Register bit 7
 
wire    [fifo_width-1:0] word0 = fifo[0];
wire    [fifo_width-1:0] word1 = fifo[1];
wire    [fifo_width-1:0] word2 = fifo[2];
wire    [fifo_width-1:0] word3 = fifo[3];
wire    [fifo_width-1:0] word4 = fifo[4];
wire    [fifo_width-1:0] word5 = fifo[5];
wire    [fifo_width-1:0] word6 = fifo[6];
wire    [fifo_width-1:0] word7 = fifo[7];
 
wire    [fifo_width-1:0] word8 = fifo[8];
wire    [fifo_width-1:0] word9 = fifo[9];
wire    [fifo_width-1:0] word10 = fifo[10];
wire    [fifo_width-1:0] word11 = fifo[11];
wire    [fifo_width-1:0] word12 = fifo[12];
wire    [fifo_width-1:0] word13 = fifo[13];
wire    [fifo_width-1:0] word14 = fifo[14];
wire    [fifo_width-1:0] word15 = fifo[15];
 
// a 1 is returned if any of the error bits in the fifo is 1
assign  error_bit = |(word0[1:0]  | word1[1:0]  | word2[1:0]  | word3[1:0]  |
                              word4[1:0]  | word5[1:0]  | word6[1:0]  | word7[1:0]  |
                              word8[1:0]  | word9[1:0]  | word10[1:0] | word11[1:0] |
                              word12[1:0] | word13[1:0] | word14[1:0] | word15[1:0] );
 
endmodule

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Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [uart16550/] [rtl/] [verilog-backup/] [uart_fifo.v] - Blame information for rev 12

Line No.	Rev	Author	Line
1	12	xianfeng	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// uart_fifo.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the "UART 16550 compatible" project ////`
7			`//// http://www.opencores.org/cores/uart16550/ ////`
8			`//// ////`
9			`//// Documentation related to this project: ////`
10			`//// - http://www.opencores.org/cores/uart16550/ ////`
11			`//// ////`
12			`//// Projects compatibility: ////`
13			`//// - WISHBONE ////`
14			`//// RS232 Protocol ////`
15			`//// 16550D uart (mostly supported) ////`
16			`//// ////`
17			`//// Overview (main Features): ////`
18			`//// UART core receiver FIFO ////`
19			`//// ////`
20			`//// Known problems (limits): ////`
21			`//// Note that the same FIFO is used for both transmission and ////`
22			`//// reception but the error bit generation is ignored in tx. ////`
23			`//// ////`
24			`//// To Do: ////`
25			`//// Nothing. ////`
26			`//// ////`
27			`//// Author(s): ////`
28			`//// - gorban@opencores.org ////`
29			`//// - Jacob Gorban ////`
30			`//// ////`
31			`//// Created: 2001/05/12 ////`
32			`//// Last Updated: 2001/05/17 ////`
33			`//// (See log for the revision history) ////`
34			`//// ////`
35			`//// ////`
36			`//////////////////////////////////////////////////////////////////////`
37			`//// ////`
38			`//// Copyright (C) 2000 Jacob Gorban, gorban@opencores.org ////`
39			`//// ////`
40			`//// This source file may be used and distributed without ////`
41			`//// restriction provided that this copyright statement is not ////`
42			`//// removed from the file and that any derivative work contains ////`
43			`//// the original copyright notice and the associated disclaimer. ////`
44			`//// ////`
45			`//// This source file is free software; you can redistribute it ////`
46			`//// and/or modify it under the terms of the GNU Lesser General ////`
47			`//// Public License as published by the Free Software Foundation; ////`
48			`//// either version 2.1 of the License, or (at your option) any ////`
49			`//// later version. ////`
50			`//// ////`
51			`//// This source is distributed in the hope that it will be ////`
52			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
53			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
54			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
55			`//// details. ////`
56			`//// ////`
57			`//// You should have received a copy of the GNU Lesser General ////`
58			`//// Public License along with this source; if not, download it ////`
59			`//// from http://www.opencores.org/lgpl.shtml ////`
60			`//// ////`
61			`//////////////////////////////////////////////////////////////////////`
62			`//`
63			`// CVS Revision History`
64			`//`
65			`// $Log: uart_fifo.v,v $`
66			`// Revision 1.3 2001/05/31 20:08:01 gorban`
67			`// FIFO changes and other corrections.`
68			`//`
69			`// Revision 1.3 2001/05/27 17:37:48 gorban`
70			`// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.`
71			`//`
72			`// Revision 1.2 2001/05/17 18:34:18 gorban`
73			`// First 'stable' release. Should be sythesizable now. Also added new header.`
74			`//`
75			`// Revision 1.0 2001-05-17 21:27:12+02 jacob`
76			`// Initial revision`
77			`//`
78			`//`
79
80			`include "timescale.v"
81			`include "uart_defines.v"
82
83			`module uart_fifo (clk,`
84			`wb_rst_i, data_in, data_out,`
85			`// Control signals`
86			`push, // push strobe, active high`
87			`pop, // pop strobe, active high`
88			`// status signals`
89			`underrun,`
90			`overrun,`
91			`count,`
92			`error_bit,`
93			`fifo_reset,`
94			`reset_status`
95			`);`
96
97
98			`// FIFO parameters`
99			parameter fifo_width = `UART_FIFO_WIDTH;
100			parameter fifo_depth = `UART_FIFO_DEPTH;
101			parameter fifo_pointer_w = `UART_FIFO_POINTER_W;
102			parameter fifo_counter_w = `UART_FIFO_COUNTER_W;
103
104			`input clk;`
105			`input wb_rst_i;`
106			`input push;`
107			`input pop;`
108			`input [fifo_width-1:0] data_in;`
109			`input fifo_reset;`
110			`input reset_status;`
111
112			`output [fifo_width-1:0] data_out;`
113			`output overrun;`
114			`output underrun;`
115			`output [fifo_counter_w-1:0] count;`
116			`output error_bit;`
117
118			`wire [fifo_width-1:0] data_out;`
119
120			`// FIFO itself`
121			`reg [fifo_width-1:0] fifo[fifo_depth-1:0];`
122
123			`// FIFO pointers`
124			`reg [fifo_pointer_w-1:0] top;`
125			`reg [fifo_pointer_w-1:0] bottom;`
126
127			`reg [fifo_counter_w-1:0] count;`
128			`reg overrun;`
129			`reg underrun;`
130
131			`// These registers and signals are to detect rise of of the signals.`
132			`// Not that it slows the maximum rate by 2, meaning you must reset the signals and then`
133			`// assert them again for the operation to repeat`
134			`// This is done to accomodate wait states`
135			`reg push_delay;`
136			`reg pop_delay;`
137
138			`wire push_rise = push_delay & push;`
139			`wire pop_rise = pop_delay & pop;`
140
141			`wire [fifo_pointer_w-1:0] top_plus_1 = top + 1;`
142
143			`always @(posedge clk or posedge wb_rst_i)`
144			`begin`
145			`if (wb_rst_i)`
146			`push_delay <= #1 1'b0;`
147			`else`
148			`push_delay <= #1 ~push;`
149			`end`
150
151			`always @(posedge clk or posedge wb_rst_i)`
152			`begin`
153			`if (wb_rst_i)`
154			`pop_delay <= #1 1'b0;`
155			`else`
156			`pop_delay <= #1 ~pop;`
157			`end`
158
159
160			`always @(posedge clk or posedge wb_rst_i) // synchronous FIFO`
161			`begin`
162			`if (wb_rst_i)`
163			`begin`
164			`top <= #1 0;`
165			`// bottom <= #1 1; igor`
166			`bottom <= #1 1'b0;`
167			`underrun <= #1 1'b0;`
168			`overrun <= #1 1'b0;`
169			`count <= #1 0;`
170			`fifo[0] <= #1 0;`
171			`fifo[1] <= #1 0;`
172			`fifo[2] <= #1 0;`
173			`fifo[3] <= #1 0;`
174			`fifo[4] <= #1 0;`
175			`fifo[5] <= #1 0;`
176			`fifo[6] <= #1 0;`
177			`fifo[7] <= #1 0;`
178			`fifo[8] <= #1 0;`
179			`fifo[9] <= #1 0;`
180			`fifo[10] <= #1 0;`
181			`fifo[11] <= #1 0;`
182			`fifo[12] <= #1 0;`
183			`fifo[13] <= #1 0;`
184			`fifo[14] <= #1 0;`
185			`fifo[15] <= #1 0;`
186			`end`
187			`else`
188			`if (fifo_reset) begin`
189			`top <= #1 0;`
190			`// bottom <= #1 1; igor`
191			`bottom <= #1 1'b0;`
192			`underrun <= #1 1'b0;`
193			`overrun <= #1 1'b0;`
194			`count <= #1 0;`
195			`end`
196			`else`
197			`if(reset_status)`
198			`begin`
199			`underrun <= #1 1'b0;`
200			`overrun <= #1 1'b0;`
201			`end`
202			`else`
203			`begin`
204			`case ({push_rise, pop_rise})`
205			`2'b00 : begin`
206			`underrun <= #1 1'b0;`
207			`// overrun <= #1 1'b0;// Igor Ko se postavita ostaneta aktivna tako dolgo, dokler se ne naredi read LSR registra`
208			`end`
209			`2'b10 : if (count==fifo_depth) // overrun condition`
210			`begin`
211			`overrun <= #1 1'b1;`
212			`underrun <= #1 1'b0;`
213			`end`
214			`else`
215			`begin`
216			`top <= #1 top_plus_1;`
217			`// fifo[top_plus_1] <= #1 data_in; igor`
218			`fifo[top] <= #1 data_in;`
219			`// overrun <= #1 0;// Igor Ko se postavita ostaneta aktivna tako dolgo, dokler se ne naredi read LSR registra`
220			`overrun <= #1 0;`
221			`count <= #1 count + 1;`
222			`end`
223			`2'b01 : if (~\|count)`
224			`begin`
225			`// overrun <= #1 1'b0; Igor Ko se postavita ostaneta aktivna tako dolgo, dokler se ne naredi read LSR registra`
226			`overrun <= #1 1'b0;`
227			`end`
228			`else`
229			`begin`
230			`bottom <= #1 bottom + 1;`
231			`// overrun <= #1 1'b0; Igor Ko se postavita ostaneta aktivna tako dolgo, dokler se ne naredi read LSR registra`
232			`overrun <= #1 1'b0;`
233			`count <= #1 count - 1;`
234			`end`
235			`2'b11 : begin`
236			`bottom <= #1 bottom + 1;`
237			`top <= #1 top_plus_1;`
238			`// fifo[top_plus_1] <= #1 data_in; igor`
239			`fifo[top] <= #1 data_in;`
240			`underrun <= #1 1'b0;`
241			`// overrun <= #1 1'b0; Igor Ko se postavita ostaneta aktivna tako dolgo, dokler se ne naredi read LSR registra`
242			`end`
243			`endcase`
244			`end`
245
246			`end // always`
247
248			`// please note though that data_out is only valid one clock after pop signal`
249			`assign data_out = fifo[bottom];`
250
251			`// Additional logic for detection of error conditions (parity and framing) inside the FIFO`
252			`// for the Line Status Register bit 7`
253
254			`wire [fifo_width-1:0] word0 = fifo[0];`
255			`wire [fifo_width-1:0] word1 = fifo[1];`
256			`wire [fifo_width-1:0] word2 = fifo[2];`
257			`wire [fifo_width-1:0] word3 = fifo[3];`
258			`wire [fifo_width-1:0] word4 = fifo[4];`
259			`wire [fifo_width-1:0] word5 = fifo[5];`
260			`wire [fifo_width-1:0] word6 = fifo[6];`
261			`wire [fifo_width-1:0] word7 = fifo[7];`
262
263			`wire [fifo_width-1:0] word8 = fifo[8];`
264			`wire [fifo_width-1:0] word9 = fifo[9];`
265			`wire [fifo_width-1:0] word10 = fifo[10];`
266			`wire [fifo_width-1:0] word11 = fifo[11];`
267			`wire [fifo_width-1:0] word12 = fifo[12];`
268			`wire [fifo_width-1:0] word13 = fifo[13];`
269			`wire [fifo_width-1:0] word14 = fifo[14];`
270			`wire [fifo_width-1:0] word15 = fifo[15];`
271
272			`// a 1 is returned if any of the error bits in the fifo is 1`
273			`assign error_bit = \|(word0[1:0] \| word1[1:0] \| word2[1:0] \| word3[1:0] \|`
274			`word4[1:0] \| word5[1:0] \| word6[1:0] \| word7[1:0] \|`
275			`word8[1:0] \| word9[1:0] \| word10[1:0] \| word11[1:0] \|`
276			`word12[1:0] \| word13[1:0] \| word14[1:0] \| word15[1:0] );`
277
278			`endmodule`