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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [uart16550/] [rtl/] [verilog-backup/] [uart_transmitter.v] - Blame information for rev 12

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  uart_transmitter.v                                          ////
////                                                              ////
////                                                              ////
////  This file is part of the "UART 16550 compatible" project    ////
////  http://www.opencores.org/cores/uart16550/                   ////
////                                                              ////
////  Documentation related to this project:                      ////
////  - http://www.opencores.org/cores/uart16550/                 ////
////                                                              ////
////  Projects compatibility:                                     ////
////  - WISHBONE                                                  ////
////  RS232 Protocol                                              ////
////  16550D uart (mostly supported)                              ////
////                                                              ////
////  Overview (main Features):                                   ////
////  UART core transmitter logic                                 ////
////                                                              ////
////  Known problems (limits):                                    ////
////  None known                                                  ////
////                                                              ////
////  To Do:                                                      ////
////  Thourough testing.                                          ////
////                                                              ////
////  Author(s):                                                  ////
////      - gorban@opencores.org                                  ////
////      - Jacob Gorban                                          ////
////                                                              ////
////  Created:        2001/05/12                                  ////
////  Last Updated:   2001/05/17                                  ////
////                  (See log for the revision history)          ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Jacob Gorban, gorban@opencores.org        ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: uart_transmitter.v,v $
// Revision 1.6  2001/06/23 11:21:48  gorban
// DL made 16-bit long. Fixed transmission/reception bugs.
//
// Revision 1.5  2001/06/02 14:28:14  gorban
// Fixed receiver and transmitter. Major bug fixed.
//
// Revision 1.4  2001/05/31 20:08:01  gorban
// FIFO changes and other corrections.
//
// Revision 1.3  2001/05/27 17:37:49  gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.2  2001/05/21 19:12:02  gorban
// Corrected some Linter messages.
//
// Revision 1.1  2001/05/17 18:34:18  gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0  2001-05-17 21:27:12+02  jacob
// Initial revision
//
//
 
`include "timescale.v"
`include "uart_defines.v"
 
module uart_transmitter (clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, stx_pad_o, state, tf_count, tx_reset);
 
input                           clk;
input                           wb_rst_i;
input   [7:0]                    lcr;
input                           tf_push;
input   [7:0]                    wb_dat_i;
input                           enable;
input                           tx_reset;
output                          stx_pad_o;
output  [2:0]                    state;
output  [`UART_FIFO_COUNTER_W-1:0]       tf_count;
 
reg     [2:0]    state;
reg     [4:0]    counter;
reg     [2:0]    bit_counter;   // counts the bits to be sent
reg     [6:0]    shift_out;      // output shift register
reg             stx_o_tmp;
reg             parity_xor;  // parity of the word
reg             tf_pop;
reg             bit_out;
 
// TX FIFO instance
//
// Transmitter FIFO signals
wire    [`UART_FIFO_WIDTH-1:0]   tf_data_in;
wire    [`UART_FIFO_WIDTH-1:0]   tf_data_out;
wire                            tf_push;
wire                            tf_underrun;
wire                            tf_overrun;
wire    [`UART_FIFO_COUNTER_W-1:0]       tf_count;
 
assign tf_data_in = wb_dat_i;
 
uart_fifo fifo_tx(      // error bit signal is not used in transmitter FIFO
        .clk(           clk             ),
        .wb_rst_i(      wb_rst_i        ),
        .data_in(       tf_data_in      ),
        .data_out(      tf_data_out     ),
        .push(          tf_push         ),
        .pop(           tf_pop          ),
        .underrun(      tf_underrun     ),
        .overrun(       tf_overrun      ),
        .count(         tf_count        ),
        .error_bit(),                 // Ta ni priklopljen. Prej je manjkal, dodal Igor
        .fifo_reset(    tx_reset        ),
        .reset_status(1'b0)
);
 
// TRANSMITTER FINAL STATE MACHINE
 
parameter s_idle        = 3'd0;
parameter s_send_start  = 3'd1;
parameter s_send_byte   = 3'd2;
parameter s_send_parity = 3'd3;
parameter s_send_stop   = 3'd4;
parameter s_pop_byte    = 3'd5;
 
always @(posedge clk or posedge wb_rst_i)
begin
  if (wb_rst_i)
  begin
        state       <= #1 s_idle;
        stx_o_tmp       <= #1 1'b1;
        counter   <= #1 5'b0;
        shift_out   <= #1 7'b0;
        bit_out     <= #1 1'b0;
        parity_xor  <= #1 1'b0;
        tf_pop      <= #1 1'b0;
        bit_counter <= #1 3'b0;
  end
  else
  if (enable)
  begin
        case (state)
        s_idle   :      if (~|tf_count) // if tf_count==0
                        begin
                                state <= #1 s_idle;
                                stx_o_tmp <= #1 1'b1;
                        end
                        else
                        begin
                                tf_pop <= #1 1'b0;
                                stx_o_tmp  <= #1 1'b1;
                                state  <= #1 s_pop_byte;
                        end
        s_pop_byte :    begin
                                tf_pop <= #1 1'b1;
                                case (lcr[/*`UART_LC_BITS*/1:0])  // number of bits in a word
                                2'b00 : begin
                                        bit_counter <= #1 3'b100;
                                        parity_xor  <= #1 ^tf_data_out[4:0];
                                     end
                                2'b01 : begin
                                        bit_counter <= #1 3'b101;
                                        parity_xor  <= #1 ^tf_data_out[5:0];
                                     end
                                2'b10 : begin
                                        bit_counter <= #1 3'b110;
                                        parity_xor  <= #1 ^tf_data_out[6:0];
                                     end
                                2'b11 : begin
                                        bit_counter <= #1 3'b111;
                                        parity_xor  <= #1 ^tf_data_out[7:0];
                                     end
                                endcase
                                {shift_out[6:0], bit_out} <= #1 tf_data_out;
                                state <= #1 s_send_start;
                        end
        s_send_start :  begin
                                tf_pop <= #1 1'b0;
                                if (~|counter)
                                        counter <= #1 5'b01111;
                                else
                                if (counter == 5'b00001)
                                begin
                                        counter <= #1 0;
                                        state <= #1 s_send_byte;
                                end
                                else
                                        counter <= #1 counter - 5'b00001;
                                stx_o_tmp <= #1 1'b0;
                        end
        s_send_byte :   begin
                                if (~|counter)
                                        counter <= #1 5'b01111;
                                else
                                if (counter == 5'b00001)
                                begin
                                        if (bit_counter > 3'b0)
                                        begin
                                                bit_counter <= #1 bit_counter - 1;
                                                {shift_out[5:0],bit_out  } <= #1 {shift_out[6:1], shift_out[0]};
                                                state <= #1 s_send_byte;
                                        end
                                        else   // end of byte
                                        if (~lcr[`UART_LC_PE])
                                        begin
                                                state <= #1 s_send_stop;
                                        end
                                        else
                                        begin
                                                case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]})
                                                2'b00:  bit_out <= #1 parity_xor;
                                                2'b01:  bit_out <= #1 1'b1;
                                                2'b10:  bit_out <= #1 ~parity_xor;
                                                2'b11:  bit_out <= #1 1'b0;
                                                endcase
                                                state <= #1 s_send_parity;
                                        end
                                        counter <= #1 0;
                                end
                                else
                                        counter <= #1 counter - 5'b00001;
                                stx_o_tmp <= #1 bit_out; // set output pin
                        end
        s_send_parity : begin
                                if (~|counter)
                                        counter <= #1 5'b01111;
                                else
                                if (counter == 5'b00001)
                                begin
                                        counter <= #1 4'b0;
                                        state <= #1 s_send_stop;
                                end
                                else
                                        counter <= #1 counter - 5'b00001;
                                stx_o_tmp <= #1 bit_out;
                        end
        s_send_stop :  begin
                                if (~|counter)
                                  begin
                                                casex ({lcr[`UART_LC_SB],lcr[`UART_LC_BITS]})
                                                3'b0xx:   counter <= #1 5'b01101;     // 1 stop bit ok igor
                                                3'b100:   counter <= #1 5'b10101;     // 1.5 stop bit
                                                3'b1xx:   counter <= #1 5'b11101;     // 2 stop bits
                                                endcase
                                        end
                                else
                                if (counter == 5'b00001)
                                begin
                                        counter <= #1 0;
                                        state <= #1 s_idle;
                                end
                                else
                                        counter <= #1 counter - 5'b00001;
                                stx_o_tmp <= #1 1'b1;
                        end
 
                default : // should never get here
                        state <= #1 s_idle;
        endcase
  end // end if enable
end // transmitter logic
 
assign stx_pad_o = lcr[`UART_LC_BC] ? 1'b0 : stx_o_tmp;    // Break condition
 
endmodule

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Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [uart16550/] [rtl/] [verilog-backup/] [uart_transmitter.v] - Blame information for rev 12

Line No.	Rev	Author	Line
1	12	xianfeng	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// uart_transmitter.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the "UART 16550 compatible" project ////`
7			`//// http://www.opencores.org/cores/uart16550/ ////`
8			`//// ////`
9			`//// Documentation related to this project: ////`
10			`//// - http://www.opencores.org/cores/uart16550/ ////`
11			`//// ////`
12			`//// Projects compatibility: ////`
13			`//// - WISHBONE ////`
14			`//// RS232 Protocol ////`
15			`//// 16550D uart (mostly supported) ////`
16			`//// ////`
17			`//// Overview (main Features): ////`
18			`//// UART core transmitter logic ////`
19			`//// ////`
20			`//// Known problems (limits): ////`
21			`//// None known ////`
22			`//// ////`
23			`//// To Do: ////`
24			`//// Thourough testing. ////`
25			`//// ////`
26			`//// Author(s): ////`
27			`//// - gorban@opencores.org ////`
28			`//// - Jacob Gorban ////`
29			`//// ////`
30			`//// Created: 2001/05/12 ////`
31			`//// Last Updated: 2001/05/17 ////`
32			`//// (See log for the revision history) ////`
33			`//// ////`
34			`//// ////`
35			`//////////////////////////////////////////////////////////////////////`
36			`//// ////`
37			`//// Copyright (C) 2000 Jacob Gorban, gorban@opencores.org ////`
38			`//// ////`
39			`//// This source file may be used and distributed without ////`
40			`//// restriction provided that this copyright statement is not ////`
41			`//// removed from the file and that any derivative work contains ////`
42			`//// the original copyright notice and the associated disclaimer. ////`
43			`//// ////`
44			`//// This source file is free software; you can redistribute it ////`
45			`//// and/or modify it under the terms of the GNU Lesser General ////`
46			`//// Public License as published by the Free Software Foundation; ////`
47			`//// either version 2.1 of the License, or (at your option) any ////`
48			`//// later version. ////`
49			`//// ////`
50			`//// This source is distributed in the hope that it will be ////`
51			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
52			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
53			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
54			`//// details. ////`
55			`//// ////`
56			`//// You should have received a copy of the GNU Lesser General ////`
57			`//// Public License along with this source; if not, download it ////`
58			`//// from http://www.opencores.org/lgpl.shtml ////`
59			`//// ////`
60			`//////////////////////////////////////////////////////////////////////`
61			`//`
62			`// CVS Revision History`
63			`//`
64			`// $Log: uart_transmitter.v,v $`
65			`// Revision 1.6 2001/06/23 11:21:48 gorban`
66			`// DL made 16-bit long. Fixed transmission/reception bugs.`
67			`//`
68			`// Revision 1.5 2001/06/02 14:28:14 gorban`
69			`// Fixed receiver and transmitter. Major bug fixed.`
70			`//`
71			`// Revision 1.4 2001/05/31 20:08:01 gorban`
72			`// FIFO changes and other corrections.`
73			`//`
74			`// Revision 1.3 2001/05/27 17:37:49 gorban`
75			`// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.`
76			`//`
77			`// Revision 1.2 2001/05/21 19:12:02 gorban`
78			`// Corrected some Linter messages.`
79			`//`
80			`// Revision 1.1 2001/05/17 18:34:18 gorban`
81			`// First 'stable' release. Should be sythesizable now. Also added new header.`
82			`//`
83			`// Revision 1.0 2001-05-17 21:27:12+02 jacob`
84			`// Initial revision`
85			`//`
86			`//`
87
88			`include "timescale.v"
89			`include "uart_defines.v"
90
91			`module uart_transmitter (clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, stx_pad_o, state, tf_count, tx_reset);`
92
93			`input clk;`
94			`input wb_rst_i;`
95			`input [7:0] lcr;`
96			`input tf_push;`
97			`input [7:0] wb_dat_i;`
98			`input enable;`
99			`input tx_reset;`
100			`output stx_pad_o;`
101			`output [2:0] state;`
102			output [`UART_FIFO_COUNTER_W-1:0] tf_count;
103
104			`reg [2:0] state;`
105			`reg [4:0] counter;`
106			`reg [2:0] bit_counter; // counts the bits to be sent`
107			`reg [6:0] shift_out; // output shift register`
108			`reg stx_o_tmp;`
109			`reg parity_xor; // parity of the word`
110			`reg tf_pop;`
111			`reg bit_out;`
112
113			`// TX FIFO instance`
114			`//`
115			`// Transmitter FIFO signals`
116			wire [`UART_FIFO_WIDTH-1:0] tf_data_in;
117			wire [`UART_FIFO_WIDTH-1:0] tf_data_out;
118			`wire tf_push;`
119			`wire tf_underrun;`
120			`wire tf_overrun;`
121			wire [`UART_FIFO_COUNTER_W-1:0] tf_count;
122
123			`assign tf_data_in = wb_dat_i;`
124
125			`uart_fifo fifo_tx( // error bit signal is not used in transmitter FIFO`
126			`.clk( clk ),`
127			`.wb_rst_i( wb_rst_i ),`
128			`.data_in( tf_data_in ),`
129			`.data_out( tf_data_out ),`
130			`.push( tf_push ),`
131			`.pop( tf_pop ),`
132			`.underrun( tf_underrun ),`
133			`.overrun( tf_overrun ),`
134			`.count( tf_count ),`
135			`.error_bit(), // Ta ni priklopljen. Prej je manjkal, dodal Igor`
136			`.fifo_reset( tx_reset ),`
137			`.reset_status(1'b0)`
138			`);`
139
140			`// TRANSMITTER FINAL STATE MACHINE`
141
142			`parameter s_idle = 3'd0;`
143			`parameter s_send_start = 3'd1;`
144			`parameter s_send_byte = 3'd2;`
145			`parameter s_send_parity = 3'd3;`
146			`parameter s_send_stop = 3'd4;`
147			`parameter s_pop_byte = 3'd5;`
148
149			`always @(posedge clk or posedge wb_rst_i)`
150			`begin`
151			`if (wb_rst_i)`
152			`begin`
153			`state <= #1 s_idle;`
154			`stx_o_tmp <= #1 1'b1;`
155			`counter <= #1 5'b0;`
156			`shift_out <= #1 7'b0;`
157			`bit_out <= #1 1'b0;`
158			`parity_xor <= #1 1'b0;`
159			`tf_pop <= #1 1'b0;`
160			`bit_counter <= #1 3'b0;`
161			`end`
162			`else`
163			`if (enable)`
164			`begin`
165			`case (state)`
166			`s_idle : if (~\|tf_count) // if tf_count==0`
167			`begin`
168			`state <= #1 s_idle;`
169			`stx_o_tmp <= #1 1'b1;`
170			`end`
171			`else`
172			`begin`
173			`tf_pop <= #1 1'b0;`
174			`stx_o_tmp <= #1 1'b1;`
175			`state <= #1 s_pop_byte;`
176			`end`
177			`s_pop_byte : begin`
178			`tf_pop <= #1 1'b1;`
179			case (lcr[/`UART_LC_BITS/1:0]) // number of bits in a word
180			`2'b00 : begin`
181			`bit_counter <= #1 3'b100;`
182			`parity_xor <= #1 ^tf_data_out[4:0];`
183			`end`
184			`2'b01 : begin`
185			`bit_counter <= #1 3'b101;`
186			`parity_xor <= #1 ^tf_data_out[5:0];`
187			`end`
188			`2'b10 : begin`
189			`bit_counter <= #1 3'b110;`
190			`parity_xor <= #1 ^tf_data_out[6:0];`
191			`end`
192			`2'b11 : begin`
193			`bit_counter <= #1 3'b111;`
194			`parity_xor <= #1 ^tf_data_out[7:0];`
195			`end`
196			`endcase`
197			`{shift_out[6:0], bit_out} <= #1 tf_data_out;`
198			`state <= #1 s_send_start;`
199			`end`
200			`s_send_start : begin`
201			`tf_pop <= #1 1'b0;`
202			`if (~\|counter)`
203			`counter <= #1 5'b01111;`
204			`else`
205			`if (counter == 5'b00001)`
206			`begin`
207			`counter <= #1 0;`
208			`state <= #1 s_send_byte;`
209			`end`
210			`else`
211			`counter <= #1 counter - 5'b00001;`
212			`stx_o_tmp <= #1 1'b0;`
213			`end`
214			`s_send_byte : begin`
215			`if (~\|counter)`
216			`counter <= #1 5'b01111;`
217			`else`
218			`if (counter == 5'b00001)`
219			`begin`
220			`if (bit_counter > 3'b0)`
221			`begin`
222			`bit_counter <= #1 bit_counter - 1;`
223			`{shift_out[5:0],bit_out } <= #1 {shift_out[6:1], shift_out[0]};`
224			`state <= #1 s_send_byte;`
225			`end`
226			`else // end of byte`
227			if (~lcr[`UART_LC_PE])
228			`begin`
229			`state <= #1 s_send_stop;`
230			`end`
231			`else`
232			`begin`
233			case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]})
234			`2'b00: bit_out <= #1 parity_xor;`
235			`2'b01: bit_out <= #1 1'b1;`
236			`2'b10: bit_out <= #1 ~parity_xor;`
237			`2'b11: bit_out <= #1 1'b0;`
238			`endcase`
239			`state <= #1 s_send_parity;`
240			`end`
241			`counter <= #1 0;`
242			`end`
243			`else`
244			`counter <= #1 counter - 5'b00001;`
245			`stx_o_tmp <= #1 bit_out; // set output pin`
246			`end`
247			`s_send_parity : begin`
248			`if (~\|counter)`
249			`counter <= #1 5'b01111;`
250			`else`
251			`if (counter == 5'b00001)`
252			`begin`
253			`counter <= #1 4'b0;`
254			`state <= #1 s_send_stop;`
255			`end`
256			`else`
257			`counter <= #1 counter - 5'b00001;`
258			`stx_o_tmp <= #1 bit_out;`
259			`end`
260			`s_send_stop : begin`
261			`if (~\|counter)`
262			`begin`
263			casex ({lcr[`UART_LC_SB],lcr[`UART_LC_BITS]})
264			`3'b0xx: counter <= #1 5'b01101; // 1 stop bit ok igor`
265			`3'b100: counter <= #1 5'b10101; // 1.5 stop bit`
266			`3'b1xx: counter <= #1 5'b11101; // 2 stop bits`
267			`endcase`
268			`end`
269			`else`
270			`if (counter == 5'b00001)`
271			`begin`
272			`counter <= #1 0;`
273			`state <= #1 s_idle;`
274			`end`
275			`else`
276			`counter <= #1 counter - 5'b00001;`
277			`stx_o_tmp <= #1 1'b1;`
278			`end`
279
280			`default : // should never get here`
281			`state <= #1 s_idle;`
282			`endcase`
283			`end // end if enable`
284			`end // transmitter logic`
285
286			assign stx_pad_o = lcr[`UART_LC_BC] ? 1'b0 : stx_o_tmp; // Break condition
287
288			`endmodule`