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URL https://opencores.org/ocsvn/or1k_soc_on_altera_embedded_dev_kit/or1k_soc_on_altera_embedded_dev_kit/trunk

Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [sim/] [bin/] [iver.cmd] - Blame information for rev 12

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Line No. Rev Author Line
1 12 xianfeng 
../../bench/CPUboard_tb.v
2 
../../bench/generic_pll/generic_pll.v
3 
../../bench/models/512Kx8.v
4 
../../bench/models/28f016s3/dp016s3.v
5 
../../bench/models/28f016s3/bwsvff.v
6 
../../bench/ATMEL_FLASH/flash_verilog/flash_verilog_w_wo_hold/AT26DFxxx.v
7 
 
8 
 
9 
../../rtl/wb_conmax/rtl/verilog/wb_conmax_master_if.v
10 
../../rtl/wb_conmax/rtl/verilog/wb_conmax_defines.v
11 
../../rtl/wb_conmax/rtl/verilog/wb_conmax_arb.v
12 
../../rtl/wb_conmax/rtl/verilog/wb_conmax_pri_enc.v
13 
../../rtl/wb_conmax/rtl/verilog/wb_conmax_top.v
14 
../../rtl/wb_conmax/rtl/verilog/wb_conmax_msel.v
15 
../../rtl/wb_conmax/rtl/verilog/wb_conmax_slave_if.v
16 
../../rtl/wb_conmax/rtl/verilog/wb_conmax_rf.v
17 
../../rtl/wb_conmax/rtl/verilog/wb_conmax_pri_dec.v
18 
 
19 
../../rtl/or1k_soc_top.v
20 
 
21 
../../rtl/rom_wb/rom_wb.v
22 
 
23 
../../rtl/uart16550/rtl/verilog/uart_top.v
24 
../../rtl/uart16550/rtl/verilog/uart_wb.v
25 
../../rtl/uart16550/rtl/verilog/uart_regs.v
26 
../../rtl/uart16550/rtl/verilog/raminfr.v
27 
../../rtl/uart16550/rtl/verilog/uart_defines.v
28 
../../rtl/uart16550/rtl/verilog/timescale.v
29 
../../rtl/uart16550/rtl/verilog/uart_rfifo.v
30 
../../rtl/uart16550/rtl/verilog/uart_debug_if.v
31 
../../rtl/uart16550/rtl/verilog/uart_tfifo.v
32 
../../rtl/uart16550/rtl/verilog/uart_receiver.v
33 
../../rtl/uart16550/rtl/verilog/uart_sync_flops.v
34 
../../rtl/uart16550/rtl/verilog/uart_transmitter.v
35 
 
36 
../../rtl/mem_if/rtl/verilog/mc_wb_if.v
37 
../../rtl/mem_if/rtl/verilog/mc_defines.v
38 
../../rtl/mem_if/rtl/verilog/mc_top.v
39 
../../rtl/mem_if/rtl/verilog/mc_cs_rf.v
40 
../../rtl/mem_if/rtl/verilog/mc_dp.v
41 
../../rtl/mem_if/rtl/verilog/mc_incn_r.v
42 
../../rtl/mem_if/rtl/verilog/mc_timing.v
43 
../../rtl/mem_if/rtl/verilog/mc_adr_sel.v
44 
../../rtl/mem_if/rtl/verilog/mc_mem_if.v
45 
../../rtl/mem_if/rtl/verilog/mc_obct.v
46 
../../rtl/mem_if/rtl/verilog/mc_obct_top.v
47 
../../rtl/mem_if/rtl/verilog/mc_refresh.v
48 
../../rtl/mem_if/rtl/verilog/mc_rf.v
49 
../../rtl/mem_if/rtl/verilog/mc_rd_fifo.v
50 
 
51 
../../rtl/or1200/rtl/verilog/or1200_reg2mem.v
52 
../../rtl/or1200/rtl/verilog/or1200_dpram_32x32.v
53 
../../rtl/or1200/rtl/verilog/or1200_wb_biu.v
54 
../../rtl/or1200/rtl/verilog/or1200_pm.v
55 
../../rtl/or1200/rtl/verilog/or1200_tpram_32x32.v
56 
../../rtl/or1200/rtl/verilog/or1200_gmultp2_32x32.v
57 
../../rtl/or1200/rtl/verilog/or1200_lsu.v
58 
../../rtl/or1200/rtl/verilog/or1200_mem2reg.v
59 
../../rtl/or1200/rtl/verilog/or1200_freeze.v
60 
../../rtl/or1200/rtl/verilog/or1200_cfgr.v
61 
../../rtl/or1200/rtl/verilog/or1200_defines.v
62 
../../rtl/or1200/rtl/verilog/or1200_xcv_ram32x8d.v
63 
../../rtl/or1200/rtl/verilog/or1200_except.v
64 
../../rtl/or1200/rtl/verilog/or1200_pic.v
65 
../../rtl/or1200/rtl/verilog/or1200_dc_tag.v
66 
../../rtl/or1200/rtl/verilog/or1200_rfram_generic.v
67 
../../rtl/or1200/rtl/verilog/or1200_sb_fifo.v
68 
../../rtl/or1200/rtl/verilog/or1200_dc_ram.v
69 
../../rtl/or1200/rtl/verilog/timescale.v
70 
../../rtl/or1200/rtl/verilog/or1200_spram_2048x32_bw.v
71 
../../rtl/or1200/rtl/verilog/or1200_dpram_256x32.v
72 
../../rtl/or1200/rtl/verilog/or1200_cpu.v
73 
../../rtl/or1200/rtl/verilog/or1200_ic_ram.v
74 
../../rtl/or1200/rtl/verilog/or1200_dc_fsm.v
75 
../../rtl/or1200/rtl/verilog/or1200_spram_32x24.v
76 
../../rtl/or1200/rtl/verilog/or1200_mult_mac.v
77 
../../rtl/or1200/rtl/verilog/or1200_spram_256x21.v
78 
../../rtl/or1200/rtl/verilog/or1200_genpc.v
79 
../../rtl/or1200/rtl/verilog/or1200_alu.v
80 
../../rtl/or1200/rtl/verilog/or1200_dmmu_top.v
81 
../../rtl/or1200/rtl/verilog/or1200_ic_tag.v
82 
../../rtl/or1200/rtl/verilog/or1200_ic_fsm.v
83 
../../rtl/or1200/rtl/verilog/or1200_spram_2048x8.v
84 
../../rtl/or1200/rtl/verilog/or1200_spram_1024x8.v
85 
../../rtl/or1200/rtl/verilog/or1200_ctrl.v
86 
../../rtl/or1200/rtl/verilog/or1200_spram_64x14.v
87 
../../rtl/or1200/rtl/verilog/or1200_qmem_top.v
88 
../../rtl/or1200/rtl/verilog/or1200_dmmu_tlb.v
89 
../../rtl/or1200/rtl/verilog/or1200_spram_1024x32_bw.v
90 
../../rtl/or1200/rtl/verilog/or1200_tt.v
91 
../../rtl/or1200/rtl/verilog/or1200_immu_top.v
92 
../../rtl/or1200/rtl/verilog/or1200_iwb_biu.v
93 
../../rtl/or1200/rtl/verilog/or1200_spram_1024x32.v
94 
../../rtl/or1200/rtl/verilog/or1200_spram_128x32.v
95 
../../rtl/or1200/rtl/verilog/or1200_immu_tlb.v
96 
../../rtl/or1200/rtl/verilog/or1200_operandmuxes.v
97 
../../rtl/or1200/rtl/verilog/or1200_dc_top.v
98 
../../rtl/or1200/rtl/verilog/or1200_sprs.v
99 
../../rtl/or1200/rtl/verilog/or1200_sb.v
100 
../../rtl/or1200/rtl/verilog/or1200_wbmux.v
101 
../../rtl/or1200/rtl/verilog/or1200_spram_64x24.v
102 
../../rtl/or1200/rtl/verilog/or1200_spram_512x20.v
103 
../../rtl/or1200/rtl/verilog/or1200_du.v
104 
../../rtl/or1200/rtl/verilog/or1200_if.v
105 
../../rtl/or1200/rtl/verilog/or1200_ic_top.v
106 
../../rtl/or1200/rtl/verilog/or1200_spram_2048x32.v
107 
../../rtl/or1200/rtl/verilog/or1200_amultp2_32x32.v
108 
../../rtl/or1200/rtl/verilog/or1200_spram_64x22.v
109 
../../rtl/or1200/rtl/verilog/or1200_rf.v
110 
../../rtl/or1200/rtl/verilog/or1200_top.v
111 
../../rtl/flash_sram/flash_top.v
112 
../../rtl/flash_sram/sram_top.v
113 
 
114 
../../rtl/gpio/rtl/verilog/gpio_defines.v
115 
../../rtl/gpio/rtl/verilog/gpio_top.v
116 
 
117 
../../rtl/spi/rtl/verilog/spi_defines.v
118 
../../rtl/spi/rtl/verilog/spi_shift.v
119 
../../rtl/spi/rtl/verilog/spi_clgen.v
120 
../../rtl/spi/rtl/verilog/spi_top.v
121 
../../rtl/spi/rtl/verilog/timescale.v
122 
 
123 
../../rtl/ethernet/rtl/verilog/eth_defines.v
124 
../../rtl/ethernet/rtl/verilog/eth_register.v
125 
../../rtl/ethernet/rtl/verilog/eth_receivecontrol.v
126 
../../rtl/ethernet/rtl/verilog/eth_fifo.v
127 
../../rtl/ethernet/rtl/verilog/eth_miim.v
128 
../../rtl/ethernet/rtl/verilog/xilinx_dist_ram_16x32.v
129 
../../rtl/ethernet/rtl/verilog/eth_txstatem.v
130 
../../rtl/ethernet/rtl/verilog/eth_registers.v
131 
../../rtl/ethernet/rtl/verilog/eth_wishbone.v
132 
../../rtl/ethernet/rtl/verilog/eth_random.v
133 
../../rtl/ethernet/rtl/verilog/eth_crc.v
134 
../../rtl/ethernet/rtl/verilog/eth_transmitcontrol.v
135 
../../rtl/ethernet/rtl/verilog/eth_clockgen.v
136 
../../rtl/ethernet/rtl/verilog/timescale.v
137 
../../rtl/ethernet/rtl/verilog/eth_shiftreg.v
138 
../../rtl/ethernet/rtl/verilog/eth_rxcounters.v
139 
../../rtl/ethernet/rtl/verilog/eth_outputcontrol.v
140 
../../rtl/ethernet/rtl/verilog/eth_maccontrol.v
141 
../../rtl/ethernet/rtl/verilog/eth_rxaddrcheck.v
142 
../../rtl/ethernet/rtl/verilog/eth_rxstatem.v
143 
../../rtl/ethernet/rtl/verilog/eth_txethmac.v
144 
../../rtl/ethernet/rtl/verilog/eth_spram_256x32.v
145 
../../rtl/ethernet/rtl/verilog/eth_top.v
146 
../../rtl/ethernet/rtl/verilog/eth_macstatus.v
147 
../../rtl/ethernet/rtl/verilog/eth_cop.v
148 
../../rtl/ethernet/rtl/verilog/eth_rxethmac.v
149 
../../rtl/ethernet/rtl/verilog/eth_txcounters.v
150 
 
151 
-y ../../bench
152 
-y ../../bench/models
153 
-y ../../bench/models/28f016s3
154 
-y ../../rtl/wb_conmax/rtl/verilog
155 
-y ../../rtl
156 
-y ../../rtl/rom_wb
157 
-y ../../rtl/or1200/rtl/verilog
158 
-y ../../rtl/flash_sram
159 
 

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