OpenCores
URL https://opencores.org/ocsvn/or1k_soc_on_altera_embedded_dev_kit/or1k_soc_on_altera_embedded_dev_kit/trunk

Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [sim/] [bin/] [iver.cmd.new] - Blame information for rev 12

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 12 xianfeng
../../bench/CPUboard_tb.v
2
../../bench/generic_pll/generic_pll.v
3
../../bench/models/512Kx8.v
4
../../bench/models/28f016s3/dp016s3.v
5
../../bench/models/28f016s3/bwsvff.v
6
 
7
../../rtl/wb_conmax/rtl/verilog/wb_conmax_master_if.v
8
../../rtl/wb_conmax/rtl/verilog/wb_conmax_defines.v
9
../../rtl/wb_conmax/rtl/verilog/wb_conmax_arb.v
10
../../rtl/wb_conmax/rtl/verilog/wb_conmax_pri_enc.v
11
../../rtl/wb_conmax/rtl/verilog/wb_conmax_top.v
12
../../rtl/wb_conmax/rtl/verilog/wb_conmax_msel.v
13
../../rtl/wb_conmax/rtl/verilog/wb_conmax_slave_if.v
14
../../rtl/wb_conmax/rtl/verilog/wb_conmax_rf.v
15
../../rtl/wb_conmax/rtl/verilog/wb_conmax_pri_dec.v
16
 
17
../../rtl/or1k_sco_top.v
18
 
19
../../rtl/rom_wb/rom_wb.v
20
 
21
../../rtl/mem_if/rtl/verilog/mc_wb_if.v
22
../../rtl/mem_if/rtl/verilog/mc_defines.v
23
../../rtl/mem_if/rtl/verilog/mc_top.v
24
../../rtl/mem_if/rtl/verilog/mc_cs_rf.v
25
../../rtl/mem_if/rtl/verilog/mc_dp.v
26
../../rtl/mem_if/rtl/verilog/mc_incn_r.v
27
../../rtl/mem_if/rtl/verilog/mc_timing.v
28
../../rtl/mem_if/rtl/verilog/mc_adr_sel.v
29
../../rtl/mem_if/rtl/verilog/mc_mem_if.v
30
../../rtl/mem_if/rtl/verilog/mc_obct.v
31
../../rtl/mem_if/rtl/verilog/mc_obct_top.v
32
../../rtl/mem_if/rtl/verilog/mc_refresh.v
33
../../rtl/mem_if/rtl/verilog/mc_rf.v
34
../../rtl/mem_if/rtl/verilog/mc_rd_fifo.v
35
 
36
../../rtl/or1200/rtl/verilog/or1200_reg2mem.v
37
../../rtl/or1200/rtl/verilog/or1200_dpram_32x32.v
38
../../rtl/or1200/rtl/verilog/or1200_wb_biu.v
39
../../rtl/or1200/rtl/verilog/or1200_pm.v
40
../../rtl/or1200/rtl/verilog/or1200_tpram_32x32.v
41
../../rtl/or1200/rtl/verilog/or1200_gmultp2_32x32.v
42
../../rtl/or1200/rtl/verilog/or1200_lsu.v
43
../../rtl/or1200/rtl/verilog/or1200_mem2reg.v
44
../../rtl/or1200/rtl/verilog/or1200_freeze.v
45
../../rtl/or1200/rtl/verilog/or1200_cfgr.v
46
../../rtl/or1200/rtl/verilog/or1200_defines.v
47
../../rtl/or1200/rtl/verilog/or1200_xcv_ram32x8d.v
48
../../rtl/or1200/rtl/verilog/or1200_except.v
49
../../rtl/or1200/rtl/verilog/or1200_pic.v
50
../../rtl/or1200/rtl/verilog/or1200_dc_tag.v
51
../../rtl/or1200/rtl/verilog/or1200_rfram_generic.v
52
../../rtl/or1200/rtl/verilog/or1200_sb_fifo.v
53
../../rtl/or1200/rtl/verilog/or1200_dc_ram.v
54
../../rtl/or1200/rtl/verilog/timescale.v
55
../../rtl/or1200/rtl/verilog/or1200_spram_2048x32_bw.v
56
../../rtl/or1200/rtl/verilog/or1200_dpram_256x32.v
57
../../rtl/or1200/rtl/verilog/or1200_cpu.v
58
../../rtl/or1200/rtl/verilog/or1200_ic_ram.v
59
../../rtl/or1200/rtl/verilog/or1200_dc_fsm.v
60
../../rtl/or1200/rtl/verilog/or1200_spram_32x24.v
61
../../rtl/or1200/rtl/verilog/or1200_mult_mac.v
62
../../rtl/or1200/rtl/verilog/or1200_spram_256x21.v
63
../../rtl/or1200/rtl/verilog/or1200_genpc.v
64
../../rtl/or1200/rtl/verilog/or1200_alu.v
65
../../rtl/or1200/rtl/verilog/or1200_dmmu_top.v
66
../../rtl/or1200/rtl/verilog/or1200_ic_tag.v
67
../../rtl/or1200/rtl/verilog/or1200_ic_fsm.v
68
../../rtl/or1200/rtl/verilog/or1200_spram_2048x8.v
69
../../rtl/or1200/rtl/verilog/or1200_spram_1024x8.v
70
../../rtl/or1200/rtl/verilog/or1200_ctrl.v
71
../../rtl/or1200/rtl/verilog/or1200_spram_64x14.v
72
../../rtl/or1200/rtl/verilog/or1200_qmem_top.v
73
../../rtl/or1200/rtl/verilog/or1200_dmmu_tlb.v
74
../../rtl/or1200/rtl/verilog/or1200_spram_1024x32_bw.v
75
../../rtl/or1200/rtl/verilog/or1200_tt.v
76
../../rtl/or1200/rtl/verilog/or1200_immu_top.v
77
../../rtl/or1200/rtl/verilog/or1200_iwb_biu.v
78
../../rtl/or1200/rtl/verilog/or1200_spram_1024x32.v
79
../../rtl/or1200/rtl/verilog/or1200_spram_128x32.v
80
../../rtl/or1200/rtl/verilog/or1200_immu_tlb.v
81
../../rtl/or1200/rtl/verilog/or1200_operandmuxes.v
82
../../rtl/or1200/rtl/verilog/or1200_dc_top.v
83
../../rtl/or1200/rtl/verilog/or1200_sprs.v
84
../../rtl/or1200/rtl/verilog/or1200_sb.v
85
../../rtl/or1200/rtl/verilog/or1200_wbmux.v
86
../../rtl/or1200/rtl/verilog/or1200_spram_64x24.v
87
../../rtl/or1200/rtl/verilog/or1200_spram_512x20.v
88
../../rtl/or1200/rtl/verilog/or1200_du.v
89
../../rtl/or1200/rtl/verilog/or1200_if.v
90
../../rtl/or1200/rtl/verilog/or1200_ic_top.v
91
../../rtl/or1200/rtl/verilog/or1200_spram_2048x32.v
92
../../rtl/or1200/rtl/verilog/or1200_amultp2_32x32.v
93
../../rtl/or1200/rtl/verilog/or1200_spram_64x22.v
94
../../rtl/or1200/rtl/verilog/or1200_rf.v
95
../../rtl/or1200/rtl/verilog/or1200_top.v
96
../../rtl/flash_sram/flash_top.v
97
../../rtl/flash_sram/sram_top.v
98
 
99
 
100
 
101
-y ../../bench
102
-y ../../bench/models
103
-y ../../bench/models/28f016s3
104
-y ../../rtl/wb_conmax/rtl/verilog
105
-y ../../rtl
106
-y ../../rtl/rom_wb
107
-y ../../rtl/or1200/rtl/verilog
108
-y ../../rtl/flash_sram
109
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.