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xianfeng |
/* or32_selftest.c -- JTAG protocol bridge between GDB and Advanced debug module.
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Copyright(C) 2001 Marko Mlinar, markom@opencores.org
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Code for TCP/IP copied from gdb, by Chris Ziomkowski
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21 |
xianfeng |
Refactoring and USB support by Nathan Yawn, (C) 2008-2010
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12 |
xianfeng |
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This file contains functions which perform high-level transactions
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on a JTAG chain and debug unit, such as setting a value in the TAP IR
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or doing a burst write through the wishbone module of the debug unit.
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It uses the protocol for the Advanced Debug Interface (adv_dbg_if).
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <stdio.h>
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#include <stdlib.h> // for exit()
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#include "or32_selftest.h"
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#include "dbg_api.h"
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#include "errcodes.h"
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// Define your system parameters here
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//#define HAS_CPU1 // stall cpu1 (as well as cpu0)
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//#define HAS_MEMORY_CONTROLLER // init the SDRAM controller
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#define MC_BASE_ADDR 0x93000000
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#define SDRAM_BASE 0x00000000
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//#define SDRAM_SIZE 0x04000000
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#define SDRAM_SIZE 0x400
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#define SRAM_BASE 0x00000000
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#define SRAM_SIZE 0x04000000
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#define FLASH_BASE_ADDR 0xf0000000
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// Define the tests to be performed here
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#define TEST_SRAM
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//#define TEST_SDRAM
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#define TEST_OR1K
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//#define TEST_8051 // run a test on an 8051 on CPU1
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// Defines which depend on user-defined values, don't change these
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#define FLASH_BAR_VAL FLASH_BASE_ADDR
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#define SDRAM_BASE_ADDR SDRAM_BASE
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#define SDRAM_BAR_VAL SDRAM_BASE_ADDR
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#define SDRAM_AMR_VAL (~(SDRAM_SIZE -1))
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#define CHECK(x) check(__FILE__, __LINE__, (x))
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void check(char *fn, int l, int i);
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void check(char *fn, int l, int i) {
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if (i != 0) {
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fprintf(stderr, "%s:%d: Jtag error %d occured; exiting.\n", fn, l, i);
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exit(1);
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}
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}
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////////////////////////////////////////////////////////////
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// Self-test functions
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///////////////////////////////////////////////////////////
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int dbg_test()
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{
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int success;
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success = stall_cpus();
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if(success == APP_ERR_NONE) {
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#ifdef HAS_MEMORY_CONTROLLER
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// Init the memory contloller
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init_mc();
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// Init the SRAM addresses in the MC
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init_sram();
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#endif
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#ifdef TEST_SDRAM
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success |= test_sdram();
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success |= test_sdram_2();
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#endif
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#ifdef TEST_SRAM
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success |= test_sram();
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#endif
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#ifdef TEST_OR1K
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success |= test_or1k_cpu0();
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#endif
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#if ((defined TEST_8051) && (defined HAS_CPU1))
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success |= test_8051_cpu1();
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#endif
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return success;
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}
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return APP_ERR_TEST_FAIL;
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}
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int stall_cpus(void)
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{
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unsigned char stalled;
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#ifdef HAS_CPU1
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printf("Stall 8051 - ");
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CHECK(dbg_cpu1_write_reg(0, 0x01)); // stall 8051
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#endif
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printf("Stall or1k - ");
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CHECK(dbg_cpu0_write_ctrl(0, 0x01)); // stall or1k
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#ifdef HAS_CPU1
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CHECK(dbg_cpu1_read_ctrl(0, &stalled));
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if (!(stalled & 0x1)) {
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printf("8051 is not stalled!\n"); // check stall 8051
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return APP_ERR_TEST_FAIL;
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}
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#endif
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CHECK(dbg_cpu0_read_ctrl(0, &stalled));
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if (!(stalled & 0x1)) {
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printf("or1k is not stalled!\n"); // check stall or1k
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return APP_ERR_TEST_FAIL;
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}
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printf("CPU(s) stalled.\n");
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return APP_ERR_NONE;
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}
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void init_mc(void)
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{
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unsigned long insn;
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printf("Initialize Memory Controller (SDRAM)\n");
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CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_BAR_0, FLASH_BAR_VAL & 0xffff0000));
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CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_AMR_0, FLASH_AMR_VAL & 0xffff0000));
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CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_WTR_0, FLASH_WTR_VAL));
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CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_RTR_0, FLASH_RTR_VAL));
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CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_OSR, 0x40000000));
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CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_BAR_4, SDRAM_BAR_VAL & 0xffff0000));
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CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_AMR_4, SDRAM_AMR_VAL & 0xffff0000));
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CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_CCR_4, 0x00bf0005));
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CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_RATR, SDRAM_RATR_VAL));
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CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_RCDR, SDRAM_RCDR_VAL));
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CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_RCTR, SDRAM_RCTR_VAL));
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CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_REFCTR, SDRAM_REFCTR_VAL));
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CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_PTR, SDRAM_PTR_VAL));
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CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_RRDR, SDRAM_RRDR_VAL));
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CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_RIR, SDRAM_RIR_VAL));
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CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_OSR, 0x5e000000));
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CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x5e000000));
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CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_OSR, 0x6e000000));
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CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x6e000000));
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CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x6e000000));
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CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x6e000000));
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CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x6e000000));
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CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x6e000000));
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CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x6e000000));
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CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x6e000000));
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CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x6e000000));
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CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_OSR, 0x7e000033));
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CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x7e000033));
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CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_CCR_4, 0xc0bf0005));
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CHECK(dbg_wb_read32(MC_BASE_ADDR+MC_CCR_4, &insn));
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printf("expected %x, read %lx\n", 0xc0bf0005, insn);
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}
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void init_sram(void)
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{
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// SRAM initialized to 0x40000000
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printf("Initialize Memory Controller (SRAM)\n");
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CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_BAR_1, SRAM_BASE & 0xffff0000));
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CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_AMR_1, ~(SRAM_SIZE - 1) & 0xffff0000));
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CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_CCR_1, 0xc020001f));
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}
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int test_sdram(void)
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{
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unsigned long insn;
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unsigned long i;
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unsigned long data4_out[0x08];
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unsigned long data4_in[0x08];
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unsigned short data2_out[0x10];
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unsigned short data2_in[0x10];
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unsigned char data1_out[0x20];
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unsigned char data1_in[0x20];
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printf("Start SDRAM WR\n");
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for (i=0x10; i<(SDRAM_SIZE+SDRAM_BASE); i=i<<1) {
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//printf("0x%x: 0x%x\n", SDRAM_BASE+i, i);
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CHECK(dbg_wb_write32(SDRAM_BASE+i, i));
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}
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printf("Start SDRAM RD\n");
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for (i=0x10; i<(SDRAM_SIZE+SDRAM_BASE); i=i<<1) {
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CHECK(dbg_wb_read32(SDRAM_BASE+i, &insn));
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//printf("0x%x: 0x%x\n", SDRAM_BASE+i, insn);
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if (i != insn) {
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printf("SDRAM test FAIL\n");
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return APP_ERR_TEST_FAIL;
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}
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}
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printf("32-bit block write from %x to %x\n", SDRAM_BASE, SDRAM_BASE + 0x20);
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for (i=0; i<(0x20/4); i++) {
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data4_out[i] = data4_in[i] = ((4*i+3)<<24) | ((4*i+2)<<16) | ((4*i+1)<<8) | (4*i);
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//printf("data_out = %0x\n", data4_out[i]);
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}
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//printf("Press a key for write\n"); getchar();
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CHECK(dbg_wb_write_block32(SDRAM_BASE, &data4_out[0], 0x20));
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// 32-bit block read is used for checking
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printf("32-bit block read from %x to %x\n", SDRAM_BASE, SDRAM_BASE + 0x20);
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CHECK(dbg_wb_read_block32(SDRAM_BASE, &data4_out[0], 0x20));
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for (i=0; i<(0x20/4); i++) {
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//printf("0x%x: 0x%x\n", SDRAM_BASE+(i*4), data_out[i]);
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if (data4_in[i] != data4_out[i]) {
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printf("SDRAM data differs. Expected: 0x%0lx, read: 0x%0lx\n", data4_in[i], data4_out[i]);
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return APP_ERR_TEST_FAIL;
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}
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}
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printf("16-bit block write from %x to %x\n", SDRAM_BASE, SDRAM_BASE + 0x20);
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for (i=0; i<(0x20/2); i++) {
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data2_out[i] = data2_in[i] = ((4*i+1)<<8) | (4*i);
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//printf("data_out = %0x\n", data_out[i]);
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}
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CHECK(dbg_wb_write_block16(SDRAM_BASE, &data2_out[0], 0x20));
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// 16-bit block read is used for checking
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printf("16-bit block read from %x to %x\n", SDRAM_BASE, SDRAM_BASE + 0x20);
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CHECK(dbg_wb_read_block16(SDRAM_BASE, &data2_out[0], 0x20));
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for (i=0; i<(0x20/2); i++) {
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//printf("0x%x: 0x%x\n", SDRAM_BASE+(i*4), data_out[i]);
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if (data2_in[i] != data2_out[i]) {
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printf("SDRAM data differs. Expected: 0x%0x, read: 0x%0x\n", data2_in[i], data2_out[i]);
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return APP_ERR_TEST_FAIL;
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}
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| 261 |
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}
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| 262 |
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| 263 |
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printf("8-bit block write from %x to %x\n", SDRAM_BASE, SDRAM_BASE + 0x20);
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for (i=0; i<(0x20/1); i++) {
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data1_out[i] = data1_in[i] = (4*i);
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| 266 |
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//printf("data_out = %0x\n", data_out[i]);
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}
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| 268 |
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CHECK(dbg_wb_write_block8(SDRAM_BASE, &data1_out[0], 0x20));
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| 270 |
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// 32-bit block read is used for checking
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printf("8-bit block read from %x to %x\n", SDRAM_BASE, SDRAM_BASE + 0x20);
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| 272 |
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CHECK(dbg_wb_read_block8(SDRAM_BASE, &data1_out[0], 0x20));
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| 273 |
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for (i=0; i<(0x20/1); i++) {
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| 274 |
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//printf("0x%x: 0x%x\n", SDRAM_BASE+(i*4), data_out[i]);
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| 275 |
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if (data1_in[i] != data1_out[i]) {
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| 276 |
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printf("SDRAM data differs. Expected: 0x%0x, read: 0x%0x\n", data1_in[i], data1_out[i]);
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| 277 |
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return APP_ERR_TEST_FAIL;
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| 278 |
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}
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| 279 |
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}
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| 280 |
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| 281 |
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printf("SDRAM OK!\n");
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| 282 |
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return APP_ERR_NONE;
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| 283 |
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}
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| 284 |
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| 285 |
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| 286 |
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int test_sdram_2(void)
|
| 287 |
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{
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| 288 |
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unsigned long insn;
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| 289 |
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| 290 |
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printf("SDRAM test 2: \n");
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| 291 |
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CHECK(dbg_wb_write32(SDRAM_BASE+0x00, 0x12345678));
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| 292 |
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CHECK(dbg_wb_read32(SDRAM_BASE+0x00, &insn));
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| 293 |
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printf("expected %x, read %lx\n", 0x12345678, insn);
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| 294 |
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if (insn != 0x12345678) return APP_ERR_TEST_FAIL;
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| 295 |
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| 296 |
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CHECK(dbg_wb_write32(SDRAM_BASE+0x0000, 0x11112222));
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| 297 |
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CHECK(dbg_wb_read32(SDRAM_BASE+0x0000, &insn));
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| 298 |
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printf("expected %x, read %lx\n", 0x11112222, insn);
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| 299 |
|
|
if (insn != 0x11112222) return APP_ERR_TEST_FAIL;
|
| 300 |
|
|
|
| 301 |
|
|
CHECK(dbg_wb_write32(SDRAM_BASE+0x0004, 0x33334444));
|
| 302 |
|
|
CHECK(dbg_wb_write32(SDRAM_BASE+0x0008, 0x55556666));
|
| 303 |
|
|
CHECK(dbg_wb_write32(SDRAM_BASE+0x000c, 0x77778888));
|
| 304 |
|
|
CHECK(dbg_wb_write32(SDRAM_BASE+0x0010, 0x9999aaaa));
|
| 305 |
|
|
CHECK(dbg_wb_write32(SDRAM_BASE+0x0014, 0xbbbbcccc));
|
| 306 |
|
|
CHECK(dbg_wb_write32(SDRAM_BASE+0x0018, 0xddddeeee));
|
| 307 |
|
|
CHECK(dbg_wb_write32(SDRAM_BASE+0x001c, 0xffff0000));
|
| 308 |
|
|
CHECK(dbg_wb_write32(SDRAM_BASE+0x0020, 0xdeadbeef));
|
| 309 |
|
|
|
| 310 |
|
|
CHECK(dbg_wb_read32(SDRAM_BASE+0x0000, &insn));
|
| 311 |
|
|
printf("expected %x, read %lx\n", 0x11112222, insn);
|
| 312 |
|
|
CHECK(dbg_wb_read32(SDRAM_BASE+0x0004, &insn));
|
| 313 |
|
|
printf("expected %x, read %lx\n", 0x33334444, insn);
|
| 314 |
|
|
CHECK(dbg_wb_read32(SDRAM_BASE+0x0008, &insn));
|
| 315 |
|
|
printf("expected %x, read %lx\n", 0x55556666, insn);
|
| 316 |
|
|
CHECK(dbg_wb_read32(SDRAM_BASE+0x000c, &insn));
|
| 317 |
|
|
printf("expected %x, read %lx\n", 0x77778888, insn);
|
| 318 |
|
|
CHECK(dbg_wb_read32(SDRAM_BASE+0x0010, &insn));
|
| 319 |
|
|
printf("expected %x, read %lx\n", 0x9999aaaa, insn);
|
| 320 |
|
|
CHECK(dbg_wb_read32(SDRAM_BASE+0x0014, &insn));
|
| 321 |
|
|
printf("expected %x, read %lx\n", 0xbbbbcccc, insn);
|
| 322 |
|
|
CHECK(dbg_wb_read32(SDRAM_BASE+0x0018, &insn));
|
| 323 |
|
|
printf("expected %x, read %lx\n", 0xddddeeee, insn);
|
| 324 |
|
|
CHECK(dbg_wb_read32(SDRAM_BASE+0x001c, &insn));
|
| 325 |
|
|
printf("expected %x, read %lx\n", 0xffff0000, insn);
|
| 326 |
|
|
CHECK(dbg_wb_read32(SDRAM_BASE+0x0020, &insn));
|
| 327 |
|
|
printf("expected %x, read %lx\n", 0xdeadbeef, insn);
|
| 328 |
|
|
|
| 329 |
|
|
if (insn != 0xdeadbeef) {
|
| 330 |
|
|
printf("SDRAM test 2 FAILED\n");
|
| 331 |
|
|
return APP_ERR_TEST_FAIL;
|
| 332 |
|
|
}
|
| 333 |
|
|
else
|
| 334 |
|
|
printf("SDRAM test 2 passed\n");
|
| 335 |
|
|
|
| 336 |
|
|
return APP_ERR_NONE;
|
| 337 |
|
|
}
|
| 338 |
|
|
|
| 339 |
|
|
|
| 340 |
|
|
int test_sram(void)
|
| 341 |
|
|
{
|
| 342 |
|
|
//unsigned long insn;
|
| 343 |
|
|
unsigned long ins;
|
| 344 |
|
|
unsigned long insn[9];
|
| 345 |
|
|
insn[0] = 0x11112222;
|
| 346 |
|
|
insn[1] = 0x33334444;
|
| 347 |
|
|
insn[2] = 0x55556666;
|
| 348 |
|
|
insn[3] = 0x77778888;
|
| 349 |
|
|
insn[4] = 0x9999aaaa;
|
| 350 |
|
|
insn[5] = 0xbbbbcccc;
|
| 351 |
|
|
insn[6] = 0xddddeeee;
|
| 352 |
|
|
insn[7] = 0xffff0000;
|
| 353 |
|
|
insn[8] = 0xdedababa;
|
| 354 |
|
|
|
| 355 |
|
|
printf("SRAM test: \n");
|
| 356 |
|
|
//dbg_wb_write_block32(0x0, insn, 9);
|
| 357 |
|
|
|
| 358 |
|
|
CHECK(dbg_wb_write32(SRAM_BASE+0x0000, 0x11112222));
|
| 359 |
|
|
CHECK(dbg_wb_write32(SRAM_BASE+0x0004, 0x33334444));
|
| 360 |
|
|
CHECK(dbg_wb_write32(SRAM_BASE+0x0008, 0x55556666));
|
| 361 |
|
|
CHECK(dbg_wb_write32(SRAM_BASE+0x000c, 0x77778888));
|
| 362 |
|
|
CHECK(dbg_wb_write32(SRAM_BASE+0x0010, 0x9999aaaa));
|
| 363 |
|
|
CHECK(dbg_wb_write32(SRAM_BASE+0x0014, 0xbbbbcccc));
|
| 364 |
|
|
CHECK(dbg_wb_write32(SRAM_BASE+0x0018, 0xddddeeee));
|
| 365 |
|
|
CHECK(dbg_wb_write32(SRAM_BASE+0x001c, 0xffff0000));
|
| 366 |
|
|
CHECK(dbg_wb_write32(SRAM_BASE+0x0020, 0xdedababa));
|
| 367 |
|
|
|
| 368 |
|
|
|
| 369 |
|
|
CHECK(dbg_wb_read32(SRAM_BASE+0x0000, &ins));
|
| 370 |
|
|
printf("expected %x, read %lx\n", 0x11112222, ins);
|
| 371 |
|
|
CHECK(dbg_wb_read32(SRAM_BASE+0x0004, &ins));
|
| 372 |
|
|
printf("expected %x, read %lx\n", 0x33334444, ins);
|
| 373 |
|
|
CHECK(dbg_wb_read32(SRAM_BASE+0x0008, &ins));
|
| 374 |
|
|
printf("expected %x, read %lx\n", 0x55556666, ins);
|
| 375 |
|
|
CHECK(dbg_wb_read32(SRAM_BASE+0x000c, &ins));
|
| 376 |
|
|
printf("expected %x, read %lx\n", 0x77778888, ins);
|
| 377 |
|
|
CHECK(dbg_wb_read32(SRAM_BASE+0x0010, &ins));
|
| 378 |
|
|
printf("expected %x, read %lx\n", 0x9999aaaa, ins);
|
| 379 |
|
|
CHECK(dbg_wb_read32(SRAM_BASE+0x0014, &ins));
|
| 380 |
|
|
printf("expected %x, read %lx\n", 0xbbbbcccc, ins);
|
| 381 |
|
|
CHECK(dbg_wb_read32(SRAM_BASE+0x0018, &ins));
|
| 382 |
|
|
printf("expected %x, read %lx\n", 0xddddeeee, ins);
|
| 383 |
|
|
CHECK(dbg_wb_read32(SRAM_BASE+0x001c, &ins));
|
| 384 |
|
|
printf("expected %x, read %lx\n", 0xffff0000, ins);
|
| 385 |
|
|
CHECK(dbg_wb_read32(SRAM_BASE+0x0020, &ins));
|
| 386 |
|
|
printf("expected %x, read %lx\n", 0xdedababa, ins);
|
| 387 |
|
|
|
| 388 |
|
|
if (ins != 0xdedababa) {
|
| 389 |
|
|
printf("SRAM test failed!!!\n");
|
| 390 |
|
|
return APP_ERR_TEST_FAIL;
|
| 391 |
|
|
}
|
| 392 |
|
|
else
|
| 393 |
|
|
printf("SRAM test passed\n");
|
| 394 |
|
|
|
| 395 |
|
|
return APP_ERR_NONE;
|
| 396 |
|
|
}
|
| 397 |
|
|
|
| 398 |
|
|
|
| 399 |
|
|
|
| 400 |
|
|
int test_or1k_cpu0(void)
|
| 401 |
|
|
{
|
| 402 |
|
|
unsigned long npc, ppc, r1, insn;
|
| 403 |
|
|
unsigned char stalled;
|
| 404 |
|
|
unsigned long result;
|
| 405 |
|
|
int i;
|
| 406 |
|
|
|
| 407 |
|
|
printf("Testing CPU0 (or1k) - writing instructions\n");
|
| 408 |
|
|
CHECK(dbg_wb_write32(SDRAM_BASE+0x00, 0xe0000005)); /* l.xor r0,r0,r0 */
|
| 409 |
|
|
CHECK(dbg_wb_write32(SDRAM_BASE+0x04, 0x9c200000)); /* l.addi r1,r0,0x0 */
|
| 410 |
|
|
CHECK(dbg_wb_write32(SDRAM_BASE+0x08, 0x18400000)); /* l.movhi r2,0x4000 */
|
| 411 |
|
|
CHECK(dbg_wb_write32(SDRAM_BASE+0x0c, 0xa8420030)); /* l.ori r2,r2,0x30 */
|
| 412 |
|
|
CHECK(dbg_wb_write32(SDRAM_BASE+0x10, 0x9c210001)); /* l.addi r1,r1,1 */
|
| 413 |
|
|
CHECK(dbg_wb_write32(SDRAM_BASE+0x14, 0x9c210001)); /* l.addi r1,r1,1 */
|
| 414 |
|
|
CHECK(dbg_wb_write32(SDRAM_BASE+0x18, 0xd4020800)); /* l.sw 0(r2),r1 */
|
| 415 |
|
|
CHECK(dbg_wb_write32(SDRAM_BASE+0x1c, 0x9c210001)); /* l.addi r1,r1,1 */
|
| 416 |
|
|
CHECK(dbg_wb_write32(SDRAM_BASE+0x20, 0x84620000)); /* l.lwz r3,0(r2) */
|
| 417 |
|
|
CHECK(dbg_wb_write32(SDRAM_BASE+0x24, 0x03fffffb)); /* l.j loop2 */
|
| 418 |
|
|
CHECK(dbg_wb_write32(SDRAM_BASE+0x28, 0xe0211800)); /* l.add r1,r1,r3 */
|
| 419 |
|
|
|
| 420 |
|
|
printf("Setting up CPU0\n");
|
| 421 |
|
|
CHECK(dbg_cpu0_write((0 << 11) + 17, 0x01)); /* Enable exceptions */
|
| 422 |
|
|
CHECK(dbg_cpu0_write((6 << 11) + 20, 0x2000)); /* Trap causes stall */
|
| 423 |
|
|
CHECK(dbg_cpu0_write((0 << 11) + 16, SDRAM_BASE)); /* Set PC */
|
| 424 |
|
|
CHECK(dbg_cpu0_write((6 << 11) + 16, 1 << 22)); /* Set step bit */
|
| 425 |
|
|
printf("Starting CPU0!\n");
|
| 426 |
|
|
for(i = 0; i < 11; i++) {
|
| 427 |
|
|
CHECK(dbg_cpu0_write_ctrl(CPU_OP_ADR, 0x00)); /* 11x Unstall */
|
| 428 |
|
|
//printf("Starting CPU, waiting for trap...\n");
|
| 429 |
|
|
do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
|
| 430 |
|
|
//printf("Got trap.\n");
|
| 431 |
|
|
}
|
| 432 |
|
|
|
| 433 |
|
|
CHECK(dbg_cpu0_read((0 << 11) + 16, &npc)); /* Read NPC */
|
| 434 |
|
|
CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc)); /* Read PPC */
|
| 435 |
|
|
CHECK(dbg_cpu0_read(0x401, &r1)); /* Read R1 */
|
| 436 |
|
|
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
|
| 437 |
|
|
printf("Expected npc = %.8x ppc = %.8x r1 = %.8x\n", 0x00000010, 0x00000028, 5);
|
| 438 |
|
|
result = npc + ppc + r1;
|
| 439 |
|
|
|
| 440 |
|
|
CHECK(dbg_cpu0_write((6 << 11) + 16, 0)); // Reset step bit
|
| 441 |
|
|
CHECK(dbg_wb_read32(SDRAM_BASE + 0x28, &insn)); // Set trap insn in delay slot
|
| 442 |
|
|
CHECK(dbg_wb_write32(SDRAM_BASE + 0x28, 0x21000001));
|
| 443 |
|
|
CHECK(dbg_cpu0_write_ctrl(CPU_OP_ADR, 0x00)); // Unstall
|
| 444 |
|
|
do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
|
| 445 |
|
|
CHECK(dbg_cpu0_read((0 << 11) + 16, &npc)); // Read NPC
|
| 446 |
|
|
CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc)); // Read PPC
|
| 447 |
|
|
CHECK(dbg_cpu0_read(0x401, &r1)); // Read R1
|
| 448 |
|
|
CHECK(dbg_wb_write32(SDRAM_BASE + 0x28, insn)); // Set back original insn
|
| 449 |
|
|
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
|
| 450 |
|
|
printf("Expected npc = %.8x ppc = %.8x r1 = %.8x\n", 0x00000010, 0x00000028, 8);
|
| 451 |
|
|
result = npc + ppc + r1 + result;
|
| 452 |
|
|
|
| 453 |
|
|
CHECK(dbg_wb_read32(SDRAM_BASE + 0x24, &insn)); // Set trap insn in place of branch insn
|
| 454 |
|
|
CHECK(dbg_wb_write32(SDRAM_BASE + 0x24, 0x21000001));
|
| 455 |
|
|
CHECK(dbg_cpu0_write((0 << 11) + 16, SDRAM_BASE + 0x10)); // Set PC
|
| 456 |
|
|
CHECK(dbg_cpu0_write_ctrl(CPU_OP_ADR, 0x00)); // Unstall
|
| 457 |
|
|
do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
|
| 458 |
|
|
CHECK(dbg_cpu0_read((0 << 11) + 16, &npc)); // Read NPC
|
| 459 |
|
|
CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc)); // Read PPC
|
| 460 |
|
|
CHECK(dbg_cpu0_read(0x401, &r1)); // Read R1
|
| 461 |
|
|
CHECK(dbg_wb_write32(SDRAM_BASE + 0x24, insn)); // Set back original insn
|
| 462 |
|
|
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
|
| 463 |
|
|
printf("Expected npc = %.8x ppc = %.8x r1 = %.8x\n", 0x00000028, 0x00000024, 11);
|
| 464 |
|
|
result = npc + ppc + r1 + result;
|
| 465 |
|
|
|
| 466 |
|
|
CHECK(dbg_wb_read32(SDRAM_BASE + 0x20, &insn)); /* Set trap insn before branch insn */
|
| 467 |
|
|
CHECK(dbg_wb_write32(SDRAM_BASE + 0x20, 0x21000001));
|
| 468 |
|
|
CHECK(dbg_cpu0_write((0 << 11) + 16, SDRAM_BASE + 0x24)); /* Set PC */
|
| 469 |
|
|
CHECK(dbg_cpu0_write_ctrl(CPU_OP_ADR, 0x00)); /* Unstall */
|
| 470 |
|
|
do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
|
| 471 |
|
|
CHECK(dbg_cpu0_read((0 << 11) + 16, &npc)); /* Read NPC */
|
| 472 |
|
|
CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc)); /* Read PPC */
|
| 473 |
|
|
CHECK(dbg_cpu0_read(0x401, &r1)); /* Read R1 */
|
| 474 |
|
|
CHECK(dbg_wb_write32(SDRAM_BASE + 0x20, insn)); /* Set back original insn */
|
| 475 |
|
|
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
|
| 476 |
|
|
printf("Expected npc = %.8x ppc = %.8x r1 = %.8x\n", 0x00000024, 0x00000020, 24);
|
| 477 |
|
|
result = npc + ppc + r1 + result;
|
| 478 |
|
|
|
| 479 |
|
|
CHECK(dbg_wb_read32(SDRAM_BASE + 0x1c, &insn)); /* Set trap insn behind lsu insn */
|
| 480 |
|
|
CHECK(dbg_wb_write32(SDRAM_BASE + 0x1c, 0x21000001));
|
| 481 |
|
|
CHECK(dbg_cpu0_write((0 << 11) + 16, SDRAM_BASE + 0x20)); /* Set PC */
|
| 482 |
|
|
CHECK(dbg_cpu0_write_ctrl(CPU_OP_ADR, 0x00)); /* Unstall */
|
| 483 |
|
|
do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
|
| 484 |
|
|
CHECK(dbg_cpu0_read((0 << 11) + 16, &npc)); /* Read NPC */
|
| 485 |
|
|
CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc)); /* Read PPC */
|
| 486 |
|
|
CHECK(dbg_cpu0_read(0x401, &r1)); /* Read R1 */
|
| 487 |
|
|
CHECK(dbg_wb_write32(SDRAM_BASE + 0x1c, insn)); /* Set back original insn */
|
| 488 |
|
|
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
|
| 489 |
|
|
printf("Expected npc = %.8x ppc = %.8x r1 = %.8x\n", 0x00000020, 0x0000001c, 49);
|
| 490 |
|
|
result = npc + ppc + r1 + result;
|
| 491 |
|
|
|
| 492 |
|
|
CHECK(dbg_wb_read32(SDRAM_BASE + 0x20, &insn)); /* Set trap insn very near previous one */
|
| 493 |
|
|
CHECK(dbg_wb_write32(SDRAM_BASE + 0x20, 0x21000001));
|
| 494 |
|
|
CHECK(dbg_cpu0_write((0 << 11) + 16, SDRAM_BASE + 0x1c)); /* Set PC */
|
| 495 |
|
|
CHECK(dbg_cpu0_write_ctrl(CPU_OP_ADR, 0x00)); /* Unstall */
|
| 496 |
|
|
do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
|
| 497 |
|
|
CHECK(dbg_cpu0_read((0 << 11) + 16, &npc)); /* Read NPC */
|
| 498 |
|
|
CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc)); /* Read PPC */
|
| 499 |
|
|
CHECK(dbg_cpu0_read(0x401, &r1)); /* Read R1 */
|
| 500 |
|
|
CHECK(dbg_wb_write32(SDRAM_BASE + 0x20, insn)); /* Set back original insn */
|
| 501 |
|
|
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
|
| 502 |
|
|
printf("Expected npc = %.8x ppc = %.8x r1 = %.8x\n", 0x00000024, 0x00000020, 50);
|
| 503 |
|
|
result = npc + ppc + r1 + result;
|
| 504 |
|
|
|
| 505 |
|
|
CHECK(dbg_wb_read32(SDRAM_BASE + 0x10, &insn)); /* Set trap insn to the start */
|
| 506 |
|
|
CHECK(dbg_wb_write32(SDRAM_BASE + 0x10, 0x21000001));
|
| 507 |
|
|
CHECK(dbg_cpu0_write((0 << 11) + 16, SDRAM_BASE + 0x20) /* Set PC */);
|
| 508 |
|
|
CHECK(dbg_cpu0_write_ctrl(CPU_OP_ADR, 0x00)); /* Unstall */
|
| 509 |
|
|
do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
|
| 510 |
|
|
CHECK(dbg_cpu0_read((0 << 11) + 16, &npc)); /* Read NPC */
|
| 511 |
|
|
CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc)); /* Read PPC */
|
| 512 |
|
|
CHECK(dbg_cpu0_read(0x401, &r1)); /* Read R1 */
|
| 513 |
|
|
CHECK(dbg_wb_write32(SDRAM_BASE + 0x10, insn)); /* Set back original insn */
|
| 514 |
|
|
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
|
| 515 |
|
|
printf("Expected npc = %.8x ppc = %.8x r1 = %.8x\n", 0x00000014, 0x00000010, 99);
|
| 516 |
|
|
result = npc + ppc + r1 + result;
|
| 517 |
|
|
|
| 518 |
|
|
CHECK(dbg_cpu0_write((6 << 11) + 16, 1 << 22)); /* Set step bit */
|
| 519 |
|
|
for(i = 0; i < 5; i++) {
|
| 520 |
|
|
CHECK(dbg_cpu0_write_ctrl(CPU_OP_ADR, 0x00)); /* Unstall */
|
| 521 |
|
|
//printf("Waiting for trap...");
|
| 522 |
|
|
do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
|
| 523 |
|
|
//printf("got trap.\n");
|
| 524 |
|
|
}
|
| 525 |
|
|
CHECK(dbg_cpu0_read((0 << 11) + 16, &npc)); /* Read NPC */
|
| 526 |
|
|
CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc)); /* Read PPC */
|
| 527 |
|
|
CHECK(dbg_cpu0_read(0x401, &r1)); /* Read R1 */
|
| 528 |
|
|
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
|
| 529 |
|
|
printf("Expected npc = %.8x ppc = %.8x r1 = %.8x\n", 0x00000028, 0x00000024, 101);
|
| 530 |
|
|
result = npc + ppc + r1 + result;
|
| 531 |
|
|
|
| 532 |
|
|
CHECK(dbg_cpu0_write((0 << 11) + 16, SDRAM_BASE + 0x24)); /* Set PC */
|
| 533 |
|
|
for(i = 0; i < 2; i++) {
|
| 534 |
|
|
CHECK(dbg_cpu0_write_ctrl(CPU_OP_ADR, 0x00)); /* Unstall */
|
| 535 |
|
|
//printf("Waiting for trap...\n");
|
| 536 |
|
|
do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
|
| 537 |
|
|
//printf("Got trap.\n");
|
| 538 |
|
|
}
|
| 539 |
|
|
CHECK(dbg_cpu0_read((0 << 11) + 16, &npc)); /* Read NPC */
|
| 540 |
|
|
CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc)); /* Read PPC */
|
| 541 |
|
|
CHECK(dbg_cpu0_read(0x401, &r1)); /* Read R1 */
|
| 542 |
|
|
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
|
| 543 |
|
|
printf("Expected npc = %.8x ppc = %.8x r1 = %.8x\n", 0x00000010, 0x00000028, 201);
|
| 544 |
|
|
result = npc + ppc + r1 + result;
|
| 545 |
|
|
printf("result = %.8lx\n", result ^ 0xdeaddae1);
|
| 546 |
|
|
|
| 547 |
|
|
if((result ^ 0xdeaddae1) != 0xdeaddead)
|
| 548 |
|
|
return APP_ERR_TEST_FAIL;
|
| 549 |
|
|
|
| 550 |
|
|
return APP_ERR_NONE;
|
| 551 |
|
|
}
|
| 552 |
|
|
|
| 553 |
|
|
|
| 554 |
|
|
// This function does not currently return a useful value
|
| 555 |
|
|
/*
|
| 556 |
|
|
unsigned char test_8051_cpu1(void)
|
| 557 |
|
|
{
|
| 558 |
|
|
int retval = 1;
|
| 559 |
|
|
unsigned long result = 0;
|
| 560 |
|
|
unsigned long npc[3], tmp;
|
| 561 |
|
|
|
| 562 |
|
|
printf("Testing CPU1 (8051)\n");
|
| 563 |
|
|
|
| 564 |
|
|
// WRITE ACC
|
| 565 |
|
|
CHECK(dbg_cpu1_write(0x20e0, 0xa6));
|
| 566 |
|
|
|
| 567 |
|
|
// READ ACC
|
| 568 |
|
|
CHECK(dbg_cpu1_read(0x20e0, &tmp)); // select SFR space
|
| 569 |
|
|
printf("Read 8051 ACC = %0x (expected a6)\n", tmp);
|
| 570 |
|
|
result = result + tmp;
|
| 571 |
|
|
|
| 572 |
|
|
// set exception to single step to jump over a loop
|
| 573 |
|
|
CHECK(dbg_cpu1_write(0x3010, 0xa0)); // set single step and global enable in EER
|
| 574 |
|
|
CHECK(dbg_cpu1_write(0x3011, 0x40)); // set evec = 24'h000040
|
| 575 |
|
|
CHECK(dbg_cpu1_write(0x3012, 0x00)); // (already reset value)
|
| 576 |
|
|
CHECK(dbg_cpu1_write(0x3013, 0x00)); // (already reset value)
|
| 577 |
|
|
|
| 578 |
|
|
// set HW breakpoint at PC == 0x41
|
| 579 |
|
|
CHECK(dbg_cpu1_write(0x3020, 0x41)); // DVR0 = 24'h000041
|
| 580 |
|
|
CHECK(dbg_cpu1_write(0x3023, 0x39)); // DCR0 = valid, == PC
|
| 581 |
|
|
CHECK(dbg_cpu1_write(0x3001, 0x04)); // DSR = watchpoint
|
| 582 |
|
|
|
| 583 |
|
|
// flush 8051 instruction cache
|
| 584 |
|
|
CHECK(dbg_cpu1_write(0x209f, 0x00));
|
| 585 |
|
|
|
| 586 |
|
|
// Put some instructions in ram (8-bit mode on wishbone)
|
| 587 |
|
|
CHECK(dbg_wb_write8 (0x40, 0x04)); // inc a
|
| 588 |
|
|
CHECK(dbg_wb_write8 (0x41, 0x03)); // rr a;
|
| 589 |
|
|
CHECK(dbg_wb_write8 (0x42, 0x14)); // dec a;
|
| 590 |
|
|
CHECK(dbg_wb_write8 (0x43, 0xf5)); // mov 0e5h, a;
|
| 591 |
|
|
CHECK(dbg_wb_write8 (0x44, 0xe5));
|
| 592 |
|
|
|
| 593 |
|
|
// unstall just 8051
|
| 594 |
|
|
CHECK(dbg_cpu1_write_reg(0, 0));
|
| 595 |
|
|
|
| 596 |
|
|
// read PC
|
| 597 |
|
|
CHECK(dbg_cpu1_read(0, &npc[0]));
|
| 598 |
|
|
CHECK(dbg_cpu1_read(1, &npc[1]));
|
| 599 |
|
|
CHECK(dbg_cpu1_read(2, &npc[2]));
|
| 600 |
|
|
printf("Read 8051 npc = %02x%02x%02x (expected 41)\n", npc[2], npc[1], npc[0]);
|
| 601 |
|
|
result = result + (npc[2] << 16) + (npc[1] << 8) + npc[0];
|
| 602 |
|
|
|
| 603 |
|
|
// READ ACC
|
| 604 |
|
|
CHECK(dbg_cpu1_read(0x20e0, &tmp)); // select SFR space
|
| 605 |
|
|
printf("Read 8051 ACC = %0x (expected a7)\n", tmp);
|
| 606 |
|
|
result = result + tmp;
|
| 607 |
|
|
|
| 608 |
|
|
// set sigle step to stop execution
|
| 609 |
|
|
CHECK(dbg_cpu1_write(0x3001, 0x20)); // set single step and global enable in DSR
|
| 610 |
|
|
|
| 611 |
|
|
// clear DRR
|
| 612 |
|
|
CHECK(dbg_cpu1_write(0x3000, 0x00)); // set single step and global enable in DRR
|
| 613 |
|
|
|
| 614 |
|
|
// unstall just 8051
|
| 615 |
|
|
CHECK(dbg_cpu1_write_reg(0, 0));
|
| 616 |
|
|
|
| 617 |
|
|
// read PC
|
| 618 |
|
|
CHECK(dbg_cpu1_read(0, &npc[0]));
|
| 619 |
|
|
CHECK(dbg_cpu1_read(1, &npc[1]));
|
| 620 |
|
|
CHECK(dbg_cpu1_read(2, &npc[2]));
|
| 621 |
|
|
printf("Read 8051 npc = %02x%02x%02x (expected 42)\n", npc[2], npc[1], npc[0]);
|
| 622 |
|
|
result = result + (npc[2] << 16) + (npc[1] << 8) + npc[0];
|
| 623 |
|
|
|
| 624 |
|
|
// READ ACC
|
| 625 |
|
|
CHECK(dbg_cpu1_read(0x20e0, &tmp)); // select SFR space
|
| 626 |
|
|
printf("Read 8051 ACC = %0x (expected d3)\n", tmp);
|
| 627 |
|
|
result = result + tmp;
|
| 628 |
|
|
|
| 629 |
|
|
printf("report (%x)\n", result ^ 0x6c1 ^ 0xdeaddead);
|
| 630 |
|
|
|
| 631 |
|
|
return APP_ERR_NONE;
|
| 632 |
|
|
}
|
| 633 |
|
|
*/
|
