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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [sw/] [adv_jtag_bridge/] [sim_rtl/] [dbg_comm.v] - Blame information for rev 21

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Line No. Rev Author Line
1 12 xianfeng
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  dbg_comm.v                                                  ////
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////                                                              ////
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////                                                              ////
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////  This file is part of the SoC/OpenRISC Development Interface ////
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////  http://www.opencores.org/cores/DebugInterface/              ////
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////                                                              ////
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////                                                              ////
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////  Author(s):                                                  ////
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////       Igor Mohor  (igorm@opencores.org)                      ////
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////       Nathan Yawn (nathan.yawn@opencores.org)                ////
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////                                                              ////
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////                                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000-2008 Authors                              ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: dbg_comm.v,v $
46 21 xianfeng
// Revision 1.3  2009-05-17 20:55:57  Nathan
47 12 xianfeng
// Changed email address to opencores.org
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//
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// Revision 1.2  2008/07/22 18:23:25  Nathan
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// Added clock and reset outputs to make simulation system simpler.  Fixed P_TRST signal name.  Added fflush calls to make file IO work as quickly as possible.  Write the data out bit on falling clock edge. Cleanup.
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//
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// Revision 1.1  2002/03/28 19:59:54  lampret
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// Added bench directory
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//
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// Revision 1.1.1.1  2001/11/04 18:51:07  lampret
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// First import.
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//
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// Revision 1.3  2001/09/24 14:06:13  mohor
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// Changes connected to the OpenRISC access (SPR read, SPR write).
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//
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// Revision 1.2  2001/09/20 10:10:30  mohor
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// Working version. Few bugs fixed, comments added.
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//
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// Revision 1.1.1.1  2001/09/13 13:49:19  mohor
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// Initial official release.
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//
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//
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//
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//
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//
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`define GDB_IN  "e:/tmp/gdb_in.dat"
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`define GDB_OUT "e:/tmp/gdb_out.dat"
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module dbg_comm(
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   SYS_CLK,
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   SYS_RSTN,
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   P_TMS,
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   P_TCK,
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   P_TRST,
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   P_TDI,
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   P_TDO
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   );
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parameter Tp = 20;
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output  SYS_CLK;
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output  SYS_RSTN;
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output          P_TMS;
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output          P_TCK;
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output          P_TRST;
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output          P_TDI;
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input            P_TDO;
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// Signal for the whole system
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reg SYS_CLK;
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reg SYS_RSTN;
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// For handling data from the input file
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integer handle1, handle2;
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reg [4:0] memory[0:0];
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wire P_TCK;
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wire P_TRST;
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wire P_TDI;
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wire P_TMS;
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wire P_TDO;
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// Temp. signal
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reg [3:0] in_word_r;
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// Provide the wishbone / CPU / system clock
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initial
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begin
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  SYS_CLK = 1'b0;
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  forever #5 SYS_CLK = ~SYS_CLK;
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end
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// Provide the system reset
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initial
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begin
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   SYS_RSTN = 1'b1;
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   #200 SYS_RSTN = 1'b0;
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   #5000 SYS_RSTN = 1'b1;
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end
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// Set the initial state of the JTAG pins
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initial
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begin
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  in_word_r = 4'h0;  // This sets the TRSTN output active...
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end
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// Handle input from a file for the JTAG pins
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initial
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begin
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  #5500;  // Wait until reset is complete
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  while(1)
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  begin
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    #Tp;
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    $readmemh(`GDB_OUT, memory);
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    if(!(memory[0] & 5'b10000))
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    begin
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           in_word_r = memory[0][3:0];
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      handle1 = $fopen(`GDB_OUT);
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      $fwrite(handle1, "%h", 5'b10000 | memory[0]);  // To ack that we read dgb_out.dat
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      $fflush(handle1);
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      $fclose(handle1);
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    end
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  end
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end
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// Send the current state of the JTAG output to a file 
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always @ (P_TDO or negedge P_TCK)
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begin
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  handle2 = $fopen(`GDB_IN);
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  $fdisplay(handle2, "%b", P_TDO);
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  $fflush(handle2);
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  $fclose(handle2);
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end
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// Note these must match the bit definitions in the JTAG bridge program (adv_jtag_bridge)
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assign P_TCK = in_word_r[0];
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assign P_TRST = in_word_r[1];
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assign P_TDI = in_word_r[2];
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assign P_TMS = in_word_r[3];
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endmodule // TAP
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