OpenCores
URL https://opencores.org/ocsvn/or1k_soc_on_altera_embedded_dev_kit/or1k_soc_on_altera_embedded_dev_kit/trunk

Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [sw/] [orpmon/] [reset.S] - Blame information for rev 20

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Line No. Rev Author Line
1 20 xianfeng 
#include "spr_defs.h"
2 
#include "board.h"
3 
#include "mc.h"
4 
 
5 
        .extern _reset_support
6 
        .extern _eth_int
7 
        .extern _src_beg
8 
        .extern _dst_beg
9 
        .extern _dst_end
10 
        .extern _c_reset
11 
        .extern _int_main
12 
        .extern _tick_interrupt
13 
        .extern _crc32
14 
 
15 
        /* Used by global.src_addr for default value */
16 
        .extern _src_addr
17 
 
18 
        .global _align
19 
        .global _calc_mycrc32
20 
        .global _mycrc32
21 
        .global _mysize
22 
 
23 
        .section .stack, "aw", @nobits
24 
.space  STACK_SIZE
25 
_stack:
26 
        .section .crc
27 
_mycrc32:
28 
        .word   0xcccccccc
29 
_mysize:
30 
        .word 0xdddddddd
31 
 
32 
.if SELF_CHECK
33 
_calc_mycrc32:
34 
        l.addi  r3,r0,0
35 
        l.movhi r4,hi(_calc_mycrc32)
36 
        l.ori   r4,r4,lo(_calc_mycrc32)
37 
        l.movhi r5,hi(_mysize)
38 
        l.ori   r5,r5,lo(_mysize)
39 
        l.lwz   r5,0(r5)
40 
        l.addi  r1,r1,-4
41 
        l.sw    0(r1),r9
42 
 
43 
        /* unsigned long crc32 (unsigned long crc, const unsigned char *buf, unsigned long len); */
44 
        l.jal           _crc32
45 
        l.nop
46 
 
47 
        l.movhi r3,hi(_mycrc32)
48 
        l.ori   r3,r3,lo(_mycrc32)
49 
        l.lwz   r3,0(r3)
50 
 
51 
        l.xor     r11,r3,r11
52 
        l.lwz   r9,0(r1)
53 
        l.jr    r9
54 
        l.addi  r1,r1,4
55 
.endif
56 
 
57 
        .org 0x100
58 
.if IN_FLASH
59 
        .section .reset, "ax"
60 
.else
61 
        .section .vectors, "ax"
62 
.endif
63 
 
64 
_reset:
65 
.if IN_FLASH
66 
        l.movhi r3,hi(MC_BASE_ADDR)
67 
        l.ori   r3,r3,MC_BA_MASK
68 
        l.addi  r5,r0,0x00
69 
        l.sw    0(r3),r5
70 
.endif
71 
        l.addi  r3,r0,SPR_SR_SM
72 
        l.mtspr r0,r3,SPR_SR
73 
        l.movhi r3,hi(_start)
74 
        l.ori   r3,r3,lo(_start)
75 
        l.jr    r3
76 
        l.nop
77 
 
78 
.if IN_FLASH
79 
        .section .vectors, "ax"
80 
        .org 0x500
81 
.else
82 
        .org (0x500 - 0x100 + _reset)
83 
.endif
84 
 
85 
        l.addi  r1,r1,-128
86 
        l.sw    0x4(r1),r2
87 
        l.movhi r2,hi(_tick)
88 
        l.ori   r2,r2,lo(_tick)
89 
        l.jr    r2
90 
        l.nop
91 
 
92 
.if IN_FLASH
93 
        .section .vectors, "ax"
94 
        .org 0x600
95 
.else
96 
        .org (0x600 - 0x100 + _reset)
97 
.endif
98 
 
99 
        l.addi  r1,r1,-128
100 
        l.sw    0x08(r1),r2
101 
        l.movhi r2,hi(_align)
102 
        l.ori   r2,r2,lo(_align)
103 
        l.jr    r2
104 
        l.nop
105 
 
106 
.if IN_FLASH
107 
        .org 0x800
108 
.else
109 
        .org (0x800 - 0x100 + _reset)
110 
.endif
111 
 
112 
        l.addi  r1,r1,-128
113 
        l.sw    0x4(r1),r2
114 
        l.movhi r2,hi(_int_wrapper)
115 
        l.ori   r2,r2,lo(_int_wrapper)
116 
        l.jr    r2
117 
        l.nop
118 
 
119 
        .section .text
120 
_start:
121 
.if IN_FLASH
122 
        l.jal   _init_mc
123 
        l.nop
124 
 
125 
        /* Wait for SDRAM */
126 
        l.addi  r3,r0,0x1000
127 
1:      l.sfeqi r3,0
128 
        l.bnf   1b
129 
        l.addi  r3,r3,-1
130 
.endif
131 
        /* Copy form flash to sram */
132 
.if IN_FLASH
133 
        l.movhi r3,hi(_src_beg)
134 
        l.ori   r3,r3,lo(_src_beg)
135 
        l.movhi r4,hi(_vec_start)
136 
        l.ori   r4,r4,lo(_vec_start)
137 
        l.movhi r5,hi(_vec_end)
138 
        l.ori   r5,r5,lo(_vec_end)
139 
        l.sub   r5,r5,r4
140 
        l.sfeqi r5,0
141 
        l.bf    2f
142 
        l.nop
143 
1:      l.lwz   r6,0(r3)
144 
        l.sw    0(r4),r6
145 
        l.addi  r3,r3,4
146 
        l.addi  r4,r4,4
147 
        l.addi  r5,r5,-4
148 
        l.sfgtsi r5,0
149 
        l.bf    1b
150 
        l.nop
151 
2:
152 
        l.movhi r4,hi(_dst_beg)
153 
        l.ori   r4,r4,lo(_dst_beg)
154 
        l.movhi r5,hi(_dst_end)
155 
        l.ori   r5,r5,lo(_dst_end)
156 
1:      l.sfgeu r4,r5
157 
        l.bf    1f
158 
        l.nop
159 
        l.lwz   r8,0(r3)
160 
        l.sw    0(r4),r8
161 
        l.addi  r3,r3,4
162 
        l.bnf   1b
163 
        l.addi  r4,r4,4
164 
1:
165 
        l.addi  r3,r0,0
166 
        l.addi  r4,r0,0
167 
3:
168 
.endif
169 
 
170 
.if IC_ENABLE
171 
        l.jal   _ic_enable
172 
        l.nop
173 
.endif
174 
 
175 
.if DC_ENABLE
176 
        l.jal   _dc_enable
177 
        l.nop
178 
.endif
179 
 
180 
        l.movhi r1,hi(_stack-4)
181 
        l.ori   r1,r1,lo(_stack-4)
182 
        l.addi  r2,r0,-3
183 
        l.and   r1,r1,r2
184 
 
185 
        l.movhi r2,hi(_main)
186 
        l.ori   r2,r2,lo(_main)
187 
        l.jr    r2
188 
        l.addi  r2,r0,0
189 
 
190 
_ic_enable:
191 
 
192 
        /* Flush IC */
193 
        l.addi  r10,r0,0
194 
        l.addi  r11,r0,IC_SIZE
195 
1:
196 
        l.mtspr r0,r10,SPR_ICBIR
197 
        l.sfne  r10,r11
198 
        l.bf    1b
199 
        l.addi  r10,r10,16
200 
 
201 
        /* Enable IC */
202 
        l.mfspr r10,r0,SPR_SR
203 
        l.ori   r10,r10,(SPR_SR_ICE|SPR_SR_SM)
204 
        l.mtspr r0,r10,SPR_SR
205 
        l.nop
206 
        l.nop
207 
        l.nop
208 
        l.nop
209 
        l.nop
210 
 
211 
        l.jr    r9
212 
        l.nop
213 
 
214 
_dc_enable:
215 
 
216 
        /* Flush DC */
217 
        l.addi  r10,r0,0
218 
        l.addi  r11,r0,DC_SIZE
219 
1:
220 
        l.mtspr r0,r10,SPR_DCBIR
221 
        l.sfne  r10,r11
222 
        l.bf    1b
223 
        l.addi  r10,r10,16
224 
 
225 
        /* Enable DC */
226 
        l.mfspr r10,r0,SPR_SR
227 
        l.ori   r10,r10,(SPR_SR_DCE|SPR_SR_SM)
228 
        l.mtspr r0,r10,SPR_SR
229 
 
230 
        l.jr    r9
231 
        l.nop
232 
 
233 
.if IN_FLASH
234 
#if CONFIG_OR32_MC_VERSION==1
235 
_init_mc:
236 
 
237 
        l.movhi r3,hi(MC_BASE_ADDR)
238 
        l.ori   r3,r3,lo(MC_BASE_ADDR)
239 
 
240 
        l.addi  r4,r3,MC_CSC(0)
241 
        l.movhi r5,hi(FLASH_BASE_ADDR)
242 
        l.srai  r5,r5,6
243 
        l.ori   r5,r5,0x0025
244 
        l.sw    0(r4),r5
245 
 
246 
        l.addi  r4,r3,MC_TMS(0)
247 
        l.movhi r5,hi(FLASH_TMS_VAL)
248 
        l.ori   r5,r5,lo(FLASH_TMS_VAL)
249 
        l.sw    0(r4),r5
250 
 
251 
        l.addi  r4,r3,MC_BA_MASK
252 
        l.addi  r5,r0,MC_MASK_VAL
253 
        l.sw    0(r4),r5
254 
 
255 
        l.addi  r4,r3,MC_CSR
256 
        l.movhi r5,hi(MC_CSR_VAL)
257 
        l.ori   r5,r5,lo(MC_CSR_VAL)
258 
        l.sw    0(r4),r5
259 
 
260 
        l.addi  r4,r3,MC_TMS(1)
261 
        l.movhi r5,hi(SDRAM_TMS_VAL)
262 
        l.ori   r5,r5,lo(SDRAM_TMS_VAL)
263 
        l.sw    0(r4),r5
264 
 
265 
        l.addi  r4,r3,MC_CSC(1)
266 
        l.movhi r5,hi(SDRAM_BASE_ADDR)
267 
        l.srai  r5,r5,6
268 
        l.ori   r5,r5,0x0411
269 
        l.sw    0(r4),r5
270 
 
271 
#ifdef ETH_DATA_BASE
272 
        l.addi  r4,r3,MC_CSC(2)
273 
        l.movhi r5,hi(ETH_DATA_BASE)
274 
        l.srai  r5,r5,6
275 
        l.ori   r5,r5,0x0005
276 
        l.sw    0(r4),r5
277 
 
278 
        l.addi  r4,r3,MC_TMS(2)
279 
        l.movhi r5,0xffff
280 
        l.ori   r5,r5,0xffff
281 
        l.sw    0(r4),r5
282 
#endif
283 
#ifdef SANCHO_BASE_ADD
284 
        l.addi  r4,r3,MC_CSC(2)
285 
        l.movhi r5,hi(SANCHO_BASE_ADD)
286 
        l.srai  r5,r5,6
287 
        l.ori   r5,r5,0x0001
288 
        l.sw    0(r4),r5
289 
 
290 
        l.addi  r4,r3,MC_TMS(2)
291 
        l.movhi r5,0x101
292 
        l.ori   r5,r5,0x101
293 
        l.sw    0(r4),r5
294 
#endif
295 
 
296 
        l.jr    r9
297 
        l.nop
298 
#elif CONFIG_OR32_MC_VERSION==2
299 
_init_mc:
300 
 
301 
        l.movhi r3,hi(MC_BASE_ADDR)
302 
        l.ori   r3,r3,lo(MC_BASE_ADDR)
303 
 
304 
        l.addi  r4,r3,MC_BAR_0
305 
        l.movhi r5,hi(FLASH_BAR_VAL)
306 
        l.sw    0(r4),r5
307 
 
308 
        l.addi  r4,r3,MC_AMR_0
309 
        l.movhi r5,hi(FLASH_AMR_VAL)
310 
        l.sw    0(r4),r5
311 
 
312 
        l.addi  r4,r3,MC_WTR_0
313 
        l.movhi r5,hi(FLASH_WTR_VAL)
314 
        l.ori   r5,r5,lo(FLASH_WTR_VAL)
315 
        l.sw    0(r4),r5
316 
 
317 
        l.addi  r4,r3,MC_RTR_0
318 
        l.movhi r5,hi(FLASH_RTR_VAL)
319 
        l.ori   r5,r5,lo(FLASH_RTR_VAL)
320 
        l.sw    0(r4),r5
321 
 
322 
        l.addi  r4,r3,MC_OSR
323 
        l.movhi r5,hi(0x40000000)
324 
        l.ori   r5,r5,lo(0x40000000)
325 
        l.sw    0(r4),r5
326 
 
327 
        l.addi  r4,r3,MC_BAR_4
328 
        l.movhi r5,hi(SDRAM_BAR_VAL)
329 
        l.sw    0(r4),r5
330 
 
331 
        l.addi  r4,r3,MC_AMR_4
332 
        l.movhi r5,hi(SDRAM_AMR_VAL)
333 
        l.sw    0(r4),r5
334 
 
335 
        l.addi  r4,r3,MC_CCR_4
336 
        l.movhi r5,hi(0x00ef0004)
337 
        l.ori   r5,r5,lo(0x00ef0004)
338 
        l.sw    0(r4),r5
339 
 
340 
        l.addi  r4,r3,MC_RATR
341 
        l.movhi r5,hi(SDRAM_RATR_VAL)
342 
        l.ori   r5,r5,lo(SDRAM_RATR_VAL)
343 
        l.sw    0(r4),r5
344 
 
345 
        l.addi  r4,r3,MC_RCDR
346 
        l.movhi r5,hi(SDRAM_RCDR_VAL)
347 
        l.ori   r5,r5,lo(SDRAM_RCDR_VAL)
348 
        l.sw    0(r4),r5
349 
 
350 
        l.addi  r4,r3,MC_RCTR
351 
        l.movhi r5,hi(SDRAM_RCTR_VAL)
352 
        l.ori   r5,r5,lo(SDRAM_RCTR_VAL)
353 
        l.sw    0(r4),r5
354 
 
355 
        l.addi  r4,r3,MC_REFCTR
356 
        l.movhi r5,hi(SDRAM_REFCTR_VAL)
357 
        l.ori   r5,r5,lo(SDRAM_REFCTR_VAL)
358 
        l.sw    0(r4),r5
359 
 
360 
        l.addi  r4,r3,MC_PTR
361 
        l.movhi r5,hi(SDRAM_PTR_VAL)
362 
        l.ori   r5,r5,lo(SDRAM_PTR_VAL)
363 
        l.sw    0(r4),r5
364 
 
365 
        l.addi  r4,r3,MC_RRDR
366 
        l.movhi r5,hi(SDRAM_RRDR_VAL)
367 
        l.ori   r5,r5,lo(SDRAM_RRDR_VAL)
368 
        l.sw    0(r4),r5
369 
 
370 
        l.addi  r4,r3,MC_RIR
371 
        l.movhi r5,hi(SDRAM_RIR_VAL)
372 
        l.ori   r5,r5,lo(SDRAM_RIR_VAL)
373 
        l.sw    0(r4),r5
374 
 
375 
        l.addi  r4,r3,MC_OSR
376 
        l.movhi r5,hi(0x5e000000)
377 
        l.ori   r5,r5,lo(0x5e000000)
378 
        l.sw    0(r4),r5
379 
 
380 
        l.addi  r4,r3,MC_ORR
381 
        l.sw    0(r4),r5
382 
 
383 
        l.addi  r4,r3,MC_OSR
384 
        l.movhi r5,hi(0x6e000000)
385 
        l.ori   r5,r5,lo(0x6e000000)
386 
        l.sw    0(r4),r5
387 
 
388 
        l.addi  r4,r3,MC_ORR
389 
        l.sw    0(r4),r5
390 
        l.sw    0(r4),r5
391 
        l.sw    0(r4),r5
392 
        l.sw    0(r4),r5
393 
        l.sw    0(r4),r5
394 
        l.sw    0(r4),r5
395 
        l.sw    0(r4),r5
396 
        l.sw    0(r4),r5
397 
 
398 
        l.addi  r4,r3,MC_OSR
399 
        l.movhi r5,hi(0x7e000023)
400 
        l.ori   r5,r5,lo(0x7e000023)
401 
        l.sw    0(r4),r5
402 
 
403 
        l.addi  r4,r3,MC_ORR
404 
        l.sw    0(r4),r5
405 
 
406 
#ifdef FLASH_ORG_16_1
407 
        l.addi  r4,r3,MC_CCR_4
408 
        l.movhi r5,hi(0xc0ae0004)
409 
        l.ori   r5,r5,lo(0xc0ae0004)
410 
        l.sw    0(r4),r5
411 
#else
412 
#  error "no configuration for this data bus width"
413 
#endif
414 
        l.jr    r9
415 
        l.nop
416 
#else
417 
#  error "no memory controler chosen"
418 
#endif
419 
 
420 
.endif
421 
 
422 
_tick:
423 
        l.sw    0x8(r1),r4
424 
        l.sw    0xc(r1),r5
425 
        l.sw    0x10(r1),r6
426 
        l.sw    0x14(r1),r7
427 
        l.sw    0x18(r1),r8
428 
        l.sw    0x1c(r1),r9
429 
        l.sw    0x20(r1),r10
430 
        l.sw    0x24(r1),r11
431 
        l.sw    0x28(r1),r12
432 
        l.sw    0x2c(r1),r13
433 
        l.sw    0x30(r1),r14
434 
        l.sw    0x34(r1),r15
435 
        l.sw    0x38(r1),r16
436 
        l.sw    0x3c(r1),r17
437 
        l.sw    0x40(r1),r18
438 
        l.sw    0x44(r1),r19
439 
        l.sw    0x48(r1),r20
440 
        l.sw    0x4c(r1),r21
441 
        l.sw    0x50(r1),r22
442 
        l.sw    0x54(r1),r23
443 
        l.sw    0x58(r1),r24
444 
        l.sw    0x5c(r1),r25
445 
        l.sw    0x60(r1),r26
446 
        l.sw    0x64(r1),r27
447 
        l.sw    0x68(r1),r28
448 
        l.sw    0x6c(r1),r29
449 
        l.sw    0x70(r1),r30
450 
        l.sw    0x74(r1),r31
451 
        l.sw    0x78(r1),r3
452 
 
453 
        l.movhi r3,hi(_tick_interrupt)
454 
        l.ori   r3,r3,lo(_tick_interrupt)
455 
        l.jalr  r3
456 
        l.nop
457 
 
458 
        l.lwz   r2,0x4(r1)
459 
        l.lwz   r4,0x8(r1)
460 
        l.lwz   r5,0xc(r1)
461 
        l.lwz   r6,0x10(r1)
462 
        l.lwz   r7,0x14(r1)
463 
        l.lwz   r8,0x18(r1)
464 
        l.lwz   r9,0x1c(r1)
465 
        l.lwz   r10,0x20(r1)
466 
        l.lwz   r11,0x24(r1)
467 
        l.lwz   r12,0x28(r1)
468 
        l.lwz   r13,0x2c(r1)
469 
        l.lwz   r14,0x30(r1)
470 
        l.lwz   r15,0x34(r1)
471 
        l.lwz   r16,0x38(r1)
472 
        l.lwz   r17,0x3c(r1)
473 
        l.lwz   r18,0x40(r1)
474 
        l.lwz   r19,0x44(r1)
475 
        l.lwz   r20,0x48(r1)
476 
        l.lwz   r21,0x4c(r1)
477 
        l.lwz   r22,0x50(r1)
478 
        l.lwz   r23,0x54(r1)
479 
        l.lwz   r24,0x58(r1)
480 
        l.lwz   r25,0x5c(r1)
481 
        l.lwz   r26,0x60(r1)
482 
        l.lwz   r27,0x64(r1)
483 
        l.lwz   r28,0x68(r1)
484 
        l.lwz   r29,0x6c(r1)
485 
        l.lwz   r30,0x70(r1)
486 
        l.mfspr r31,r0,0x40
487 
        l.lwz   r31,0x74(r1)
488 
        l.lwz   r3,0x78(r1)
489 
 
490 
        l.addi  r1,r1,128
491 
        l.rfe
492 
        l.nop
493 
 
494 
_int_wrapper:
495 
        l.sw    0x8(r1),r4
496 
        l.sw    0xc(r1),r5
497 
        l.sw    0x10(r1),r6
498 
        l.sw    0x14(r1),r7
499 
        l.sw    0x18(r1),r8
500 
        l.sw    0x1c(r1),r9
501 
        l.sw    0x20(r1),r10
502 
        l.sw    0x24(r1),r11
503 
        l.sw    0x28(r1),r12
504 
        l.sw    0x2c(r1),r13
505 
        l.sw    0x30(r1),r14
506 
        l.sw    0x34(r1),r15
507 
        l.sw    0x38(r1),r16
508 
        l.sw    0x3c(r1),r17
509 
        l.sw    0x40(r1),r18
510 
        l.sw    0x44(r1),r19
511 
        l.sw    0x48(r1),r20
512 
        l.sw    0x4c(r1),r21
513 
        l.sw    0x50(r1),r22
514 
        l.sw    0x54(r1),r23
515 
        l.sw    0x58(r1),r24
516 
        l.sw    0x5c(r1),r25
517 
        l.sw    0x60(r1),r26
518 
        l.sw    0x64(r1),r27
519 
        l.sw    0x68(r1),r28
520 
        l.sw    0x6c(r1),r29
521 
        l.sw    0x70(r1),r30
522 
        l.sw    0x74(r1),r31
523 
        l.sw    0x78(r1),r3
524 
 
525 
        l.movhi r3,hi(_int_main)
526 
        l.ori   r3,r3,lo(_int_main)
527 
        l.jalr  r3
528 
        l.nop
529 
 
530 
        l.lwz   r2,0x4(r1)
531 
        l.lwz   r4,0x8(r1)
532 
        l.lwz   r5,0xc(r1)
533 
        l.lwz   r6,0x10(r1)
534 
        l.lwz   r7,0x14(r1)
535 
        l.lwz   r8,0x18(r1)
536 
        l.lwz   r9,0x1c(r1)
537 
        l.lwz   r10,0x20(r1)
538 
        l.lwz   r11,0x24(r1)
539 
        l.lwz   r12,0x28(r1)
540 
        l.lwz   r13,0x2c(r1)
541 
        l.lwz   r14,0x30(r1)
542 
        l.lwz   r15,0x34(r1)
543 
        l.lwz   r16,0x38(r1)
544 
        l.lwz   r17,0x3c(r1)
545 
        l.lwz   r18,0x40(r1)
546 
        l.lwz   r19,0x44(r1)
547 
        l.lwz   r20,0x48(r1)
548 
        l.lwz   r21,0x4c(r1)
549 
        l.lwz   r22,0x50(r1)
550 
        l.lwz   r23,0x54(r1)
551 
        l.lwz   r24,0x58(r1)
552 
        l.lwz   r25,0x5c(r1)
553 
        l.lwz   r26,0x60(r1)
554 
        l.lwz   r27,0x64(r1)
555 
        l.lwz   r28,0x68(r1)
556 
        l.lwz   r29,0x6c(r1)
557 
        l.lwz   r30,0x70(r1)
558 
        l.lwz   r31,0x74(r1)
559 
        l.lwz   r3,0x78(r1)
560 
 
561 
        l.mtspr r0,r0,SPR_PICSR
562 
 
563 
        l.addi  r1,r1,128
564 
        l.rfe
565 
        l.nop
566 
 
567 
_align:
568 
        l.sw    0x0c(r1),r3
569 
        l.sw    0x10(r1),r4
570 
        l.sw    0x14(r1),r5
571 
        l.sw    0x18(r1),r6
572 
        l.sw    0x1c(r1),r7
573 
        l.sw    0x20(r1),r8
574 
        l.sw    0x24(r1),r9
575 
        l.sw    0x28(r1),r10
576 
        l.sw    0x2c(r1),r11
577 
        l.sw    0x30(r1),r12
578 
        l.sw    0x34(r1),r13
579 
        l.sw    0x38(r1),r14
580 
        l.sw    0x3c(r1),r15
581 
        l.sw    0x40(r1),r16
582 
        l.sw    0x44(r1),r17
583 
        l.sw    0x48(r1),r18
584 
        l.sw    0x4c(r1),r19
585 
        l.sw    0x50(r1),r20
586 
        l.sw    0x54(r1),r21
587 
        l.sw    0x58(r1),r22
588 
        l.sw    0x5c(r1),r23
589 
        l.sw    0x60(r1),r24
590 
        l.sw    0x64(r1),r25
591 
        l.sw    0x68(r1),r26
592 
        l.sw    0x6c(r1),r27
593 
        l.sw    0x70(r1),r28
594 
        l.sw    0x74(r1),r29
595 
        l.sw    0x78(r1),r30
596 
        l.sw    0x7c(r1),r31
597 
 
598 
        l.mfspr r2,r0,SPR_EEAR_BASE /* Load the efective addres */
599 
        l.mfspr r5,r0,SPR_EPCR_BASE /* Load the insn address */
600 
 
601 
        l.lwz   r3,0(r5)    /* Load insn */
602 
        l.srli  r4,r3,26    /* Shift left to get the insn opcode */
603 
 
604 
        l.sfeqi r4,0x00     /* Check if the load/store insn is in delay slot */
605 
        l.bf    jmp
606 
        l.sfeqi r4,0x01
607 
        l.bf    jmp
608 
        l.sfeqi r4,0x03
609 
        l.bf    jmp
610 
        l.sfeqi r4,0x04
611 
        l.bf    jmp
612 
        l.sfeqi r4,0x11
613 
        l.bf    jr
614 
        l.sfeqi r4,0x12
615 
        l.bf    jr
616 
        l.nop
617 
        l.j     1f
618 
        l.addi  r5,r5,4     /* Increment PC to get return insn address */
619 
 
620 
jmp:
621 
        l.slli  r4,r3,6     /* Get the signed extended jump length */
622 
        l.srai  r4,r4,4
623 
 
624 
        l.lwz   r3,4(r5)      /* Load the real load/store insn */
625 
 
626 
        l.add   r5,r5,r4      /* Calculate jump target address */
627 
 
628 
        l.j     1f
629 
        l.srli  r4,r3,26    /* Shift left to get the insn opcode */
630 
 
631 
jr:
632 
        l.slli  r4,r3,9     /* Shift to get the reg nb */
633 
        l.andi  r4,r4,0x7c
634 
 
635 
        l.lwz   r3,4(r5)    /* Load the real load/store insn */
636 
 
637 
        l.add   r4,r4,r1    /* Load the jump register value from the stack */
638 
        l.lwz   r5,0(r4)
639 
 
640 
        l.srli  r4,r3,26    /* Shift left to get the insn opcode */
641 
 
642 
 
643 
1:      l.mtspr r0,r5,SPR_EPCR_BASE
644 
 
645 
        l.sfeqi r4,0x26
646 
        l.bf    lhs
647 
        l.sfeqi r4,0x25
648 
        l.bf    lhz
649 
        l.sfeqi r4,0x22
650 
        l.bf    lws
651 
        l.sfeqi r4,0x21
652 
        l.bf    lwz
653 
        l.sfeqi r4,0x37
654 
        l.bf    sh
655 
        l.sfeqi r4,0x35
656 
        l.bf    sw
657 
        l.nop
658 
 
659 
1:      l.j     1b      /* I don't know what to do */
660 
        l.nop
661 
 
662 
lhs:    l.lbs   r5,0(r2)
663 
        l.slli  r5,r5,8
664 
        l.lbz   r6,1(r2)
665 
        l.or    r5,r5,r6
666 
        l.srli  r4,r3,19
667 
        l.andi  r4,r4,0x7c
668 
        l.add   r4,r4,r1
669 
        l.j     align_end
670 
        l.sw    0(r4),r5
671 
 
672 
lhz:    l.lbz   r5,0(r2)
673 
        l.slli  r5,r5,8
674 
        l.lbz   r6,1(r2)
675 
        l.or    r5,r5,r6
676 
        l.srli  r4,r3,19
677 
        l.andi  r4,r4,0x7c
678 
        l.add   r4,r4,r1
679 
        l.j     align_end
680 
        l.sw    0(r4),r5
681 
 
682 
lws:    l.lbs   r5,0(r2)
683 
        l.slli  r5,r5,24
684 
        l.lbz   r6,1(r2)
685 
        l.slli  r6,r6,16
686 
        l.or    r5,r5,r6
687 
        l.lbz   r6,2(r2)
688 
        l.slli  r6,r6,8
689 
        l.or    r5,r5,r6
690 
        l.lbz   r6,3(r2)
691 
        l.or    r5,r5,r6
692 
        l.srli  r4,r3,19
693 
        l.andi  r4,r4,0x7c
694 
        l.add   r4,r4,r1
695 
        l.j     align_end
696 
        l.sw    0(r4),r5
697 
 
698 
lwz:    l.lbz   r5,0(r2)
699 
        l.slli  r5,r5,24
700 
        l.lbz   r6,1(r2)
701 
        l.slli  r6,r6,16
702 
        l.or    r5,r5,r6
703 
        l.lbz   r6,2(r2)
704 
        l.slli  r6,r6,8
705 
        l.or    r5,r5,r6
706 
        l.lbz   r6,3(r2)
707 
        l.or    r5,r5,r6
708 
        l.srli  r4,r3,19
709 
        l.andi  r4,r4,0x7c
710 
        l.add   r4,r4,r1
711 
        l.j     align_end
712 
        l.sw    0(r4),r5
713 
 
714 
sh:
715 
        l.srli  r4,r3,9
716 
        l.andi  r4,r4,0x7c
717 
        l.add   r4,r4,r1
718 
        l.lwz   r5,0(r4)
719 
        l.sb    1(r2),r5
720 
        l.srli  r5,r5,8
721 
        l.j     align_end
722 
        l.sb    0(r2),r5
723 
 
724 
sw:
725 
        l.srli  r4,r3,9
726 
        l.andi  r4,r4,0x7c
727 
        l.add   r4,r4,r1
728 
        l.lwz   r5,0(r4)
729 
        l.sb    3(r2),r5
730 
        l.srli  r5,r5,8
731 
        l.sb    2(r2),r5
732 
        l.srli  r5,r5,8
733 
        l.sb    1(r2),r5
734 
        l.srli  r5,r5,8
735 
        l.j     align_end
736 
        l.sb    0(r2),r5
737 
 
738 
align_end:
739 
        l.lwz   r2,0x08(r1)
740 
        l.lwz   r3,0x0c(r1)
741 
        l.lwz   r4,0x10(r1)
742 
        l.lwz   r5,0x14(r1)
743 
        l.lwz   r6,0x18(r1)
744 
        l.lwz   r7,0x1c(r1)
745 
        l.lwz   r8,0x20(r1)
746 
        l.lwz   r9,0x24(r1)
747 
        l.lwz   r10,0x28(r1)
748 
        l.lwz   r11,0x2c(r1)
749 
        l.lwz   r12,0x30(r1)
750 
        l.lwz   r13,0x34(r1)
751 
        l.lwz   r14,0x38(r1)
752 
        l.lwz   r15,0x3c(r1)
753 
        l.lwz   r16,0x40(r1)
754 
        l.lwz   r17,0x44(r1)
755 
        l.lwz   r18,0x48(r1)
756 
        l.lwz   r19,0x4c(r1)
757 
        l.lwz   r20,0x50(r1)
758 
        l.lwz   r21,0x54(r1)
759 
        l.lwz   r22,0x58(r1)
760 
        l.lwz   r23,0x5c(r1)
761 
        l.lwz   r24,0x60(r1)
762 
        l.lwz   r25,0x64(r1)
763 
        l.lwz   r26,0x68(r1)
764 
        l.lwz   r27,0x6c(r1)
765 
        l.lwz   r28,0x70(r1)
766 
        l.lwz   r29,0x74(r1)
767 
        l.lwz   r30,0x78(r1)
768 
        l.mfspr r31,r0,0x40
769 
        l.lwz   r31,0x7c(r1)
770 
        l.addi  r1,r1,128
771 
        l.rfe

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