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URL https://opencores.org/ocsvn/or1k_soc_on_altera_embedded_dev_kit/or1k_soc_on_altera_embedded_dev_kit/trunk

Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [sw/] [sd_boot_loader/] [main.c] - Blame information for rev 22

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Line No. Rev Author Line
1 12 xianfeng 
 /*
2 
 * SD/MMC card bootloader for OR1k SoC
3 
 *
4 
 * Copyright (c) 2008 by:
5 13 xianfeng 
 *      Xianfeng Zeng <xianfeng.zeng@gmail.com, Xianfeng.zeng@SierraAtlantic.com>
6 12 xianfeng 
 *
7 
 * This program is free software; you can redistribute it and/or modify
8 
 * it under the terms of the BSD Licence, GNU General Public License
9 
 * as published by the Free Software Foundation; either version 2 of the
10 
 * License, or (at your option) any later version
11 
 *
12 
 * ChangeLog:
13 
 *      2009-10-05 12:56:55   xzeng
14 
 *          Init.
15 
 *
16 
 */
17 
 
18 
 
19 
#define INCLUDED_FROM_C_FILE
20 
 
21 
#include "orsocdef.h"
22 
#include "board.h"
23 
 
24 
 
25 
#define DEBUG 1
26 
 
27 
#define barrier() __asm__ __volatile__("": : :"memory")
28 
 
29 
#ifdef DEBUG
30 22 xianfeng 
void or1k_putc(int c)
31 12 xianfeng 
{
32 
        while ( 0x20 != (REG8(UART_BASE_ADD+5) & 0x20) )
33 
                ;
34 
 
35 
        REG8(UART_BASE_ADD) = c;
36 
}
37 
 
38 
void print(unsigned char *c)
39 
{
40 
        uint32 i;
41 
 
42 
        if (c == NULL)
43 
                return;
44 
 
45 
        for (i = 0; c[i] != 0; i++) {
46 22 xianfeng 
                or1k_putc(c[i]);
47 12 xianfeng 
        }
48 
}
49 
 
50 
void print32bit (long unsigned int val)
51 
{
52 
  int i;
53 
  unsigned long int myNibble;
54 
  char myChar;
55 
 
56 
  for (i=0;i<8;i++) {
57 
    myNibble =  (val >> 28) & 0xfUL;
58 
    if (myNibble <= 0x9)
59 
      myChar = (char) myNibble + 0x30;
60 
    else
61 
      myChar = (char) myNibble + 0x37;
62 22 xianfeng 
    or1k_putc (myChar);
63 12 xianfeng 
    val = val << 4;
64 
  }
65 22 xianfeng 
  or1k_putc ('\n');
66 
  or1k_putc ('\r');
67 12 xianfeng 
}
68 
 
69 
 
70 
#else
71 22 xianfeng 
#define or1k_putc(a)
72 12 xianfeng 
#define print(a)
73 
#endif
74 
 
75 
 
76 
void do_sleep()
77 
{
78 
        uint32 i;
79 
        for (i = 0; i < 200000; i++)
80 
                ;
81 
}
82 
 
83 
void do_sleep2()
84 
{
85 
        uint32 i;
86 
        for (i = 0; i < 1000; i++)
87 
                ;
88 
}
89 
 
90 
/******************************************************************************/
91 
/*                           G P I O   W  R I T E                             */
92 
/******************************************************************************/
93 
 
94 
// Write to the GPIO (32 bits)
95 
 
96 
void GPIO_Write(uint32 GPIO_data)
97 
{
98 
   REG32(GPIO_BASE + RGPIO_OUT) = GPIO_data;
99 
}
100 
 
101 
 
102 
/******************************************************************************/
103 
/*                           F O R   s p i M A S T E R                        */
104 
/******************************************************************************/
105 17 xianfeng 
 
106 12 xianfeng 
//Initialize
107 
int spiMaster_init()
108 
{
109 
        uint8 data;
110 
        int   i;
111 
 
112 17 xianfeng 
        REG8(SD_BASE_ADD + SD_CLK_DEL_REG) = 0x1;
113 12 xianfeng 
 
114 
        for (i = 0; i < 5; i++) {
115 
                REG8(SD_BASE_ADD + SD_TRANS_TYPE_REG) = SD_INIT_SD;
116 
                REG8(SD_BASE_ADD + SD_TRANS_CTRL_REG) = 1; // TRANS_START;
117 
 
118 
                do_sleep();
119 
 
120 
                while (REG8(SD_BASE_ADD + SD_TRANS_STS_REG) & 0x1) { // exit while !TRABS_BUSY
121 
                        ;
122 
                }
123 
 
124 
                data = REG8(SD_BASE_ADD + SD_TRANS_ERROR_REG) & 0x3;
125 
 
126 17 xianfeng 
                if (data == 0) {
127 
                        return 0;
128 
                }
129 12 xianfeng 
        }
130 
        return data;
131 
}
132 
 
133 
unsigned char data[512];
134 
 
135 
int copy_sd2ddr(void)
136 
{
137 
 
138 
        int i, j;
139 
        uint8 data;
140 
        unsigned char transError;
141 
 
142 
        uint32 blockCnt;
143 
        uint32 numBlocks = 2 * 1024 * 10; // How mang blocks will be copied
144 
 
145 
        uint32 ddr_offset = 0;
146 
 
147 22 xianfeng 
        print("\n\r");
148 
        print("Copying SD image to DDR SDRAM...\n\r");
149 12 xianfeng 
        print("Blocks:");
150 
        print32bit((long unsigned int)numBlocks);
151 
 
152 
        for (blockCnt = 0; blockCnt < numBlocks; blockCnt++) {
153 
                REG8(SD_BASE_ADD + SD_ADDR_7_0_REG)   = 0;
154 
                REG8(SD_BASE_ADD + SD_ADDR_15_8_REG)  = (unsigned char) ((ddr_offset >> 8) & 0xff);
155 
                REG8(SD_BASE_ADD + SD_ADDR_23_16_REG) = (unsigned char) ((ddr_offset >> 16) & 0xff);
156 
                REG8(SD_BASE_ADD + SD_ADDR_31_24_REG) = (unsigned char) ((ddr_offset >> 24) & 0xff);
157 
 
158 
 
159 
                REG8(SD_BASE_ADD + SD_TRANS_TYPE_REG) = SD_RW_READ_SD_BLOCK;
160 
                REG8(SD_BASE_ADD + SD_RX_FIFO_CONTROL_REG) = 0x1; // Clean the RX FIFO
161 
                REG8(SD_BASE_ADD + SD_TRANS_CTRL_REG) = 0x1; //TRANS_START
162 
                while (REG8(SD_BASE_ADD + SD_TRANS_STS_REG) & 0x1) { // exit while !TRABS_BUSY
163 
                        ;
164 
                }
165 
 
166 
                transError = REG8(SD_BASE_ADD + SD_TRANS_ERROR_REG) & 0xc;
167 
                if ( transError == SD_READ_NO_ERROR) {
168 
                        for (i = 0; i < 512; i++) {
169 
                                data = REG8(SD_BASE_ADD + SD_RX_FIFO_DATA_REG) ;
170 
                                REG8(DDR_SDRAM_BASE_ADDR + ddr_offset + i) = data ;
171 
//                              print32bit((long unsigned int)data);
172 
                        }
173 
                        if ((blockCnt % 0x40) == 0) {
174 22 xianfeng 
                                or1k_putc('.');
175 12 xianfeng 
                                j++;
176 
                        }
177 
                        if (j == 20) {
178 
                                j = 0;
179 
                                print("\n\r");
180 
                        }
181 
 
182 
                        ddr_offset += 512;
183 
                } else {
184 22 xianfeng 
                        or1k_putc('R');
185 12 xianfeng 
                        j++;
186 
                        if (j == 20) {
187 
                                j = 0;
188 
                                print("\n\r");
189 
                        }
190 
                        spiMaster_init(); // Init again and retry
191 
                        blockCnt--; // read the same block again
192 
                }
193 
        }
194 
 
195 
        print("\r\nSD Copy Done!\n\r");
196 
}
197 
 
198 
 
199 
/******************************************************************************/
200 
/*                        TEST EXTERNAL DDR SDRAM                             */
201 
/******************************************************************************/
202 
 
203 
void ddr_sdram_sample_test()
204 
{
205 
        uint32 int32;
206 
        uint16 int16;
207 
        uint8  int8;
208 
        int    i;
209 
 
210 
        REG32(DDR_SDRAM_BASE_ADDR) = 0x12345678;
211 
        int32 = REG32(DDR_SDRAM_BASE_ADDR);
212 
 
213 
        REG16(DDR_SDRAM_BASE_ADDR + 10) = 0x55aa;
214 
        int16 = REG16(DDR_SDRAM_BASE_ADDR + 10);
215 
 
216 
        REG8(DDR_SDRAM_BASE_ADDR + 20) = 0x5a;
217 
        int8 = REG8(DDR_SDRAM_BASE_ADDR + 20);
218 
 
219 
        if (REG8(DDR_SDRAM_BASE_ADDR + 20)  != 0x5a)
220 
                print ("DDR SDRAM accesses short type Error:20!\n\r");
221 
 
222 
        REG8(DDR_SDRAM_BASE_ADDR + 100) = 0x12;
223 
        REG8(DDR_SDRAM_BASE_ADDR + 101) = 0x34;
224 
        REG8(DDR_SDRAM_BASE_ADDR + 102) = 0x56;
225 
        REG8(DDR_SDRAM_BASE_ADDR + 103) = 0x78;
226 
 
227 
        int32 = REG32(DDR_SDRAM_BASE_ADDR + 100);
228 
 
229 
        if (REG8(DDR_SDRAM_BASE_ADDR + 100)  != 0x12)
230 
                print ("DDR SDRAM accesses char type Error:100!\n\r");
231 
        if (REG8(DDR_SDRAM_BASE_ADDR + 101)  != 0x34)
232 
                print ("DDR SDRAM accesses char type Error:101!\n\r");
233 
        if (REG8(DDR_SDRAM_BASE_ADDR + 102)  != 0x56)
234 
                print ("DDR SDRAM accesses char type Error:102!\n\r");
235 
        if (REG8(DDR_SDRAM_BASE_ADDR + 103)  != 0x78)
236 
                print ("DDR SDRAM accesses char type Error:103!\n\r");
237 
 
238 
        for (i=0;i<64;i++) {
239 
                REG8(DDR_SDRAM_BASE_ADDR + i) = i;
240 
        }
241 
 
242 
        for (i=0;i<64;i++) {
243 
                REG8(0x3900+i) = REG8(DDR_SDRAM_BASE_ADDR + i);
244 
        }
245 
 
246 
        print ("DDR SDRAM sample test done.\n\r");
247 
}
248 
 
249 
 
250 
/*$$EXTERNAL EXEPTIONS*/
251 
/******************************************************************************/
252 
/*                  E X T E R N A L   E X E P T I O N S                       */
253 
/******************************************************************************/
254 
 
255 
void external_exeption()
256 
{
257 
  REG uint8 i;
258 
  REG uint32 PicSr,sr;
259 
}
260 
 
261 
 
262 
/*$$MAIN*/
263 
/******************************************************************************/
264 
/*                                                                            */
265 
/*                       M A I N   P R O G R A M                              */
266 
/*                                                                            */
267 
/******************************************************************************/
268 
 
269 
void Start()
270 
{
271 
  uint32 i;
272 
  uint8  str[9];
273 
 
274 
  // Configure GPIO
275 
  REG32(GPIO_BASE + RGPIO_OE)   = 0xff;  // bit0-7 = outputs, bit8-31 = inputs
276 
  REG32(GPIO_BASE + RGPIO_INTE) = 0x0;   // Disable interrupts from GPIO
277 
 
278 
  print("\n\r\n\t");
279 
  print("==OpenRisc 1200 SOC==\n\r\n");
280 
  GPIO_Write(~0x0);
281 
 
282 
  print("\n\r");
283 
 
284 17 xianfeng 
  print("SD Card Bootloader, v0.2\n\r");
285 13 xianfeng 
  print("Xianfeng Zeng, 2009 SA\n\r");
286 
  print("Xianfeng@opencores.org\n\r");
287 
  print("http://www.opencores.org/project,or1k_soc_on_altera_embedded_dev_kit\n\r");
288 12 xianfeng 
 
289 
  print("\n\r");
290 
 
291 
  print("System Clock: 30MHz\n\r\n");
292 
 
293 
  print("DDR SDRAM Base Address: 0x00000000 - 32MB\n\r");
294 
  print("Ethernet Base Address:  0x20000000  IRQ 4\n\r");
295 
  print("UART Base Address:      0x30000000  IRQ 2\n\r");
296 
  print("GPIO Base Address:      0x40000000  IRQ 3\n\r");
297 
  print("SD Card Base Address:   0x50000000\n\r");
298 
  print("SRAM Base Address:      0xF0000000 - 16KB\n\r");
299 
  print("\r\n\n");
300 
 
301 
 
302 
  print("Init SD Card:");
303 17 xianfeng 
  REG8(SD_BASE_ADD + SD_TRANS_CTRL_REG) = 0x1;  /* reset spiMaster */
304 
  do_sleep();
305 
  REG8(SD_BASE_ADD + SD_TRANS_CTRL_REG) = 0x0;
306 12 xianfeng 
  if (spiMaster_init() == 0) {
307 
        print("Passed!\n\r");
308 
  } else {
309 
        print("Failed!\n\r");
310 
  }
311 
 
312 
  ddr_sdram_sample_test();
313 
  copy_sd2ddr();
314 
 
315 
  GPIO_Write(~0x1);
316 
 
317 
  print("\n\r");
318 
 
319 
  print("Jump to DDR SDRAM: 0x100\n\r");
320 
  jumpToRAM();
321 
 
322 
  print("Should not get here!!:\n\r");
323 
  while(TRUE) {
324 
        do_sleep();
325 22 xianfeng 
        or1k_putc('.');
326 12 xianfeng 
        GPIO_Write(~0x0);  // Test finished
327 
        do_sleep();
328 
        GPIO_Write(~0x1);
329 
        do_sleep();
330 
        GPIO_Write(~0x2);
331 
        do_sleep();
332 
        GPIO_Write(~0x4);
333 
        do_sleep();
334 
        GPIO_Write(~0x8);
335 
 
336 
        if (i == 39) {
337 
                print("\n\r");
338 
                i = 0;
339 
        } else
340 
                i++;
341 
  }
342 
}
343 
 

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