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`include "../../../rtl/verilog/gfx/gfx_wbs.v"
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`include "../../../rtl/verilog/gfx/gfx_wbm_write.v"
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`include "../../../rtl/verilog/gfx/gfx_wbm_read.v"
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`include "../../../rtl/verilog/gfx/gfx_vector_processor.v"
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`include "../../../rtl/verilog/gfx/gfx_rasterizer.v"
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`include "../../../rtl/verilog/gfx/gfx_fragment_processor.v"
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`include "../../../rtl/verilog/gfx/gfx_blender.v"
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`include "../../../rtl/verilog/gfx/gfx_renderer.v"
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`include "../../../rtl/verilog/gfx/gfx_top.v"
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`include "../../../rtl/verilog/gfx/basic_fifo.v"
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`include "../../../rtl/verilog/gfx/gfx_color.v"
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`include "../../../rtl/verilog/gfx/gfx_wbm_read_arbiter.v"
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`include "../../../rtl/verilog/gfx/gfx_line.v"
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module gfx_bench();
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// Common wishbone signals
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reg wb_clk_i; // master clock reg
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reg wb_rst_i; // Asynchronous active high reset
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wire wb_inta_o; // interrupt
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// Wishbone master signals (write)
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wire wbm_write_cyc_o; // cycle wire
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wire wbm_write_stb_o; // strobe wire
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wire [ 2:0] wbm_write_cti_o; // cycle type id
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wire [ 1:0] wbm_write_bte_o; // burst type extension
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wire wbm_write_we_o; // write enable wire
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wire [31:0] wbm_write_adr_o; // address wire
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wire [ 3:0] wbm_write_sel_o; // byte select wires (only 32bits accesses are supported)
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reg wbm_write_ack_i; // wishbone cycle acknowledge
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reg wbm_write_err_i; // wishbone cycle error
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wire [31:0] wbm_write_dat_o; // wishbone data out
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// Wishbone master signals (read)
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wire wbm_read_cyc_o; // cycle wire
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wire wbm_read_stb_o; // strobe wire
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wire [ 2:0] wbm_read_cti_o; // cycle type id
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wire [ 1:0] wbm_read_bte_o; // burst type extension
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wire wbm_read_we_o; // write enable wire
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wire [31:0] wbm_read_adr_o; // address wire
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wire [ 3:0] wbm_read_sel_o; // byte select wires (only 32bits accesses are supported)
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reg wbm_read_ack_i; // wishbone cycle acknowledge
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reg wbm_read_err_i; // wishbone cycle error
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reg [31:0] wbm_read_dat_i; // wishbone data in
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// Wishbone slave signals
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reg wbs_cyc_i; // cycle reg
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reg wbs_stb_i; // strobe reg
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reg [ 2:0] wbs_cti_i; // cycle type id
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reg [ 1:0] wbs_bte_i; // burst type extension
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reg wbs_we_i; // write enable reg
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reg [31:0] wbs_adr_i; // address reg
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reg [ 3:0] wbs_sel_i; // byte select reg (only 32bits accesses are supported)
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wire wbs_ack_o; // wishbone cycle acknowledge
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wire wbs_err_o; // wishbone cycle error
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reg [31:0] wbs_dat_i; // wishbone data in
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wire [31:0] wbs_dat_o; // wishbone data out
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parameter GFX_VMEM = 32'h00800000;
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parameter GFX_CTRL = 32'h000;
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parameter GFX_STATUS = 32'h004;
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parameter GFX_SRC_PIXEL0 = 32'h008;
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parameter GFX_SRC_PIXEL1 = 32'h00c;
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parameter GFX_DEST_PIXEL0 = 32'h010;
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parameter GFX_DEST_PIXEL1 = 32'h014;
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parameter GFX_CLIP_PIXEL0 = 32'h018;
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parameter GFX_CLIP_PIXEL1 = 32'h01c;
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parameter GFX_COLOR = 32'h020;
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parameter GFX_TARGET_BASE = 32'h024;
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parameter GFX_TARGET_SIZE = 32'h028;
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parameter GFX_TEX0_BASE = 32'h02c;
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parameter GFX_TEX0_SIZE = 32'h030;
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parameter GFX_ALPHA = 32'h034;
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parameter GFX_COLORKEY = 32'h038;
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parameter GFX_CTRL_CD8 = 32'h00000000; /* Color Depth 8 */
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parameter GFX_CTRL_CD16 = 32'h00000001; /* Color Depth 16 */
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parameter GFX_CTRL_CD24 = 32'h00000002; /* Color Depth 24 */ // Not supported!
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parameter GFX_CTRL_CD32 = 32'h00000003; /* Color Depth 32 */
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parameter GFX_CTRL_CDMASK = 32'h00000003; /* All color depth bits */
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parameter GFX_TEXTURE_ENABLE = 32'h00000004; /* Enable Texture Reads */
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parameter GFX_BLEND_ENABLE = 32'h00000008; /* Enable Alpha Blending */
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parameter GFX_COLORKEY_ENABLE = 32'h00000010; /* Enable Colorkeying */
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parameter GFX_CTRL_RECT = 32'h00000100; /* Put rect */
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parameter GFX_CTRL_LINE = 32'h00000200; /* Put line */
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initial begin
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$dumpfile("gfx.vcd");
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$dumpvars(0,gfx_bench);
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// init values
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wb_clk_i = 0;
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wb_rst_i = 1;
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wbm_write_ack_i = 0;
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wbm_read_ack_i = 0;
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wbm_write_err_i = 0;
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wbm_read_err_i = 0;
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wbs_cyc_i = 0;
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wbs_cti_i = 0;
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wbs_bte_i = 0;
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wbs_adr_i = 0;
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wbs_sel_i = 4'b1111;
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wbs_dat_i = 0;
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// Can be high all the time
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wbs_we_i = 1;
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wbs_stb_i = 1;
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// wbm_read_dat_i = 32'hf18ff18f;
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// Set the texture read pixel
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wbm_read_dat_i = 32'h00000000;
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// Finish the reset of the component
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#2 wb_rst_i = 0;
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// Initialize color register
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#2 wbs_cyc_i = 1;
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wbs_adr_i = GFX_COLOR;
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wbs_dat_i = 32'h12345671;
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#4 wbs_cyc_i = 0;
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// Initialize traget base
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#2 wbs_cyc_i = 1;
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wbs_dat_i = GFX_VMEM;
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wbs_adr_i = GFX_TARGET_BASE;
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#4 wbs_cyc_i = 0;
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// oc_gfx_set_videomode(640, 480, 16);
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#2 wbs_cyc_i = 1;
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wbs_dat_i = 32'h028001e0; // (640 << 16) | 480
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wbs_adr_i = GFX_TEX0_SIZE;
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#4 wbs_cyc_i = 0;
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// Set 16 bit color depth
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#2 wbs_cyc_i = 1;
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wbs_dat_i = GFX_CTRL_CD16;
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wbs_adr_i = GFX_CTRL;
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#4 wbs_cyc_i = 0;
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// Enable colorkey
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#2 wbs_cyc_i = 1;
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wbs_dat_i = 32'h0000F18F; // pink color
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wbs_adr_i = GFX_COLORKEY;
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#4 wbs_cyc_i = 0;
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#2 wbs_cyc_i = 1;
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wbs_dat_i = GFX_COLORKEY_ENABLE | GFX_CTRL_CD16;
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wbs_adr_i = GFX_CTRL;
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#4 wbs_cyc_i = 0;
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// set cliparea
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#2 wbs_cyc_i = 1;
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wbs_dat_i = 32'h00000000; // (0 << 16) | 0
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wbs_adr_i = GFX_CLIP_PIXEL0; // Clip Pixel 0
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#4 wbs_cyc_i = 0;
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#2 wbs_cyc_i = 1;
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wbs_dat_i = 32'h028001e0; // (640 << 16) | 480
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wbs_adr_i = GFX_CLIP_PIXEL1; // Clip Pixel 1
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#4 wbs_cyc_i = 0;
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// oc_gfx_enable_tex0(1)
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#2 wbs_cyc_i = 1;
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wbs_dat_i = GFX_TEXTURE_ENABLE | GFX_COLORKEY_ENABLE | GFX_CTRL_CD16;
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wbs_adr_i = GFX_CTRL;
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#4 wbs_cyc_i = 0;
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// oc_gfx_bind_tex0(0x01f00000, 10, 10)
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#2 wbs_cyc_i = 1;
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wbs_dat_i = GFX_VMEM;
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wbs_adr_i = GFX_TEX0_BASE;
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#4 wbs_cyc_i = 0;
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#2 wbs_cyc_i = 1;
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wbs_dat_i = 32'h000a000a; // (10 << 16) | 10
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wbs_adr_i = GFX_TEX0_SIZE;
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#4 wbs_cyc_i = 0;
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// oc_gfx_rect(110, 110, 115, 115, 0xf800f800);
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#2 wbs_cyc_i = 1;
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wbs_dat_i = 32'h006e006e; // (110 << 16) | 110
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wbs_adr_i = GFX_DEST_PIXEL0;
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#4 wbs_cyc_i = 0;
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#2 wbs_cyc_i = 1;
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wbs_dat_i = 32'h00780073; // (115 << 16) | 115
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wbs_adr_i = GFX_DEST_PIXEL1;
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#4 wbs_cyc_i = 0;
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#2 wbs_cyc_i = 1;
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wbs_dat_i = 32'hf800f800; // Red
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wbs_adr_i = GFX_COLOR;
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#4 wbs_cyc_i = 0;
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#2 wbs_cyc_i = 1;
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wbs_dat_i = GFX_CTRL_RECT | GFX_TEXTURE_ENABLE | GFX_COLORKEY_ENABLE | GFX_CTRL_CD16;
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wbs_adr_i = GFX_CTRL;
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#4 wbs_cyc_i = 0;
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// After a while, set every pixel read to the color key (demonstrates that colorkeyed pixels are not written)
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#200 wbm_read_dat_i = 32'hf18ff18f;
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// TODO: Demonstrate alpha blending
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/*
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wbm_read_dat_i = #40 32'hffffffff;
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// oc_gfx_rect(110, 110, 115, 115, 0xf800f800);
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#200 wbs_cyc_i = 1;
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wbs_dat_i = 32'h006e006e; // (110 << 16) | 110
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wbs_adr_i = GFX_DEST_PIXEL0;
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#4 wbs_cyc_i = 0;
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#2 wbs_cyc_i = 1;
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wbs_dat_i = 32'h00730073; // (115 << 16) | 115
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wbs_adr_i = GFX_DEST_PIXEL1;
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#4 wbs_cyc_i = 0;
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// set cliparea
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#2 wbs_cyc_i = 1;
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wbs_dat_i = 32'h00700070; // (112 << 16) | 112
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wbs_adr_i = GFX_CLIP_PIXEL0;
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#4 wbs_cyc_i = 0;
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#2 wbs_cyc_i = 1;
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wbs_dat_i = 32'h00720072; // (114 << 16) | 114
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wbs_adr_i = GFX_CLIP_PIXEL1;
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#4 wbs_cyc_i = 0;
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#2 wbs_cyc_i = 1;
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wbs_dat_i = GFX_CTRL_RECT | GFX_TEXTURE_ENABLE | GFX_CTRL_CD16;
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wbs_adr_i = GFX_CTRL;
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#4 wbs_cyc_i = 0;
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*/
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// Draw a bunch of lines
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//draw line ############### 1
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#2 wbs_cyc_i = 1;
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wbs_dat_i = 32'h00040004; // (110 << 16) | 110
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wbs_adr_i = GFX_DEST_PIXEL0;
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#4 wbs_cyc_i = 0;
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#2 wbs_cyc_i = 1;
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wbs_dat_i = 32'h00080006; // (115 << 16) | 115
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wbs_adr_i = GFX_DEST_PIXEL1;
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#4 wbs_cyc_i = 0;
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#2 wbs_cyc_i = 1;
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wbs_dat_i = GFX_CTRL_LINE | GFX_CTRL_CD16;
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wbs_adr_i = GFX_CTRL;
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#4 wbs_cyc_i = 0;
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//#########################
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//draw line ############### 2
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#10 wbs_cyc_i = 1;
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wbs_dat_i = 32'h00040004; // (110 << 16) | 110
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wbs_adr_i = GFX_DEST_PIXEL0;
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#4 wbs_cyc_i = 0;
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#2 wbs_cyc_i = 1;
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wbs_dat_i = 32'h00060008; // (115 << 16) | 115
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wbs_adr_i = GFX_DEST_PIXEL1;
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#4 wbs_cyc_i = 0;
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#2 wbs_cyc_i = 1;
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wbs_dat_i = GFX_CTRL_LINE | GFX_CTRL_CD16;
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wbs_adr_i = GFX_CTRL;
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#4 wbs_cyc_i = 0;
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//#########################
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281 |
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//draw line ############### 3
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#10 wbs_cyc_i = 1;
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wbs_dat_i = 32'h00040004; // (110 << 16) | 110
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wbs_adr_i = GFX_DEST_PIXEL0;
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#4 wbs_cyc_i = 0;
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#2 wbs_cyc_i = 1;
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wbs_dat_i = 32'h00020008; // (115 << 16) | 115
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wbs_adr_i = GFX_DEST_PIXEL1;
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#4 wbs_cyc_i = 0;
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#2 wbs_cyc_i = 1;
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wbs_dat_i = GFX_CTRL_LINE | GFX_CTRL_CD16;
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wbs_adr_i = GFX_CTRL;
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#4 wbs_cyc_i = 0;
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//#########################
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298 |
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//draw line ############### 4
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300 |
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#10 wbs_cyc_i = 1;
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wbs_dat_i = 32'h00040004; // (110 << 16) | 110
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wbs_adr_i = GFX_DEST_PIXEL0;
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#4 wbs_cyc_i = 0;
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#2 wbs_cyc_i = 1;
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wbs_dat_i = 32'h00000006; // (115 << 16) | 115
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wbs_adr_i = GFX_DEST_PIXEL1;
|
308 |
|
|
#4 wbs_cyc_i = 0;
|
309 |
|
|
|
310 |
|
|
#2 wbs_cyc_i = 1;
|
311 |
|
|
wbs_dat_i = GFX_CTRL_LINE | GFX_CTRL_CD16;
|
312 |
|
|
wbs_adr_i = GFX_CTRL;
|
313 |
|
|
#4 wbs_cyc_i = 0;
|
314 |
|
|
//#########################
|
315 |
|
|
|
316 |
|
|
//draw line ############### 5
|
317 |
|
|
#10 wbs_cyc_i = 1;
|
318 |
|
|
wbs_dat_i = 32'h00040004; // (110 << 16) | 110
|
319 |
|
|
wbs_adr_i = GFX_DEST_PIXEL0;
|
320 |
|
|
#4 wbs_cyc_i = 0;
|
321 |
|
|
|
322 |
|
|
#2 wbs_cyc_i = 1;
|
323 |
|
|
wbs_dat_i = 32'h00000002; // (115 << 16) | 115
|
324 |
|
|
wbs_adr_i = GFX_DEST_PIXEL1;
|
325 |
|
|
#4 wbs_cyc_i = 0;
|
326 |
|
|
|
327 |
|
|
#2 wbs_cyc_i = 1;
|
328 |
|
|
wbs_dat_i = GFX_CTRL_LINE | GFX_CTRL_CD16;
|
329 |
|
|
wbs_adr_i = GFX_CTRL;
|
330 |
|
|
#4 wbs_cyc_i = 0;
|
331 |
|
|
//#########################
|
332 |
|
|
|
333 |
|
|
//draw line ############### 6
|
334 |
|
|
#10 wbs_cyc_i = 1;
|
335 |
|
|
wbs_dat_i = 32'h00040004; // (110 << 16) | 110
|
336 |
|
|
wbs_adr_i = GFX_DEST_PIXEL0;
|
337 |
|
|
#4 wbs_cyc_i = 0;
|
338 |
|
|
|
339 |
|
|
#2 wbs_cyc_i = 1;
|
340 |
|
|
wbs_dat_i = 32'h00020000; // (115 << 16) | 115
|
341 |
|
|
wbs_adr_i = GFX_DEST_PIXEL1;
|
342 |
|
|
#4 wbs_cyc_i = 0;
|
343 |
|
|
|
344 |
|
|
#2 wbs_cyc_i = 1;
|
345 |
|
|
wbs_dat_i = GFX_CTRL_LINE | GFX_CTRL_CD16;
|
346 |
|
|
wbs_adr_i = GFX_CTRL;
|
347 |
|
|
#4 wbs_cyc_i = 0;
|
348 |
|
|
//#########################
|
349 |
|
|
|
350 |
|
|
//draw line ############### 7
|
351 |
|
|
#10 wbs_cyc_i = 1;
|
352 |
|
|
wbs_dat_i = 32'h00040004; // (110 << 16) | 110
|
353 |
|
|
wbs_adr_i = GFX_DEST_PIXEL0;
|
354 |
|
|
#4 wbs_cyc_i = 0;
|
355 |
|
|
|
356 |
|
|
#2 wbs_cyc_i = 1;
|
357 |
|
|
wbs_dat_i = 32'h00060000; // (115 << 16) | 115
|
358 |
|
|
wbs_adr_i = GFX_DEST_PIXEL1;
|
359 |
|
|
#4 wbs_cyc_i = 0;
|
360 |
|
|
|
361 |
|
|
#2 wbs_cyc_i = 1;
|
362 |
|
|
wbs_dat_i = GFX_CTRL_LINE | GFX_CTRL_CD16;
|
363 |
|
|
wbs_adr_i = GFX_CTRL;
|
364 |
|
|
#4 wbs_cyc_i = 0;
|
365 |
|
|
//#########################
|
366 |
|
|
|
367 |
|
|
//draw line ############### 8
|
368 |
|
|
#10 wbs_cyc_i = 1;
|
369 |
|
|
wbs_dat_i = 32'h00040004; // (110 << 16) | 110
|
370 |
|
|
wbs_adr_i = GFX_DEST_PIXEL0;
|
371 |
|
|
#4 wbs_cyc_i = 0;
|
372 |
|
|
|
373 |
|
|
#2 wbs_cyc_i = 1;
|
374 |
|
|
wbs_dat_i = 32'h00080002; // (115 << 16) | 115
|
375 |
|
|
wbs_adr_i = GFX_DEST_PIXEL1;
|
376 |
|
|
#4 wbs_cyc_i = 0;
|
377 |
|
|
|
378 |
|
|
#2 wbs_cyc_i = 1;
|
379 |
|
|
wbs_dat_i = GFX_CTRL_LINE | GFX_CTRL_CD16;
|
380 |
|
|
wbs_adr_i = GFX_CTRL;
|
381 |
|
|
#4 wbs_cyc_i = 0;
|
382 |
|
|
//#########################
|
383 |
|
|
|
384 |
|
|
#10000 $finish;
|
385 |
|
|
end
|
386 |
|
|
|
387 |
|
|
// Set up ack behaviour from memory circuits
|
388 |
|
|
always @(posedge wb_clk_i)
|
389 |
|
|
begin
|
390 |
|
|
wbm_write_ack_i <= #1 wbm_write_cyc_o & !wbm_write_ack_i;
|
391 |
|
|
wbm_read_ack_i <= #1 wbm_read_cyc_o & !wbm_read_ack_i;
|
392 |
|
|
end
|
393 |
|
|
|
394 |
|
|
// Set up clock
|
395 |
|
|
always begin
|
396 |
|
|
#1 wb_clk_i = ~wb_clk_i;
|
397 |
|
|
end
|
398 |
|
|
|
399 |
|
|
// Instansiate module
|
400 |
|
|
gfx_top top(
|
401 |
|
|
.wb_clk_i (wb_clk_i),
|
402 |
|
|
.wb_rst_i (wb_rst_i),
|
403 |
|
|
.wb_inta_o (wb_inta_o),
|
404 |
|
|
// Wishbone master signals (interfaces with video memory)
|
405 |
|
|
.wbm_write_cyc_o (wbm_write_cyc_o),
|
406 |
|
|
.wbm_write_stb_o (wbm_write_stb_o),
|
407 |
|
|
.wbm_write_cti_o (wbm_write_cti_o),
|
408 |
|
|
.wbm_write_bte_o (wbm_write_bte_o),
|
409 |
|
|
.wbm_write_we_o (wbm_write_we_o),
|
410 |
|
|
.wbm_write_adr_o (wbm_write_adr_o),
|
411 |
|
|
.wbm_write_sel_o (wbm_write_sel_o),
|
412 |
|
|
.wbm_write_ack_i (wbm_write_ack_i),
|
413 |
|
|
.wbm_write_err_i (wbm_write_err_i),
|
414 |
|
|
.wbm_write_dat_o (wbm_write_dat_o),
|
415 |
|
|
// Wishbone master signals (interfaces with video memory)
|
416 |
|
|
.wbm_read_cyc_o (wbm_read_cyc_o),
|
417 |
|
|
.wbm_read_stb_o (wbm_read_stb_o),
|
418 |
|
|
.wbm_read_cti_o (wbm_read_cti_o),
|
419 |
|
|
.wbm_read_bte_o (wbm_read_bte_o),
|
420 |
|
|
.wbm_read_we_o (wbm_read_we_o),
|
421 |
|
|
.wbm_read_adr_o (wbm_read_adr_o),
|
422 |
|
|
.wbm_read_sel_o (wbm_read_sel_o),
|
423 |
|
|
.wbm_read_ack_i (wbm_read_ack_i),
|
424 |
|
|
.wbm_read_err_i (wbm_read_err_i),
|
425 |
|
|
.wbm_read_dat_i (wbm_read_dat_i),
|
426 |
|
|
// Wishbone slave signals (interfaces with main bus/CPU)
|
427 |
|
|
.wbs_cyc_i (wbs_cyc_i),
|
428 |
|
|
.wbs_stb_i (wbs_stb_i),
|
429 |
|
|
.wbs_cti_i (wbs_cti_i),
|
430 |
|
|
.wbs_bte_i (wbs_bte_i),
|
431 |
|
|
.wbs_we_i (wbs_we_i),
|
432 |
|
|
.wbs_adr_i (wbs_adr_i),
|
433 |
|
|
.wbs_sel_i (wbs_sel_i),
|
434 |
|
|
.wbs_ack_o (wbs_ack_o),
|
435 |
|
|
.wbs_err_o (wbs_err_o),
|
436 |
|
|
.wbs_dat_i (wbs_dat_i),
|
437 |
|
|
.wbs_dat_o (wbs_dat_o)
|
438 |
|
|
);
|
439 |
|
|
|
440 |
|
|
endmodule
|