URL https://opencores.org/ocsvn/orsoc_graphics_accelerator/orsoc_graphics_accelerator/trunk

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[/] [orsoc_graphics_accelerator/] [tags/] [version1.0/] [bench/] [verilog/] [gfx/] [gfx_bench.v] - Blame information for rev 5

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`include "../../../rtl/verilog/gfx/gfx_wbs.v"
`include "../../../rtl/verilog/gfx/gfx_wbm_write.v"
`include "../../../rtl/verilog/gfx/gfx_wbm_read.v"
`include "../../../rtl/verilog/gfx/gfx_vector_processor.v"
`include "../../../rtl/verilog/gfx/gfx_rasterizer.v"
`include "../../../rtl/verilog/gfx/gfx_fragment_processor.v"
`include "../../../rtl/verilog/gfx/gfx_blender.v"
`include "../../../rtl/verilog/gfx/gfx_renderer.v"
`include "../../../rtl/verilog/gfx/gfx_top.v"
`include "../../../rtl/verilog/gfx/basic_fifo.v"
`include "../../../rtl/verilog/gfx/gfx_color.v"
`include "../../../rtl/verilog/gfx/gfx_wbm_read_arbiter.v"
`include "../../../rtl/verilog/gfx/gfx_line.v"
 
module gfx_bench();
 
// Common wishbone signals
reg         wb_clk_i;    // master clock reg
reg         wb_rst_i;    // Asynchronous active high reset
wire        wb_inta_o;   // interrupt
 
// Wishbone master signals (write)
wire        wbm_write_cyc_o;    // cycle wire
wire        wbm_write_stb_o;    // strobe wire
wire [ 2:0] wbm_write_cti_o;    // cycle type id
wire [ 1:0] wbm_write_bte_o;    // burst type extension
wire        wbm_write_we_o;     // write enable wire
wire [31:0] wbm_write_adr_o;    // address wire
wire [ 3:0] wbm_write_sel_o;    // byte select wires (only 32bits accesses are supported)
reg         wbm_write_ack_i;    // wishbone cycle acknowledge
reg         wbm_write_err_i;    // wishbone cycle error
wire [31:0] wbm_write_dat_o;    // wishbone data out
 
// Wishbone master signals (read)
wire        wbm_read_cyc_o;    // cycle wire
wire        wbm_read_stb_o;    // strobe wire
wire [ 2:0] wbm_read_cti_o;    // cycle type id
wire [ 1:0] wbm_read_bte_o;    // burst type extension
wire        wbm_read_we_o;     // write enable wire
wire [31:0] wbm_read_adr_o;    // address wire
wire [ 3:0] wbm_read_sel_o;    // byte select wires (only 32bits accesses are supported)
reg         wbm_read_ack_i;    // wishbone cycle acknowledge
reg         wbm_read_err_i;    // wishbone cycle error
reg [31:0]  wbm_read_dat_i;    // wishbone data in
 
// Wishbone slave signals
reg         wbs_cyc_i;    // cycle reg
reg         wbs_stb_i;    // strobe reg
reg [ 2:0]  wbs_cti_i;    // cycle type id
reg [ 1:0]  wbs_bte_i;    // burst type extension
reg         wbs_we_i;     // write enable reg
reg [31:0]  wbs_adr_i;    // address reg
reg [ 3:0]  wbs_sel_i;    // byte select reg (only 32bits accesses are supported)
wire        wbs_ack_o;    // wishbone cycle acknowledge
wire        wbs_err_o;    // wishbone cycle error
reg  [31:0] wbs_dat_i;    // wishbone data in
wire [31:0] wbs_dat_o;    // wishbone data out
 
parameter GFX_VMEM        = 32'h00800000;
 
parameter GFX_CTRL        = 32'h000;
parameter GFX_STATUS      = 32'h004;
parameter GFX_SRC_PIXEL0  = 32'h008;
parameter GFX_SRC_PIXEL1  = 32'h00c;
parameter GFX_DEST_PIXEL0 = 32'h010;
parameter GFX_DEST_PIXEL1 = 32'h014;
parameter GFX_CLIP_PIXEL0 = 32'h018;
parameter GFX_CLIP_PIXEL1 = 32'h01c;
parameter GFX_COLOR       = 32'h020;
parameter GFX_TARGET_BASE = 32'h024;
parameter GFX_TARGET_SIZE = 32'h028;
parameter GFX_TEX0_BASE   = 32'h02c;
parameter GFX_TEX0_SIZE   = 32'h030;
parameter GFX_ALPHA       = 32'h034;
parameter GFX_COLORKEY    = 32'h038;
 
parameter GFX_CTRL_CD8        = 32'h00000000; /* Color Depth 8 */
parameter GFX_CTRL_CD16       = 32'h00000001; /* Color Depth 16 */
parameter GFX_CTRL_CD24       = 32'h00000002; /* Color Depth 24 */ // Not supported!
parameter GFX_CTRL_CD32       = 32'h00000003; /* Color Depth 32 */
parameter GFX_CTRL_CDMASK     = 32'h00000003; /* All color depth bits */
parameter GFX_TEXTURE_ENABLE  = 32'h00000004; /* Enable Texture Reads */
parameter GFX_BLEND_ENABLE    = 32'h00000008; /* Enable Alpha Blending */
parameter GFX_COLORKEY_ENABLE = 32'h00000010; /* Enable Colorkeying */
 
parameter GFX_CTRL_RECT       = 32'h00000100; /* Put rect  */
parameter GFX_CTRL_LINE       = 32'h00000200; /* Put line  */
 
 
initial begin
  $dumpfile("gfx.vcd");
  $dumpvars(0,gfx_bench);
 
// init values
  wb_clk_i = 0;
  wb_rst_i = 1;
  wbm_write_ack_i = 0;
  wbm_read_ack_i = 0;
  wbm_write_err_i = 0;
  wbm_read_err_i = 0;
  wbs_cyc_i = 0;
  wbs_cti_i = 0;
  wbs_bte_i = 0;
  wbs_adr_i = 0;
  wbs_sel_i = 4'b1111;
  wbs_dat_i = 0;
 
  // Can be high all the time
  wbs_we_i   = 1;
  wbs_stb_i  = 1;
 
//  wbm_read_dat_i = 32'hf18ff18f;
 
  // Set the texture read pixel
  wbm_read_dat_i = 32'h00000000;
 
  // Finish the reset of the component
  #2 wb_rst_i = 0;
 
 
  // Initialize color register
  #2 wbs_cyc_i  = 1;
  wbs_adr_i = GFX_COLOR;
  wbs_dat_i = 32'h12345671;
  #4 wbs_cyc_i  = 0;
 
  // Initialize traget base
  #2 wbs_cyc_i  = 1;
  wbs_dat_i  = GFX_VMEM;
  wbs_adr_i  = GFX_TARGET_BASE;
  #4 wbs_cyc_i = 0;
 
  // oc_gfx_set_videomode(640, 480, 16);
  #2 wbs_cyc_i = 1;
  wbs_dat_i  = 32'h028001e0; // (640 << 16) | 480
  wbs_adr_i  = GFX_TEX0_SIZE;
  #4 wbs_cyc_i = 0;
 
  // Set 16 bit color depth
  #2 wbs_cyc_i = 1;
  wbs_dat_i  = GFX_CTRL_CD16;
  wbs_adr_i  = GFX_CTRL;
  #4 wbs_cyc_i = 0;
 
// Enable colorkey
  #2 wbs_cyc_i = 1;
  wbs_dat_i  = 32'h0000F18F; // pink color
  wbs_adr_i  = GFX_COLORKEY;
  #4 wbs_cyc_i = 0;
 
  #2 wbs_cyc_i = 1;
  wbs_dat_i  = GFX_COLORKEY_ENABLE | GFX_CTRL_CD16;
  wbs_adr_i  = GFX_CTRL;
  #4 wbs_cyc_i = 0;
 
  // set cliparea
  #2 wbs_cyc_i = 1;
  wbs_dat_i  = 32'h00000000; // (0 << 16) | 0
  wbs_adr_i  = GFX_CLIP_PIXEL0; // Clip Pixel 0
  #4 wbs_cyc_i = 0;
 
  #2 wbs_cyc_i = 1;
  wbs_dat_i  = 32'h028001e0; // (640 << 16) | 480
  wbs_adr_i  = GFX_CLIP_PIXEL1; // Clip Pixel 1
  #4 wbs_cyc_i = 0;
 
// oc_gfx_enable_tex0(1)
  #2 wbs_cyc_i = 1;
  wbs_dat_i  = GFX_TEXTURE_ENABLE | GFX_COLORKEY_ENABLE | GFX_CTRL_CD16;
  wbs_adr_i  = GFX_CTRL;
  #4 wbs_cyc_i = 0;
 
// oc_gfx_bind_tex0(0x01f00000, 10, 10)
  #2 wbs_cyc_i = 1;
  wbs_dat_i  = GFX_VMEM;
  wbs_adr_i  = GFX_TEX0_BASE;
  #4 wbs_cyc_i = 0;
 
  #2 wbs_cyc_i = 1;
  wbs_dat_i  = 32'h000a000a; // (10 << 16) | 10
  wbs_adr_i  = GFX_TEX0_SIZE;
  #4 wbs_cyc_i = 0;
 
// oc_gfx_rect(110, 110, 115, 115, 0xf800f800);
  #2 wbs_cyc_i = 1;
  wbs_dat_i  = 32'h006e006e; // (110 << 16) | 110
  wbs_adr_i  = GFX_DEST_PIXEL0;
  #4 wbs_cyc_i = 0;
 
  #2 wbs_cyc_i = 1;
  wbs_dat_i  = 32'h00780073; // (115 << 16) | 115
  wbs_adr_i  = GFX_DEST_PIXEL1;
  #4 wbs_cyc_i = 0;
 
  #2 wbs_cyc_i = 1;
  wbs_dat_i  = 32'hf800f800; // Red
  wbs_adr_i  = GFX_COLOR;
  #4 wbs_cyc_i = 0;
 
  #2 wbs_cyc_i = 1;
  wbs_dat_i  = GFX_CTRL_RECT | GFX_TEXTURE_ENABLE | GFX_COLORKEY_ENABLE | GFX_CTRL_CD16;
  wbs_adr_i  = GFX_CTRL;
  #4 wbs_cyc_i = 0;
 
  // After a while, set every pixel read to the color key (demonstrates that colorkeyed pixels are not written)
  #200 wbm_read_dat_i = 32'hf18ff18f;
 
  // TODO: Demonstrate alpha blending
 
/*
 
  wbm_read_dat_i = #40 32'hffffffff;
 
 
// oc_gfx_rect(110, 110, 115, 115, 0xf800f800);
  #200 wbs_cyc_i = 1;
  wbs_dat_i  = 32'h006e006e; // (110 << 16) | 110
  wbs_adr_i  = GFX_DEST_PIXEL0;
  #4 wbs_cyc_i = 0;
 
  #2 wbs_cyc_i = 1;
  wbs_dat_i  = 32'h00730073; // (115 << 16) | 115
  wbs_adr_i  = GFX_DEST_PIXEL1;
  #4 wbs_cyc_i = 0;
 
 
// set cliparea
  #2 wbs_cyc_i = 1;
  wbs_dat_i  = 32'h00700070; // (112 << 16) | 112
  wbs_adr_i  = GFX_CLIP_PIXEL0;
  #4 wbs_cyc_i = 0;
 
  #2 wbs_cyc_i = 1;
  wbs_dat_i  = 32'h00720072; // (114 << 16) | 114
  wbs_adr_i  = GFX_CLIP_PIXEL1;
  #4 wbs_cyc_i = 0;
 
 
  #2 wbs_cyc_i = 1;
  wbs_dat_i  = GFX_CTRL_RECT | GFX_TEXTURE_ENABLE | GFX_CTRL_CD16;
  wbs_adr_i  = GFX_CTRL;
  #4 wbs_cyc_i = 0;
 
*/
 
  // Draw a bunch of lines
 
  //draw line ############### 1
  #2 wbs_cyc_i = 1;
  wbs_dat_i  = 32'h00040004; // (110 << 16) | 110
  wbs_adr_i  = GFX_DEST_PIXEL0;
  #4 wbs_cyc_i = 0;
 
  #2 wbs_cyc_i = 1;
  wbs_dat_i  = 32'h00080006; // (115 << 16) | 115
  wbs_adr_i  = GFX_DEST_PIXEL1;
  #4 wbs_cyc_i = 0;
 
  #2 wbs_cyc_i = 1;
  wbs_dat_i  = GFX_CTRL_LINE | GFX_CTRL_CD16;
  wbs_adr_i  = GFX_CTRL;
  #4 wbs_cyc_i = 0;
  //#########################
 
  //draw line ############### 2
  #10 wbs_cyc_i = 1;
  wbs_dat_i  = 32'h00040004; // (110 << 16) | 110
  wbs_adr_i  = GFX_DEST_PIXEL0;
  #4 wbs_cyc_i = 0;
 
  #2 wbs_cyc_i = 1;
  wbs_dat_i  = 32'h00060008; // (115 << 16) | 115
  wbs_adr_i  = GFX_DEST_PIXEL1;
  #4 wbs_cyc_i = 0;
 
  #2 wbs_cyc_i = 1;
  wbs_dat_i  = GFX_CTRL_LINE | GFX_CTRL_CD16;
  wbs_adr_i  = GFX_CTRL;
  #4 wbs_cyc_i = 0;
  //#########################
 
  //draw line ############### 3
  #10 wbs_cyc_i = 1;
  wbs_dat_i  = 32'h00040004; // (110 << 16) | 110
  wbs_adr_i  = GFX_DEST_PIXEL0;
  #4 wbs_cyc_i = 0;
 
  #2 wbs_cyc_i = 1;
  wbs_dat_i  = 32'h00020008; // (115 << 16) | 115
  wbs_adr_i  = GFX_DEST_PIXEL1;
  #4 wbs_cyc_i = 0;
 
  #2 wbs_cyc_i = 1;
  wbs_dat_i  = GFX_CTRL_LINE | GFX_CTRL_CD16;
  wbs_adr_i  = GFX_CTRL;
  #4 wbs_cyc_i = 0;
  //#########################
 
  //draw line ############### 4
  #10 wbs_cyc_i = 1;
  wbs_dat_i  = 32'h00040004; // (110 << 16) | 110
  wbs_adr_i  = GFX_DEST_PIXEL0;
  #4 wbs_cyc_i = 0;
 
  #2 wbs_cyc_i = 1;
  wbs_dat_i  = 32'h00000006; // (115 << 16) | 115
  wbs_adr_i  = GFX_DEST_PIXEL1;
  #4 wbs_cyc_i = 0;
 
  #2 wbs_cyc_i = 1;
  wbs_dat_i  = GFX_CTRL_LINE | GFX_CTRL_CD16;
  wbs_adr_i  = GFX_CTRL;
  #4 wbs_cyc_i = 0;
  //#########################
 
  //draw line ############### 5
  #10 wbs_cyc_i = 1;
  wbs_dat_i  = 32'h00040004; // (110 << 16) | 110
  wbs_adr_i  = GFX_DEST_PIXEL0;
  #4 wbs_cyc_i = 0;
 
  #2 wbs_cyc_i = 1;
  wbs_dat_i  = 32'h00000002; // (115 << 16) | 115
  wbs_adr_i  = GFX_DEST_PIXEL1;
  #4 wbs_cyc_i = 0;
 
  #2 wbs_cyc_i = 1;
  wbs_dat_i  = GFX_CTRL_LINE | GFX_CTRL_CD16;
  wbs_adr_i  = GFX_CTRL;
  #4 wbs_cyc_i = 0;
  //#########################
 
  //draw line ############### 6
  #10 wbs_cyc_i = 1;
  wbs_dat_i  = 32'h00040004; // (110 << 16) | 110
  wbs_adr_i  = GFX_DEST_PIXEL0;
  #4 wbs_cyc_i = 0;
 
  #2 wbs_cyc_i = 1;
  wbs_dat_i  = 32'h00020000; // (115 << 16) | 115
  wbs_adr_i  = GFX_DEST_PIXEL1;
  #4 wbs_cyc_i = 0;
 
  #2 wbs_cyc_i = 1;
  wbs_dat_i  = GFX_CTRL_LINE | GFX_CTRL_CD16;
  wbs_adr_i  = GFX_CTRL;
  #4 wbs_cyc_i = 0;
  //#########################
 
  //draw line ############### 7
  #10 wbs_cyc_i = 1;
  wbs_dat_i  = 32'h00040004; // (110 << 16) | 110
  wbs_adr_i  = GFX_DEST_PIXEL0;
  #4 wbs_cyc_i = 0;
 
  #2 wbs_cyc_i = 1;
  wbs_dat_i  = 32'h00060000; // (115 << 16) | 115
  wbs_adr_i  = GFX_DEST_PIXEL1;
  #4 wbs_cyc_i = 0;
 
  #2 wbs_cyc_i = 1;
  wbs_dat_i  = GFX_CTRL_LINE | GFX_CTRL_CD16;
  wbs_adr_i  = GFX_CTRL;
  #4 wbs_cyc_i = 0;
  //#########################
 
  //draw line ############### 8
  #10 wbs_cyc_i = 1;
  wbs_dat_i  = 32'h00040004; // (110 << 16) | 110
  wbs_adr_i  = GFX_DEST_PIXEL0;
  #4 wbs_cyc_i = 0;
 
  #2 wbs_cyc_i = 1;
  wbs_dat_i  = 32'h00080002; // (115 << 16) | 115
  wbs_adr_i  = GFX_DEST_PIXEL1;
  #4 wbs_cyc_i = 0;
 
  #2 wbs_cyc_i = 1;
  wbs_dat_i  = GFX_CTRL_LINE | GFX_CTRL_CD16;
  wbs_adr_i  = GFX_CTRL;
  #4 wbs_cyc_i = 0;
  //#########################
 
  #10000 $finish;
end
 
// Set up ack behaviour from memory circuits
always @(posedge wb_clk_i)
begin
  wbm_write_ack_i <= #1 wbm_write_cyc_o & !wbm_write_ack_i;
  wbm_read_ack_i  <= #1 wbm_read_cyc_o  & !wbm_read_ack_i;
end
 
// Set up clock
always begin
  #1 wb_clk_i = ~wb_clk_i;
end
 
// Instansiate module
gfx_top top(
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_inta_o (wb_inta_o),
// Wishbone master signals (interfaces with video memory)
.wbm_write_cyc_o (wbm_write_cyc_o),
.wbm_write_stb_o (wbm_write_stb_o),
.wbm_write_cti_o (wbm_write_cti_o),
.wbm_write_bte_o (wbm_write_bte_o),
.wbm_write_we_o (wbm_write_we_o),
.wbm_write_adr_o (wbm_write_adr_o),
.wbm_write_sel_o (wbm_write_sel_o),
.wbm_write_ack_i (wbm_write_ack_i),
.wbm_write_err_i (wbm_write_err_i),
.wbm_write_dat_o (wbm_write_dat_o),
// Wishbone master signals (interfaces with video memory)
.wbm_read_cyc_o (wbm_read_cyc_o),
.wbm_read_stb_o (wbm_read_stb_o),
.wbm_read_cti_o (wbm_read_cti_o),
.wbm_read_bte_o (wbm_read_bte_o),
.wbm_read_we_o (wbm_read_we_o),
.wbm_read_adr_o (wbm_read_adr_o),
.wbm_read_sel_o (wbm_read_sel_o),
.wbm_read_ack_i (wbm_read_ack_i),
.wbm_read_err_i (wbm_read_err_i),
.wbm_read_dat_i (wbm_read_dat_i),
// Wishbone slave signals (interfaces with main bus/CPU)
.wbs_cyc_i (wbs_cyc_i),
.wbs_stb_i (wbs_stb_i),
.wbs_cti_i (wbs_cti_i),
.wbs_bte_i (wbs_bte_i),
.wbs_we_i (wbs_we_i),
.wbs_adr_i (wbs_adr_i),
.wbs_sel_i (wbs_sel_i),
.wbs_ack_o (wbs_ack_o),
.wbs_err_o (wbs_err_o),
.wbs_dat_i (wbs_dat_i),
.wbs_dat_o (wbs_dat_o)
);
 
endmodule

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Subversion Repositories orsoc_graphics_accelerator

[/] [orsoc_graphics_accelerator/] [tags/] [version1.0/] [bench/] [verilog/] [gfx/] [gfx_bench.v] - Blame information for rev 5

Line No.	Rev	Author	Line
1	2	maiden	`include "../../../rtl/verilog/gfx/gfx_wbs.v"
2			`include "../../../rtl/verilog/gfx/gfx_wbm_write.v"
3			`include "../../../rtl/verilog/gfx/gfx_wbm_read.v"
4			`include "../../../rtl/verilog/gfx/gfx_vector_processor.v"
5			`include "../../../rtl/verilog/gfx/gfx_rasterizer.v"
6			`include "../../../rtl/verilog/gfx/gfx_fragment_processor.v"
7			`include "../../../rtl/verilog/gfx/gfx_blender.v"
8			`include "../../../rtl/verilog/gfx/gfx_renderer.v"
9			`include "../../../rtl/verilog/gfx/gfx_top.v"
10			`include "../../../rtl/verilog/gfx/basic_fifo.v"
11			`include "../../../rtl/verilog/gfx/gfx_color.v"
12			`include "../../../rtl/verilog/gfx/gfx_wbm_read_arbiter.v"
13			`include "../../../rtl/verilog/gfx/gfx_line.v"
14
15			`module gfx_bench();`
16
17			`// Common wishbone signals`
18			`reg wb_clk_i; // master clock reg`
19			`reg wb_rst_i; // Asynchronous active high reset`
20			`wire wb_inta_o; // interrupt`
21
22			`// Wishbone master signals (write)`
23			`wire wbm_write_cyc_o; // cycle wire`
24			`wire wbm_write_stb_o; // strobe wire`
25			`wire [ 2:0] wbm_write_cti_o; // cycle type id`
26			`wire [ 1:0] wbm_write_bte_o; // burst type extension`
27			`wire wbm_write_we_o; // write enable wire`
28			`wire [31:0] wbm_write_adr_o; // address wire`
29			`wire [ 3:0] wbm_write_sel_o; // byte select wires (only 32bits accesses are supported)`
30			`reg wbm_write_ack_i; // wishbone cycle acknowledge`
31			`reg wbm_write_err_i; // wishbone cycle error`
32			`wire [31:0] wbm_write_dat_o; // wishbone data out`
33
34			`// Wishbone master signals (read)`
35			`wire wbm_read_cyc_o; // cycle wire`
36			`wire wbm_read_stb_o; // strobe wire`
37			`wire [ 2:0] wbm_read_cti_o; // cycle type id`
38			`wire [ 1:0] wbm_read_bte_o; // burst type extension`
39			`wire wbm_read_we_o; // write enable wire`
40			`wire [31:0] wbm_read_adr_o; // address wire`
41			`wire [ 3:0] wbm_read_sel_o; // byte select wires (only 32bits accesses are supported)`
42			`reg wbm_read_ack_i; // wishbone cycle acknowledge`
43			`reg wbm_read_err_i; // wishbone cycle error`
44			`reg [31:0] wbm_read_dat_i; // wishbone data in`
45
46			`// Wishbone slave signals`
47			`reg wbs_cyc_i; // cycle reg`
48			`reg wbs_stb_i; // strobe reg`
49			`reg [ 2:0] wbs_cti_i; // cycle type id`
50			`reg [ 1:0] wbs_bte_i; // burst type extension`
51			`reg wbs_we_i; // write enable reg`
52			`reg [31:0] wbs_adr_i; // address reg`
53			`reg [ 3:0] wbs_sel_i; // byte select reg (only 32bits accesses are supported)`
54			`wire wbs_ack_o; // wishbone cycle acknowledge`
55			`wire wbs_err_o; // wishbone cycle error`
56			`reg [31:0] wbs_dat_i; // wishbone data in`
57			`wire [31:0] wbs_dat_o; // wishbone data out`
58
59			`parameter GFX_VMEM = 32'h00800000;`
60
61			`parameter GFX_CTRL = 32'h000;`
62			`parameter GFX_STATUS = 32'h004;`
63			`parameter GFX_SRC_PIXEL0 = 32'h008;`
64			`parameter GFX_SRC_PIXEL1 = 32'h00c;`
65			`parameter GFX_DEST_PIXEL0 = 32'h010;`
66			`parameter GFX_DEST_PIXEL1 = 32'h014;`
67			`parameter GFX_CLIP_PIXEL0 = 32'h018;`
68			`parameter GFX_CLIP_PIXEL1 = 32'h01c;`
69			`parameter GFX_COLOR = 32'h020;`
70			`parameter GFX_TARGET_BASE = 32'h024;`
71			`parameter GFX_TARGET_SIZE = 32'h028;`
72			`parameter GFX_TEX0_BASE = 32'h02c;`
73			`parameter GFX_TEX0_SIZE = 32'h030;`
74			`parameter GFX_ALPHA = 32'h034;`
75			`parameter GFX_COLORKEY = 32'h038;`
76
77			`parameter GFX_CTRL_CD8 = 32'h00000000; /* Color Depth 8 */`
78			`parameter GFX_CTRL_CD16 = 32'h00000001; /* Color Depth 16 */`
79			`parameter GFX_CTRL_CD24 = 32'h00000002; /* Color Depth 24 */ // Not supported!`
80			`parameter GFX_CTRL_CD32 = 32'h00000003; /* Color Depth 32 */`
81			`parameter GFX_CTRL_CDMASK = 32'h00000003; /* All color depth bits */`
82			`parameter GFX_TEXTURE_ENABLE = 32'h00000004; /* Enable Texture Reads */`
83			`parameter GFX_BLEND_ENABLE = 32'h00000008; /* Enable Alpha Blending */`
84			`parameter GFX_COLORKEY_ENABLE = 32'h00000010; /* Enable Colorkeying */`
85
86			`parameter GFX_CTRL_RECT = 32'h00000100; /* Put rect */`
87			`parameter GFX_CTRL_LINE = 32'h00000200; /* Put line */`
88
89
90			`initial begin`
91			`$dumpfile("gfx.vcd");`
92			`$dumpvars(0,gfx_bench);`
93
94			`// init values`
95			`wb_clk_i = 0;`
96			`wb_rst_i = 1;`
97			`wbm_write_ack_i = 0;`
98			`wbm_read_ack_i = 0;`
99			`wbm_write_err_i = 0;`
100			`wbm_read_err_i = 0;`
101			`wbs_cyc_i = 0;`
102			`wbs_cti_i = 0;`
103			`wbs_bte_i = 0;`
104			`wbs_adr_i = 0;`
105			`wbs_sel_i = 4'b1111;`
106			`wbs_dat_i = 0;`
107
108			`// Can be high all the time`
109			`wbs_we_i = 1;`
110			`wbs_stb_i = 1;`
111
112			`// wbm_read_dat_i = 32'hf18ff18f;`
113
114			`// Set the texture read pixel`
115			`wbm_read_dat_i = 32'h00000000;`
116
117			`// Finish the reset of the component`
118			`#2 wb_rst_i = 0;`
119
120
121			`// Initialize color register`
122			`#2 wbs_cyc_i = 1;`
123			`wbs_adr_i = GFX_COLOR;`
124			`wbs_dat_i = 32'h12345671;`
125			`#4 wbs_cyc_i = 0;`
126
127			`// Initialize traget base`
128			`#2 wbs_cyc_i = 1;`
129			`wbs_dat_i = GFX_VMEM;`
130			`wbs_adr_i = GFX_TARGET_BASE;`
131			`#4 wbs_cyc_i = 0;`
132
133			`// oc_gfx_set_videomode(640, 480, 16);`
134			`#2 wbs_cyc_i = 1;`
135			`wbs_dat_i = 32'h028001e0; // (640 << 16) \| 480`
136			`wbs_adr_i = GFX_TEX0_SIZE;`
137			`#4 wbs_cyc_i = 0;`
138
139			`// Set 16 bit color depth`
140			`#2 wbs_cyc_i = 1;`
141			`wbs_dat_i = GFX_CTRL_CD16;`
142			`wbs_adr_i = GFX_CTRL;`
143			`#4 wbs_cyc_i = 0;`
144
145			`// Enable colorkey`
146			`#2 wbs_cyc_i = 1;`
147			`wbs_dat_i = 32'h0000F18F; // pink color`
148			`wbs_adr_i = GFX_COLORKEY;`
149			`#4 wbs_cyc_i = 0;`
150
151			`#2 wbs_cyc_i = 1;`
152			`wbs_dat_i = GFX_COLORKEY_ENABLE \| GFX_CTRL_CD16;`
153			`wbs_adr_i = GFX_CTRL;`
154			`#4 wbs_cyc_i = 0;`
155
156			`// set cliparea`
157			`#2 wbs_cyc_i = 1;`
158			`wbs_dat_i = 32'h00000000; // (0 << 16) \| 0`
159			`wbs_adr_i = GFX_CLIP_PIXEL0; // Clip Pixel 0`
160			`#4 wbs_cyc_i = 0;`
161
162			`#2 wbs_cyc_i = 1;`
163			`wbs_dat_i = 32'h028001e0; // (640 << 16) \| 480`
164			`wbs_adr_i = GFX_CLIP_PIXEL1; // Clip Pixel 1`
165			`#4 wbs_cyc_i = 0;`
166
167			`// oc_gfx_enable_tex0(1)`
168			`#2 wbs_cyc_i = 1;`
169			`wbs_dat_i = GFX_TEXTURE_ENABLE \| GFX_COLORKEY_ENABLE \| GFX_CTRL_CD16;`
170			`wbs_adr_i = GFX_CTRL;`
171			`#4 wbs_cyc_i = 0;`
172
173			`// oc_gfx_bind_tex0(0x01f00000, 10, 10)`
174			`#2 wbs_cyc_i = 1;`
175			`wbs_dat_i = GFX_VMEM;`
176			`wbs_adr_i = GFX_TEX0_BASE;`
177			`#4 wbs_cyc_i = 0;`
178
179			`#2 wbs_cyc_i = 1;`
180			`wbs_dat_i = 32'h000a000a; // (10 << 16) \| 10`
181			`wbs_adr_i = GFX_TEX0_SIZE;`
182			`#4 wbs_cyc_i = 0;`
183
184			`// oc_gfx_rect(110, 110, 115, 115, 0xf800f800);`
185			`#2 wbs_cyc_i = 1;`
186			`wbs_dat_i = 32'h006e006e; // (110 << 16) \| 110`
187			`wbs_adr_i = GFX_DEST_PIXEL0;`
188			`#4 wbs_cyc_i = 0;`
189
190			`#2 wbs_cyc_i = 1;`
191			`wbs_dat_i = 32'h00780073; // (115 << 16) \| 115`
192			`wbs_adr_i = GFX_DEST_PIXEL1;`
193			`#4 wbs_cyc_i = 0;`
194
195			`#2 wbs_cyc_i = 1;`
196			`wbs_dat_i = 32'hf800f800; // Red`
197			`wbs_adr_i = GFX_COLOR;`
198			`#4 wbs_cyc_i = 0;`
199
200			`#2 wbs_cyc_i = 1;`
201			`wbs_dat_i = GFX_CTRL_RECT \| GFX_TEXTURE_ENABLE \| GFX_COLORKEY_ENABLE \| GFX_CTRL_CD16;`
202			`wbs_adr_i = GFX_CTRL;`
203			`#4 wbs_cyc_i = 0;`
204
205			`// After a while, set every pixel read to the color key (demonstrates that colorkeyed pixels are not written)`
206			`#200 wbm_read_dat_i = 32'hf18ff18f;`
207
208			`// TODO: Demonstrate alpha blending`
209
210			`/*`
211
212			`wbm_read_dat_i = #40 32'hffffffff;`
213
214
215			`// oc_gfx_rect(110, 110, 115, 115, 0xf800f800);`
216			`#200 wbs_cyc_i = 1;`
217			`wbs_dat_i = 32'h006e006e; // (110 << 16) \| 110`
218			`wbs_adr_i = GFX_DEST_PIXEL0;`
219			`#4 wbs_cyc_i = 0;`
220
221			`#2 wbs_cyc_i = 1;`
222			`wbs_dat_i = 32'h00730073; // (115 << 16) \| 115`
223			`wbs_adr_i = GFX_DEST_PIXEL1;`
224			`#4 wbs_cyc_i = 0;`
225
226
227			`// set cliparea`
228			`#2 wbs_cyc_i = 1;`
229			`wbs_dat_i = 32'h00700070; // (112 << 16) \| 112`
230			`wbs_adr_i = GFX_CLIP_PIXEL0;`
231			`#4 wbs_cyc_i = 0;`
232
233			`#2 wbs_cyc_i = 1;`
234			`wbs_dat_i = 32'h00720072; // (114 << 16) \| 114`
235			`wbs_adr_i = GFX_CLIP_PIXEL1;`
236			`#4 wbs_cyc_i = 0;`
237
238
239			`#2 wbs_cyc_i = 1;`
240			`wbs_dat_i = GFX_CTRL_RECT \| GFX_TEXTURE_ENABLE \| GFX_CTRL_CD16;`
241			`wbs_adr_i = GFX_CTRL;`
242			`#4 wbs_cyc_i = 0;`
243
244			`*/`
245
246			`// Draw a bunch of lines`
247
248			`//draw line ############### 1`
249			`#2 wbs_cyc_i = 1;`
250			`wbs_dat_i = 32'h00040004; // (110 << 16) \| 110`
251			`wbs_adr_i = GFX_DEST_PIXEL0;`
252			`#4 wbs_cyc_i = 0;`
253
254			`#2 wbs_cyc_i = 1;`
255			`wbs_dat_i = 32'h00080006; // (115 << 16) \| 115`
256			`wbs_adr_i = GFX_DEST_PIXEL1;`
257			`#4 wbs_cyc_i = 0;`
258
259			`#2 wbs_cyc_i = 1;`
260			`wbs_dat_i = GFX_CTRL_LINE \| GFX_CTRL_CD16;`
261			`wbs_adr_i = GFX_CTRL;`
262			`#4 wbs_cyc_i = 0;`
263			`//#########################`
264
265			`//draw line ############### 2`
266			`#10 wbs_cyc_i = 1;`
267			`wbs_dat_i = 32'h00040004; // (110 << 16) \| 110`
268			`wbs_adr_i = GFX_DEST_PIXEL0;`
269			`#4 wbs_cyc_i = 0;`
270
271			`#2 wbs_cyc_i = 1;`
272			`wbs_dat_i = 32'h00060008; // (115 << 16) \| 115`
273			`wbs_adr_i = GFX_DEST_PIXEL1;`
274			`#4 wbs_cyc_i = 0;`
275
276			`#2 wbs_cyc_i = 1;`
277			`wbs_dat_i = GFX_CTRL_LINE \| GFX_CTRL_CD16;`
278			`wbs_adr_i = GFX_CTRL;`
279			`#4 wbs_cyc_i = 0;`
280			`//#########################`
281
282			`//draw line ############### 3`
283			`#10 wbs_cyc_i = 1;`
284			`wbs_dat_i = 32'h00040004; // (110 << 16) \| 110`
285			`wbs_adr_i = GFX_DEST_PIXEL0;`
286			`#4 wbs_cyc_i = 0;`
287
288			`#2 wbs_cyc_i = 1;`
289			`wbs_dat_i = 32'h00020008; // (115 << 16) \| 115`
290			`wbs_adr_i = GFX_DEST_PIXEL1;`
291			`#4 wbs_cyc_i = 0;`
292
293			`#2 wbs_cyc_i = 1;`
294			`wbs_dat_i = GFX_CTRL_LINE \| GFX_CTRL_CD16;`
295			`wbs_adr_i = GFX_CTRL;`
296			`#4 wbs_cyc_i = 0;`
297			`//#########################`
298
299			`//draw line ############### 4`
300			`#10 wbs_cyc_i = 1;`
301			`wbs_dat_i = 32'h00040004; // (110 << 16) \| 110`
302			`wbs_adr_i = GFX_DEST_PIXEL0;`
303			`#4 wbs_cyc_i = 0;`
304
305			`#2 wbs_cyc_i = 1;`
306			`wbs_dat_i = 32'h00000006; // (115 << 16) \| 115`
307			`wbs_adr_i = GFX_DEST_PIXEL1;`
308			`#4 wbs_cyc_i = 0;`
309
310			`#2 wbs_cyc_i = 1;`
311			`wbs_dat_i = GFX_CTRL_LINE \| GFX_CTRL_CD16;`
312			`wbs_adr_i = GFX_CTRL;`
313			`#4 wbs_cyc_i = 0;`
314			`//#########################`
315
316			`//draw line ############### 5`
317			`#10 wbs_cyc_i = 1;`
318			`wbs_dat_i = 32'h00040004; // (110 << 16) \| 110`
319			`wbs_adr_i = GFX_DEST_PIXEL0;`
320			`#4 wbs_cyc_i = 0;`
321
322			`#2 wbs_cyc_i = 1;`
323			`wbs_dat_i = 32'h00000002; // (115 << 16) \| 115`
324			`wbs_adr_i = GFX_DEST_PIXEL1;`
325			`#4 wbs_cyc_i = 0;`
326
327			`#2 wbs_cyc_i = 1;`
328			`wbs_dat_i = GFX_CTRL_LINE \| GFX_CTRL_CD16;`
329			`wbs_adr_i = GFX_CTRL;`
330			`#4 wbs_cyc_i = 0;`
331			`//#########################`
332
333			`//draw line ############### 6`
334			`#10 wbs_cyc_i = 1;`
335			`wbs_dat_i = 32'h00040004; // (110 << 16) \| 110`
336			`wbs_adr_i = GFX_DEST_PIXEL0;`
337			`#4 wbs_cyc_i = 0;`
338
339			`#2 wbs_cyc_i = 1;`
340			`wbs_dat_i = 32'h00020000; // (115 << 16) \| 115`
341			`wbs_adr_i = GFX_DEST_PIXEL1;`
342			`#4 wbs_cyc_i = 0;`
343
344			`#2 wbs_cyc_i = 1;`
345			`wbs_dat_i = GFX_CTRL_LINE \| GFX_CTRL_CD16;`
346			`wbs_adr_i = GFX_CTRL;`
347			`#4 wbs_cyc_i = 0;`
348			`//#########################`
349
350			`//draw line ############### 7`
351			`#10 wbs_cyc_i = 1;`
352			`wbs_dat_i = 32'h00040004; // (110 << 16) \| 110`
353			`wbs_adr_i = GFX_DEST_PIXEL0;`
354			`#4 wbs_cyc_i = 0;`
355
356			`#2 wbs_cyc_i = 1;`
357			`wbs_dat_i = 32'h00060000; // (115 << 16) \| 115`
358			`wbs_adr_i = GFX_DEST_PIXEL1;`
359			`#4 wbs_cyc_i = 0;`
360
361			`#2 wbs_cyc_i = 1;`
362			`wbs_dat_i = GFX_CTRL_LINE \| GFX_CTRL_CD16;`
363			`wbs_adr_i = GFX_CTRL;`
364			`#4 wbs_cyc_i = 0;`
365			`//#########################`
366
367			`//draw line ############### 8`
368			`#10 wbs_cyc_i = 1;`
369			`wbs_dat_i = 32'h00040004; // (110 << 16) \| 110`
370			`wbs_adr_i = GFX_DEST_PIXEL0;`
371			`#4 wbs_cyc_i = 0;`
372
373			`#2 wbs_cyc_i = 1;`
374			`wbs_dat_i = 32'h00080002; // (115 << 16) \| 115`
375			`wbs_adr_i = GFX_DEST_PIXEL1;`
376			`#4 wbs_cyc_i = 0;`
377
378			`#2 wbs_cyc_i = 1;`
379			`wbs_dat_i = GFX_CTRL_LINE \| GFX_CTRL_CD16;`
380			`wbs_adr_i = GFX_CTRL;`
381			`#4 wbs_cyc_i = 0;`
382			`//#########################`
383
384			`#10000 $finish;`
385			`end`
386
387			`// Set up ack behaviour from memory circuits`
388			`always @(posedge wb_clk_i)`
389			`begin`
390			`wbm_write_ack_i <= #1 wbm_write_cyc_o & !wbm_write_ack_i;`
391			`wbm_read_ack_i <= #1 wbm_read_cyc_o & !wbm_read_ack_i;`
392			`end`
393
394			`// Set up clock`
395			`always begin`
396			`#1 wb_clk_i = ~wb_clk_i;`
397			`end`
398
399			`// Instansiate module`
400			`gfx_top top(`
401			`.wb_clk_i (wb_clk_i),`
402			`.wb_rst_i (wb_rst_i),`
403			`.wb_inta_o (wb_inta_o),`
404			`// Wishbone master signals (interfaces with video memory)`
405			`.wbm_write_cyc_o (wbm_write_cyc_o),`
406			`.wbm_write_stb_o (wbm_write_stb_o),`
407			`.wbm_write_cti_o (wbm_write_cti_o),`
408			`.wbm_write_bte_o (wbm_write_bte_o),`
409			`.wbm_write_we_o (wbm_write_we_o),`
410			`.wbm_write_adr_o (wbm_write_adr_o),`
411			`.wbm_write_sel_o (wbm_write_sel_o),`
412			`.wbm_write_ack_i (wbm_write_ack_i),`
413			`.wbm_write_err_i (wbm_write_err_i),`
414			`.wbm_write_dat_o (wbm_write_dat_o),`
415			`// Wishbone master signals (interfaces with video memory)`
416			`.wbm_read_cyc_o (wbm_read_cyc_o),`
417			`.wbm_read_stb_o (wbm_read_stb_o),`
418			`.wbm_read_cti_o (wbm_read_cti_o),`
419			`.wbm_read_bte_o (wbm_read_bte_o),`
420			`.wbm_read_we_o (wbm_read_we_o),`
421			`.wbm_read_adr_o (wbm_read_adr_o),`
422			`.wbm_read_sel_o (wbm_read_sel_o),`
423			`.wbm_read_ack_i (wbm_read_ack_i),`
424			`.wbm_read_err_i (wbm_read_err_i),`
425			`.wbm_read_dat_i (wbm_read_dat_i),`
426			`// Wishbone slave signals (interfaces with main bus/CPU)`
427			`.wbs_cyc_i (wbs_cyc_i),`
428			`.wbs_stb_i (wbs_stb_i),`
429			`.wbs_cti_i (wbs_cti_i),`
430			`.wbs_bte_i (wbs_bte_i),`
431			`.wbs_we_i (wbs_we_i),`
432			`.wbs_adr_i (wbs_adr_i),`
433			`.wbs_sel_i (wbs_sel_i),`
434			`.wbs_ack_o (wbs_ack_o),`
435			`.wbs_err_o (wbs_err_o),`
436			`.wbs_dat_i (wbs_dat_i),`
437			`.wbs_dat_o (wbs_dat_o)`
438			`);`
439
440			`endmodule`