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maiden |
/*
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Bare metal OpenCores GFX IP driver for Wishbone bus.
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Anton Fosselius, Per Lenander 2012
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*/
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#include "orgfx.h"
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#include "orgfx_regs.h"
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#define GFX_STAT_COUNT_OFFSET 16
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#define GFX_INSTRUCTION_FIFO_SIZE 1024
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#define SUBPIXEL_WIDTH 16
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/* VGA defines */
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#define VGA_BASEADDR 0x97000000 /* Bus Adress to VGA */
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#define VGA_CTRL (VGA_BASEADDR + 0x000) /* Control Register */
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#define VGA_STAT (VGA_BASEADDR + 0x004) /* Status Register */
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#define VGA_HTIM (VGA_BASEADDR + 0x008) /* Horisontal Timing Register */
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#define VGA_VTIM (VGA_BASEADDR + 0x00c) /* Vertical Timing Register */
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#define VGA_HVLEN (VGA_BASEADDR + 0x010) /* Horisontal and Vertical Total Screen Size, (Screen size + Blank) */
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#define VGA_VBARA (VGA_BASEADDR + 0x014) /* Adress to Video Base Register A */
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#define VGA_VBARB (VGA_BASEADDR + 0x018) /* Adress to Video Base Register B */
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#define VGA_PALETTE (VGA_BASEADDR + 0x800) /* Color Palette */
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#define VGA_STAT_AVMP 16
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#define VGA_CTRL_VEN 0x00000001 /* Video Enable */
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#define VGA_CTRL_HIE 0x00000002 /* HSync Interrupt Enable */
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#define VGA_CTRL_PC 0x00000800 /* 8-bit Pseudo Color Enable*/
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#define VGA_CTRL_CD8 0x00000000 /* Color Depth 8 */
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#define VGA_CTRL_CD16 0x00000200 /* Color Depth 16 */
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#define VGA_CTRL_CD24 0x00000400 /* Color Depth 24 */
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#define VGA_CTRL_CD32 0x00000600 /* Color Depth 32 */
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#define VGA_CTRL_VBL1 0x00000000 /* Burst Length 1 */
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#define VGA_CTRL_VBL2 0x00000080 /* Burst Length 2 */
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#define VGA_CTRL_VBL4 0x00000100 /* Burst Length 4 */
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#define VGA_CTRL_VBL8 0x00000180 /* Burst Length 8 */
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#define VGA_CTRL_VBSWE 0x00000020 /* Bank switch enable */
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// Generate bits from orgfx_regs.h
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/* ===================== */
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/* Control register bits */
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/* ===================== */
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#define GFX_CTRL_CD8 0 /* Color Depth 8 */
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#define GFX_CTRL_CD16 (1 << GFX_CTRL_COLOR_DEPTH ) /* Color Depth 16 */
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#define GFX_CTRL_CD24 (2 << GFX_CTRL_COLOR_DEPTH ) /* Color Depth 24 */ // Not supported!
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#define GFX_CTRL_CD32 (3 << GFX_CTRL_COLOR_DEPTH ) /* Color Depth 32 */
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#define GFX_CTRL_CDMASK (3 << GFX_CTRL_COLOR_DEPTH ) /* All color depth bits */
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#define GFX_TEXTURE_ENABLE (1 << GFX_CTRL_TEXTURE ) /* Enable Texture Reads */
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#define GFX_BLEND_ENABLE (1 << GFX_CTRL_BLENDING ) /* Enable Alpha Blending */
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#define GFX_COLORKEY_ENABLE (1 << GFX_CTRL_COLORKEY ) /* Enable Colorkeying */
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#define GFX_CLIPPING_ENABLE (1 << GFX_CTRL_CLIPPING ) /* Enable Clipping/Scissoring */
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#define GFX_ZBUFFER_ENABLE (1 << GFX_CTRL_ZBUFFER ) /* Enable depth buffer */
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#define GFX_RECT (1 << GFX_CTRL_RECT ) /* Put rect */
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#define GFX_LINE (1 << GFX_CTRL_LINE ) /* Put line */
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#define GFX_TRI (1 << GFX_CTRL_TRI ) /* Put triangle */
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#define GFX_CURVE (1 << GFX_CTRL_CURVE ) /* Put curve */
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#define GFX_INTERP (1 << GFX_CTRL_INTERP ) /* Activate interpolation */
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#define GFX_INSIDE (1 << GFX_CTRL_INSIDE ) /* Bezier inside/outside */
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#define GFX_ACTIVE_POINT0 0 /* Set the active point to p0 */
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#define GFX_ACTIVE_POINT1 (1 << GFX_CTRL_ACTIVE_POINT ) /* Set the active point to p1 */
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#define GFX_ACTIVE_POINT2 (2 << GFX_CTRL_ACTIVE_POINT ) /* Set the active point to p2 */
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#define GFX_ACTIVE_POINTMASK (3 << GFX_CTRL_ACTIVE_POINT )
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#define GFX_FORWARD_POINT (1 << GFX_CTRL_FORWARD_POINT ) /* Forward the active point */
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#define GFX_TRANSFORM_POINT (1 << GFX_CTRL_TRANSFORM_POINT) /* Transform the active point */
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/* ==================== */
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/* Status register bits */
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/* ==================== */
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#define GFX_BUSY (1 << GFX_STAT_BUSY ) /* Ready for op */
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/* Register access macros */
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#define REG8(add) *((volatile unsigned char *)(add))
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#define REG16(add) *((volatile unsigned short *)(add))
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#define REG32(add) *((volatile unsigned int *)(add))
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// Wait until req_spaces number of places in the instruction fifo are clear
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inline void orgfx_wait(unsigned int reg_spaces)
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{
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while( REG32(GFX_STATUS) & GFX_BUSY );
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//while( (REG32(GFX_STATUS) >> GFX_STAT_COUNT_OFFSET) + reg_spaces > GFX_INSTRUCTION_FIFO_SIZE);
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}
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unsigned int memory_base = GFX_VMEM;
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struct orgfx_surface* target_surface = 0;
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struct orgfx_surface* tex0_surface = 0;
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struct orgfx_surface* zbuffer_surface = 0;
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unsigned int gfx_control_reg_memory = 0;
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// Forward or transform points?
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unsigned int transformation_mode = GFX_FORWARD_POINT;
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inline void orgfx_set_colordepth(unsigned char bpp);
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void Set640x480_60(void)
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{
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// Set horizontal timing register
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REG32(VGA_HTIM) = ((96 - 1) << 24) |
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((48 - 1) << 16) |
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(640 - 1);
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// Set vertical timing register
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REG32(VGA_VTIM) = ((2 - 1) << 24) |
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((31 - 1) << 16) |
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(480 - 1);
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// Set total vertical and horizontal lenghts
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REG32(VGA_HVLEN) = ((800 - 1) << 16) | (525 - 1);
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orgfx_wait(2);
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REG32(GFX_TARGET_SIZE_X) = 640;
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REG32(GFX_TARGET_SIZE_Y) = 480;
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}
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void Set800x600_60(void)
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{
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// Set horizontal timing register
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REG32(VGA_HTIM) = ((128 - 1) << 24) |
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((88 - 1) << 16) |
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(800 - 1);
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// Set vertical timing register
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REG32(VGA_VTIM) = ((4 - 1) << 24) |
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((23 - 1) << 16) |
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(600 - 1);
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// Set total vertical and horizontal lenghts
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REG32(VGA_HVLEN) = ((1056 - 1) << 16) | (628 - 1);
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orgfx_wait(2);
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REG32(GFX_TARGET_SIZE_X) = 800;
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REG32(GFX_TARGET_SIZE_Y) = 600;
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}
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void Set1024x768_60(void)
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{
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// Set horizontal timing register
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REG32(VGA_HTIM) = ((136 - 1) << 24) |
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((160 - 1) << 16) |
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(1024 - 1);
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// Set vertical timing register
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REG32(VGA_VTIM) = ((6 - 1) << 24) |
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((29 - 1) << 16) |
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(768 - 1);
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// Set total vertical and horizontal lenghts
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REG32(VGA_HVLEN) = ((1344 - 1) << 16) | (806 - 1);
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orgfx_wait(2);
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REG32(GFX_TARGET_SIZE_X) = 1024;
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REG32(GFX_TARGET_SIZE_Y) = 768;
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}
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void orgfx_init(unsigned int memoryArea)
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{
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memory_base = memoryArea;
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// Reset VGA+GFX first
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REG32(VGA_CTRL) = 0;
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gfx_control_reg_memory = 0;
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orgfx_wait(2);
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REG32(GFX_CONTROL) = gfx_control_reg_memory;
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orgfx_vga_set_vbara(memory_base);
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orgfx_vga_set_vbarb(memory_base);
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REG32(GFX_TARGET_BASE) = memory_base;
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}
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void orgfx_vga_set_vbara(unsigned int addr)
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{
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// Set base address for Video Base Register A
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REG32(VGA_VBARA) = addr;
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}
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void orgfx_vga_set_vbarb(unsigned int addr)
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{
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// Set base address for Video Base Register B
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REG32(VGA_VBARB) = addr;
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}
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inline void orgfx_vga_bank_switch()
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{
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orgfx_wait(GFX_INSTRUCTION_FIFO_SIZE);
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REG32(VGA_CTRL) |= VGA_CTRL_VBSWE;
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}
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inline unsigned int orgfx_vga_AVMP()
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{
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// Get the active memory page bit
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unsigned int status_reg = REG32(VGA_STAT);
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status_reg = status_reg >> VGA_STAT_AVMP;
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return status_reg & 1;
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}
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void orgfx_set_colordepth(unsigned char bpp)
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{
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unsigned int vga_bpp = 0, gfx_bpp = 0;
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switch(bpp)
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{
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case 8: vga_bpp = VGA_CTRL_CD8; gfx_bpp = GFX_CTRL_CD8; break;
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case 16: vga_bpp = VGA_CTRL_CD16; gfx_bpp = GFX_CTRL_CD16; break;
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// case 24: vga_bpp = VGA_CTRL_CD24; gfx_bpp = GFX_CTRL_CD24; break; // Unsupported by gfx
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case 32: vga_bpp = VGA_CTRL_CD32; gfx_bpp = GFX_CTRL_CD32; break;
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default: break;
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}
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// Activate VGA
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REG32(VGA_CTRL) |= VGA_CTRL_VEN | VGA_CTRL_VBL8 | vga_bpp;
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gfx_control_reg_memory &= ~GFX_CTRL_CDMASK;
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gfx_control_reg_memory |= gfx_bpp;
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orgfx_wait(1);
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REG32(GFX_CONTROL) = gfx_control_reg_memory;
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}
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void orgfx_vga_set_videomode(unsigned int width, unsigned int height, unsigned char bpp)
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{
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if(width == 640 && height == 480)
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Set640x480_60();
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else if(width == 800 && height == 600)
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Set800x600_60();
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else if(width == 1024 && height == 768)
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Set1024x768_60();
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else // Default mode
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Set640x480_60();
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orgfx_set_colordepth(bpp);
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}
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struct orgfx_surface orgfx_init_surface(unsigned int width, unsigned int height)
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{
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struct orgfx_surface surface;
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surface.addr = memory_base;
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surface.w = width;
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surface.h = height;
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memory_base += (width << 1) * height; // TODO: Only true for 16 bit surfaces!
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return surface;
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}
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void orgfx_bind_rendertarget(struct orgfx_surface *surface)
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{
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target_surface = surface;
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orgfx_wait(3);
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REG32(GFX_TARGET_BASE) = surface->addr;
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REG32(GFX_TARGET_SIZE_X) = surface->w;
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REG32(GFX_TARGET_SIZE_Y) = surface->h;
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// Clear clip rect
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orgfx_cliprect(0,0,surface->w,surface->h);
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}
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void orgfx_enable_zbuffer(unsigned int enable)
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{
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if(enable)
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gfx_control_reg_memory |= GFX_ZBUFFER_ENABLE;
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else
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gfx_control_reg_memory &= ~GFX_ZBUFFER_ENABLE;
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orgfx_wait(1);
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REG32(GFX_CONTROL) = gfx_control_reg_memory;
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}
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void orgfx_bind_zbuffer(struct orgfx_surface *surface)
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{
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zbuffer_surface = surface;
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orgfx_wait(1);
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REG32(GFX_ZBUFFER_BASE) = surface->addr;
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}
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void orgfx_clear_zbuffer()
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{
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int y, x;
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for(y = 0; y < zbuffer_surface->h; ++y)
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{
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for(x = 0; x < zbuffer_surface->w; x+=2)
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{
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int addr = (y*zbuffer_surface->w + x)*2; // TODO: only works for 16bits
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REG32(zbuffer_surface->addr+addr) = 0x80008000;
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}
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}
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}
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void orgfx_enable_cliprect(unsigned int enable)
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{
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if(enable)
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gfx_control_reg_memory |= GFX_CLIPPING_ENABLE;
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else
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gfx_control_reg_memory &= ~GFX_CLIPPING_ENABLE;
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orgfx_wait(1);
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REG32(GFX_CONTROL) = gfx_control_reg_memory;
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}
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void orgfx_cliprect(unsigned int x0, unsigned int y0, unsigned int x1, unsigned int y1)
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{
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orgfx_wait(4);
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REG32(GFX_CLIP_PIXEL0_X) = x0;
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REG32(GFX_CLIP_PIXEL0_Y) = y0;
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REG32(GFX_CLIP_PIXEL1_X) = x1;
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REG32(GFX_CLIP_PIXEL1_Y) = y1;
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}
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void orgfx_srcrect(unsigned int x0, unsigned int y0, unsigned int x1, unsigned int y1)
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{
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orgfx_wait(4);
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REG32(GFX_SRC_PIXEL0_X) = x0;
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REG32(GFX_SRC_PIXEL0_Y) = y0;
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REG32(GFX_SRC_PIXEL1_X) = x1;
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REG32(GFX_SRC_PIXEL1_Y) = y1;
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}
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void orgfx_init_src()
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{
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if((gfx_control_reg_memory & GFX_TEXTURE_ENABLE) && tex0_surface)
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orgfx_srcrect(0, 0, tex0_surface->w, tex0_surface->h);
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else if(target_surface)
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orgfx_srcrect(0, 0, target_surface->w, target_surface->h);
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}
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void orgfx_set_pixel(int x, int y, unsigned int color)
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{
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if(x >= 0 && y >= 0)
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{
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325 |
|
|
int addr = (y*target_surface->w + x)*2; // TODO: only works for 16bits
|
326 |
|
|
REG32(target_surface->addr+addr) = color;
|
327 |
|
|
}
|
328 |
|
|
}
|
329 |
|
|
|
330 |
|
|
// Copies a buffer into the current render target
|
331 |
|
|
void orgfx_memcpy(unsigned int mem[], unsigned int size)
|
332 |
|
|
{
|
333 |
|
|
unsigned int i;
|
334 |
|
|
for(i=0; i < size; ++i)
|
335 |
|
|
REG32(target_surface->addr+i*4) = mem[i];
|
336 |
|
|
}
|
337 |
|
|
|
338 |
|
|
void orgfx_set_color(unsigned int color)
|
339 |
|
|
{
|
340 |
|
|
orgfx_wait(1);
|
341 |
|
|
REG32(GFX_COLOR0) = color;
|
342 |
|
|
}
|
343 |
|
|
|
344 |
|
|
|
345 |
|
|
void orgfx_set_colors(unsigned int color0, unsigned int color1, unsigned int color2)
|
346 |
|
|
{
|
347 |
|
|
orgfx_wait(3);
|
348 |
|
|
REG32(GFX_COLOR0) = color0;
|
349 |
|
|
REG32(GFX_COLOR1) = color1;
|
350 |
|
|
REG32(GFX_COLOR2) = color2;
|
351 |
|
|
}
|
352 |
|
|
|
353 |
|
|
void orgfx_rect(int x0, int y0, int x1, int y1)
|
354 |
|
|
{
|
355 |
|
|
orgfx_wait(7);
|
356 |
|
|
REG32(GFX_DEST_PIXEL_X) = x0;
|
357 |
|
|
REG32(GFX_DEST_PIXEL_Y) = y0;
|
358 |
|
|
REG32(GFX_CONTROL) = gfx_control_reg_memory | GFX_ACTIVE_POINT0 | transformation_mode;
|
359 |
|
|
REG32(GFX_DEST_PIXEL_X) = x1;
|
360 |
|
|
REG32(GFX_DEST_PIXEL_Y) = y1;
|
361 |
|
|
REG32(GFX_CONTROL) = gfx_control_reg_memory | GFX_ACTIVE_POINT1 | transformation_mode;
|
362 |
|
|
REG32(GFX_CONTROL) = gfx_control_reg_memory | GFX_RECT;
|
363 |
|
|
}
|
364 |
|
|
|
365 |
|
|
void orgfx_line(int x0, int y0, int x1, int y1)
|
366 |
|
|
{
|
367 |
|
|
orgfx_line3d(x0, y0, 0, x1, y1, 0);
|
368 |
|
|
}
|
369 |
|
|
|
370 |
|
|
void orgfx_triangle(int x0, int y0,
|
371 |
|
|
int x1, int y1,
|
372 |
|
|
int x2, int y2,
|
373 |
|
|
unsigned int interpolate)
|
374 |
|
|
{
|
375 |
|
|
orgfx_triangle3d(x0, y0, 0, x1, y1, 0, x2, y2, 0, interpolate);
|
376 |
|
|
}
|
377 |
|
|
|
378 |
|
|
void orgfx_curve(int x0, int y0,
|
379 |
|
|
int x1, int y1,
|
380 |
|
|
int x2, int y2,
|
381 |
|
|
unsigned int inside)
|
382 |
|
|
{
|
383 |
|
|
orgfx_wait(14);
|
384 |
|
|
REG32(GFX_DEST_PIXEL_Z) = 0; // Set all points depth value to zero
|
385 |
|
|
|
386 |
|
|
REG32(GFX_DEST_PIXEL_X) = x0;
|
387 |
|
|
REG32(GFX_DEST_PIXEL_Y) = y0;
|
388 |
|
|
REG32(GFX_CONTROL) = gfx_control_reg_memory | GFX_ACTIVE_POINT0 | transformation_mode;
|
389 |
|
|
REG32(GFX_DEST_PIXEL_X) = x1;
|
390 |
|
|
REG32(GFX_DEST_PIXEL_Y) = y1;
|
391 |
|
|
REG32(GFX_CONTROL) = gfx_control_reg_memory | GFX_ACTIVE_POINT1 | transformation_mode;
|
392 |
|
|
REG32(GFX_DEST_PIXEL_X) = x2;
|
393 |
|
|
REG32(GFX_DEST_PIXEL_Y) = y2;
|
394 |
|
|
REG32(GFX_CONTROL) = gfx_control_reg_memory | GFX_ACTIVE_POINT2 | transformation_mode;
|
395 |
|
|
|
396 |
|
|
if(inside)
|
397 |
|
|
gfx_control_reg_memory |= GFX_INSIDE;
|
398 |
|
|
else
|
399 |
|
|
gfx_control_reg_memory &= ~GFX_INSIDE;
|
400 |
|
|
|
401 |
|
|
REG32(GFX_CONTROL) = gfx_control_reg_memory | GFX_CURVE | GFX_TRI | GFX_INTERP;
|
402 |
|
|
}
|
403 |
|
|
|
404 |
|
|
void orgfx_triangle3d(int x0, int y0, int z0,
|
405 |
|
|
int x1, int y1, int z1,
|
406 |
|
|
int x2, int y2, int z2,
|
407 |
|
|
unsigned int interpolate)
|
408 |
|
|
{
|
409 |
|
|
orgfx_wait(13);
|
410 |
|
|
REG32(GFX_DEST_PIXEL_X) = x0;
|
411 |
|
|
REG32(GFX_DEST_PIXEL_Y) = y0;
|
412 |
|
|
REG32(GFX_DEST_PIXEL_Z) = z0;
|
413 |
|
|
REG32(GFX_CONTROL) = gfx_control_reg_memory | GFX_ACTIVE_POINT0 | transformation_mode;
|
414 |
|
|
REG32(GFX_DEST_PIXEL_X) = x1;
|
415 |
|
|
REG32(GFX_DEST_PIXEL_Y) = y1;
|
416 |
|
|
REG32(GFX_DEST_PIXEL_Z) = z1;
|
417 |
|
|
REG32(GFX_CONTROL) = gfx_control_reg_memory | GFX_ACTIVE_POINT1 | transformation_mode;
|
418 |
|
|
REG32(GFX_DEST_PIXEL_X) = x2;
|
419 |
|
|
REG32(GFX_DEST_PIXEL_Y) = y2;
|
420 |
|
|
REG32(GFX_DEST_PIXEL_Z) = z2;
|
421 |
|
|
REG32(GFX_CONTROL) = gfx_control_reg_memory | GFX_ACTIVE_POINT2 | transformation_mode;
|
422 |
|
|
|
423 |
|
|
if(interpolate)
|
424 |
|
|
REG32(GFX_CONTROL) = gfx_control_reg_memory | GFX_TRI | GFX_INTERP;
|
425 |
|
|
else
|
426 |
|
|
REG32(GFX_CONTROL) = gfx_control_reg_memory | GFX_TRI;
|
427 |
|
|
}
|
428 |
|
|
|
429 |
|
|
void orgfx_line3d(int x0, int y0, int z0, int x1, int y1, int z1)
|
430 |
|
|
{
|
431 |
|
|
orgfx_wait(9);
|
432 |
|
|
REG32(GFX_DEST_PIXEL_X) = x0;
|
433 |
|
|
REG32(GFX_DEST_PIXEL_Y) = y0;
|
434 |
|
|
REG32(GFX_DEST_PIXEL_Z) = z0;
|
435 |
|
|
REG32(GFX_CONTROL) = gfx_control_reg_memory | GFX_ACTIVE_POINT0 | transformation_mode;
|
436 |
|
|
REG32(GFX_DEST_PIXEL_X) = x1;
|
437 |
|
|
REG32(GFX_DEST_PIXEL_Y) = y1;
|
438 |
|
|
REG32(GFX_DEST_PIXEL_Z) = z1;
|
439 |
|
|
REG32(GFX_CONTROL) = gfx_control_reg_memory | GFX_ACTIVE_POINT1 | transformation_mode;
|
440 |
|
|
REG32(GFX_CONTROL) = gfx_control_reg_memory | GFX_LINE;
|
441 |
|
|
}
|
442 |
|
|
|
443 |
|
|
void orgfx_uv(unsigned int u0, unsigned int v0,
|
444 |
|
|
unsigned int u1, unsigned int v1,
|
445 |
|
|
unsigned int u2, unsigned int v2)
|
446 |
|
|
{
|
447 |
|
|
orgfx_wait(6);
|
448 |
|
|
REG32(GFX_U0) = u0;
|
449 |
|
|
REG32(GFX_V0) = v0;
|
450 |
|
|
REG32(GFX_U1) = u1;
|
451 |
|
|
REG32(GFX_V1) = v1;
|
452 |
|
|
REG32(GFX_U2) = u2;
|
453 |
|
|
REG32(GFX_V2) = v2;
|
454 |
|
|
}
|
455 |
|
|
|
456 |
|
|
void orgfx_enable_tex0(unsigned int enable)
|
457 |
|
|
{
|
458 |
|
|
orgfx_wait(1);
|
459 |
|
|
if(enable)
|
460 |
|
|
{
|
461 |
|
|
gfx_control_reg_memory |= GFX_TEXTURE_ENABLE;
|
462 |
|
|
REG32(GFX_CONTROL) = gfx_control_reg_memory;
|
463 |
|
|
}
|
464 |
|
|
else
|
465 |
|
|
{
|
466 |
|
|
gfx_control_reg_memory &= ~GFX_TEXTURE_ENABLE;
|
467 |
|
|
REG32(GFX_CONTROL) = gfx_control_reg_memory;
|
468 |
|
|
}
|
469 |
|
|
orgfx_init_src();
|
470 |
|
|
}
|
471 |
|
|
|
472 |
|
|
void orgfx_bind_tex0(struct orgfx_surface* surface)
|
473 |
|
|
{
|
474 |
|
|
orgfx_wait(3);
|
475 |
|
|
tex0_surface = surface;
|
476 |
|
|
REG32(GFX_TEX0_BASE) = surface->addr;
|
477 |
|
|
REG32(GFX_TEX0_SIZE_X) = surface->w;
|
478 |
|
|
REG32(GFX_TEX0_SIZE_Y) = surface->h;
|
479 |
|
|
orgfx_init_src();
|
480 |
|
|
}
|
481 |
|
|
|
482 |
|
|
void orgfx_enable_alpha(unsigned int enable)
|
483 |
|
|
{
|
484 |
|
|
orgfx_wait(1);
|
485 |
|
|
if(enable)
|
486 |
|
|
gfx_control_reg_memory |= GFX_BLEND_ENABLE;
|
487 |
|
|
else
|
488 |
|
|
gfx_control_reg_memory &= ~GFX_BLEND_ENABLE;
|
489 |
|
|
|
490 |
|
|
REG32(GFX_CONTROL) = gfx_control_reg_memory;
|
491 |
|
|
}
|
492 |
|
|
|
493 |
|
|
void orgfx_set_alpha(unsigned int alpha)
|
494 |
|
|
{
|
495 |
|
|
orgfx_wait(1);
|
496 |
|
|
REG32(GFX_ALPHA) = alpha;
|
497 |
|
|
}
|
498 |
|
|
|
499 |
|
|
void orgfx_enable_colorkey(unsigned int enable)
|
500 |
|
|
{
|
501 |
|
|
orgfx_wait(1);
|
502 |
|
|
if(enable)
|
503 |
|
|
gfx_control_reg_memory |= GFX_COLORKEY_ENABLE;
|
504 |
|
|
else
|
505 |
|
|
gfx_control_reg_memory &= ~GFX_COLORKEY_ENABLE;
|
506 |
|
|
|
507 |
|
|
REG32(GFX_CONTROL) = gfx_control_reg_memory;
|
508 |
|
|
}
|
509 |
|
|
|
510 |
|
|
void orgfx_set_colorkey(unsigned int colorkey)
|
511 |
|
|
{
|
512 |
|
|
orgfx_wait(1);
|
513 |
|
|
REG32(GFX_COLORKEY) = colorkey;
|
514 |
|
|
}
|
515 |
|
|
|
516 |
|
|
void orgfx_enable_transform(unsigned int enable)
|
517 |
|
|
{
|
518 |
|
|
if(enable)
|
519 |
|
|
transformation_mode = GFX_TRANSFORM_POINT;
|
520 |
|
|
else
|
521 |
|
|
transformation_mode = GFX_FORWARD_POINT;
|
522 |
|
|
}
|
523 |
|
|
|
524 |
|
|
void orgfx_set_transformation_matrix(int aa, int ab, int ac, int tx,
|
525 |
|
|
int ba, int bb, int bc, int ty,
|
526 |
|
|
int ca, int cb, int cc, int tz)
|
527 |
|
|
{
|
528 |
|
|
orgfx_wait(12);
|
529 |
|
|
REG32(GFX_AA) = aa;
|
530 |
|
|
REG32(GFX_AB) = ab;
|
531 |
|
|
REG32(GFX_AC) = ac;
|
532 |
|
|
REG32(GFX_TX) = tx;
|
533 |
|
|
REG32(GFX_BA) = ba;
|
534 |
|
|
REG32(GFX_BB) = bb;
|
535 |
|
|
REG32(GFX_BC) = bc;
|
536 |
|
|
REG32(GFX_TY) = ty;
|
537 |
|
|
REG32(GFX_CA) = ca;
|
538 |
|
|
REG32(GFX_CB) = cb;
|
539 |
|
|
REG32(GFX_CC) = cc;
|
540 |
|
|
REG32(GFX_TZ) = tz;
|
541 |
|
|
}
|
542 |
|
|
|