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-- Engineer: Joao Carlos Nunes Bittencourt

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-- Create Date:    13:18:18 03/06/2012 

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-- Design Name:    Adder Macrofunction

-- Module Name:    adder - behavioral 

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-- Project Name:   16-bit uRISC Processor

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-- Revision: 

--      1.0 - File Created

--      2.0 - Project refactoring

--

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library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity adder is

        Generic (

                WIDTH : integer := 16 );

    Port (

        sink_a   : in std_logic_vector (WIDTH-1 downto 0);

        sink_b   : in std_logic_vector (WIDTH-1 downto 0);

        src_data : out std_logic_vector (WIDTH-1 downto 0) );

end adder;

architecture behavioral of adder is

begin

        process(sink_a, sink_b)

                variable aux : std_logic_vector(WIDTH-1 downto 0) := conv_std_logic_vector(0,WIDTH);

        begin

                aux := sink_a + sink_b;

                src_data <= aux;

        end process;

end behavioral;