1 |
12 |
joaocarlos |
----------------------------------------------------------------------------------
|
2 |
|
|
-- Engineer: Joao Carlos Nunes Bittencourt
|
3 |
|
|
----------------------------------------------------------------------------------
|
4 |
|
|
-- Create Date: 13:18:18 03/06/2012
|
5 |
|
|
----------------------------------------------------------------------------------
|
6 |
|
|
-- Design Name: Opcode Package
|
7 |
|
|
-- Package Name: flags
|
8 |
|
|
----------------------------------------------------------------------------------
|
9 |
|
|
-- Project Name: 16-bit uRISC Processor
|
10 |
|
|
----------------------------------------------------------------------------------
|
11 |
|
|
-- Revision:
|
12 |
|
|
-- 1.0 - File Created
|
13 |
|
|
-- 2.0 - Project refactoring
|
14 |
2 |
joaocarlos |
--
|
15 |
12 |
joaocarlos |
----------------------------------------------------------------------------------
|
16 |
4 |
joaocarlos |
library ieee;
|
17 |
|
|
use ieee.std_logic_1164.all;
|
18 |
2 |
joaocarlos |
|
19 |
12 |
joaocarlos |
package operations is
|
20 |
2 |
joaocarlos |
constant add: std_logic_vector (4 downto 0) := "00000";
|
21 |
|
|
constant addinc: std_logic_vector (4 downto 0) := "00001";
|
22 |
|
|
constant inca: std_logic_vector (4 downto 0) := "00011";
|
23 |
|
|
constant subdec: std_logic_vector (4 downto 0) := "00100";
|
24 |
|
|
constant sub: std_logic_vector (4 downto 0) := "00101";
|
25 |
|
|
constant deca: std_logic_vector (4 downto 0) := "00110";
|
26 |
|
|
constant lsl: std_logic_vector (4 downto 0) := "01000"; -- Left shift logic
|
27 |
|
|
constant asr: std_logic_vector (4 downto 0) := "01001"; -- Aritmetic shift right
|
28 |
|
|
constant zeros: std_logic_vector (4 downto 0) := "10000";
|
29 |
|
|
constant land: std_logic_vector (4 downto 0) := "10001"; -- Logic and
|
30 |
|
|
constant andnota: std_logic_vector (4 downto 0) := "10010";
|
31 |
|
|
constant passb: std_logic_vector (4 downto 0) := "10011";
|
32 |
|
|
constant andnotb: std_logic_vector (4 downto 0) := "10100";
|
33 |
|
|
constant passa: std_logic_vector (4 downto 0) := "10101";
|
34 |
|
|
constant lxor: std_logic_vector (4 downto 0) := "10110"; -- Logic XOR
|
35 |
|
|
constant lor: std_logic_vector (4 downto 0) := "10111"; -- Logic OR
|
36 |
|
|
constant lnor: std_logic_vector (4 downto 0) := "11000"; -- Logic NOR
|
37 |
|
|
constant lxnor: std_logic_vector (4 downto 0) := "11001"; -- Logic XOR
|
38 |
|
|
constant passnota: std_logic_vector (4 downto 0) := "11010";
|
39 |
|
|
constant ornota: std_logic_vector (4 downto 0) := "11011";
|
40 |
|
|
constant passnotb: std_logic_vector (4 downto 0) := "11100";
|
41 |
|
|
constant ornotb: std_logic_vector (4 downto 0) := "11101";
|
42 |
|
|
constant lnand: std_logic_vector (4 downto 0) := "11110"; -- Logic NAND
|
43 |
|
|
constant ones: std_logic_vector (4 downto 0) := "11111";
|
44 |
|
|
constant lcl: std_logic_vector (4 downto 0) := "00010"; -- Load constant low
|
45 |
|
|
constant lch: std_logic_vector (4 downto 0) := "00111"; -- Load constant high
|
46 |
12 |
joaocarlos |
end operations;
|