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jclaytons |
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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package fifo_pack is
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-- Component declarations not provided any more.
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-- With VHDL '93 and newer, component declarations are allowed,
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-- but not required.
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--
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-- Please to try direct instantiation instead, for example:
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--
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-- instance_name : entity work.entity_name(beh)
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--
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end fifo_pack;
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--------------------------------------------------------------
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-- SWISS ARMY FIFO with fill level output
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--------------------------------------------------------------
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-- Description:
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--
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-- This is the same as "fifo_with_fill_level" but it has been
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-- coded to select whether Block RAMs or distributed RAMs are inferred.
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--
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-- Note : When USE_BRAM=0, the behavior when reading the FIFO is to
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-- make read data available immediately during the clock cycle
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-- in which fifo_rd_i='1'. When USE_BRAM/=0, then an additional
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-- clock cycle occurs following the fifo_rd_i pulse, before the
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-- output data is available.
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-- Please be aware of this.
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--
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--
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use IEEE.MATH_REAL.ALL;
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library work;
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use work.function_pack.all;
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entity swiss_army_fifo is
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generic (
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USE_BRAM : integer := 1; -- Set to nonzero value for BRAM, zero for distributed RAM
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WIDTH : integer := 8;
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DEPTH : integer := 5;
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FILL_LEVEL_BITS : integer := 3; -- Should be at least int(floor(log2(DEPTH))+1.0)
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PF_FULL_POINT : integer := 3;
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PF_FLAG_POINT : integer := 2;
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PF_EMPTY_POINT : integer := 0
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);
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port (
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sys_rst_n : in std_logic; -- Asynchronous
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sys_clk : in std_logic;
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sys_clk_en : in std_logic;
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reset_i : in std_logic; -- Synchronous
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fifo_wr_i : in std_logic;
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fifo_din : in unsigned(WIDTH-1 downto 0);
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fifo_rd_i : in std_logic;
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fifo_dout : out unsigned(WIDTH-1 downto 0);
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fifo_fill_level : out unsigned(FILL_LEVEL_BITS-1 downto 0);
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fifo_full : out std_logic;
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fifo_empty : out std_logic;
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fifo_pf_full : out std_logic;
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fifo_pf_flag : out std_logic;
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fifo_pf_empty : out std_logic
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);
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end swiss_army_fifo;
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architecture beh of swiss_army_fifo is
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-- Constants
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constant FLG_WIDTH : integer := bit_width(DEPTH); -- Bit Width of memory address. Pointers are one bit wider,
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-- so that fill_level can represent the full quantity of
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-- items stored in the FIFO. This is important when DEPTH
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-- is an even power of 2.
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-- Signal Declarations
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signal rd_row : unsigned(FLG_WIDTH downto 0);
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signal wr_row : unsigned(FLG_WIDTH downto 0);
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signal fill_level : unsigned(FLG_WIDTH downto 0);
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signal ram_we_a : std_logic;
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signal ram_dout : unsigned(WIDTH-1 downto 0);
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TYPE STATE_TYPE IS (st_empty, st_data, st_full);
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signal current_state : STATE_TYPE ;
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signal bram_dat_b : unsigned(WIDTH-1 downto 0);
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BEGIN
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fifo_empty <= '1' when (current_state=st_empty) else '0';
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fifo_full <= '1' when (current_state=st_full) else '0';
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fifo_pf_full <= '1' when (fill_level>=PF_FULL_POINT or current_state=st_full) else '0';
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fifo_pf_flag <= '1' when (fill_level>=PF_FLAG_POINT) else '0';
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fifo_pf_empty <= '1' when (fill_level<=PF_EMPTY_POINT and current_state/=st_full) else '0';
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fifo_fill_level <= resize(fill_level,FILL_LEVEL_BITS);
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-------------------------
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-- The FIFO Fill Level
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fill_level_proc: process(wr_row, rd_row, current_state)
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begin
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if (current_state=st_empty) then
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fill_level <= (others=>'0');
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elsif (wr_row>rd_row) then
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fill_level <= wr_row-rd_row;
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else
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fill_level <= DEPTH+(wr_row-rd_row);
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end if;
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end process;
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-------------------------
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-- The FIFO memory
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-- Port A is the write side.
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-- Port B is dedicated to reading only.
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-- The hexfile is used to permit initialization of the RAM
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fifo_ram : entity work.swiss_army_ram(beh)
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generic map(
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USE_BRAM => USE_BRAM,
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WRITETHRU => 0, -- Set to nonzero value for writethrough mode
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USE_FILE => 0, -- Set to nonzero value to use INIT_FILE
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INIT_VAL => 0,
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INIT_SEL => 0, -- No generate loop here
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INIT_FILE => "foo.txt", -- ASCII hexadecimal init file name (not needed)
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FIL_WIDTH => 32, -- Bit width of init file lines
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ADR_WIDTH => FLG_WIDTH,
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DAT_WIDTH => WIDTH
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)
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port map (
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clk_a => sys_clk,
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clk_b => sys_clk,
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adr_a_i => wr_row(FLG_WIDTH-1 downto 0),
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adr_b_i => rd_row(FLG_WIDTH-1 downto 0),
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we_a_i => ram_we_a,
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en_a_i => sys_clk_en,
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dat_a_i => fifo_din,
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dat_a_o => open,
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we_b_i => '0',
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en_b_i => sys_clk_en,
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dat_b_i => bram_dat_b,
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dat_b_o => ram_dout
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);
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bram_dat_b <= (others=>'0');
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ram_we_a <= '1' when fifo_wr_i='1' and (current_state/=st_full or (current_state=st_full and fifo_rd_i='1')) else '0';
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fifo_dout <= ram_dout;
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-------------------------
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-- The FIFO state machine
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clocked : PROCESS(sys_clk, sys_rst_n)
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procedure do_write is
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begin
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if (wr_row=DEPTH-1) then -- Roll buffer index for non-power-of-two
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wr_row <= (others=>'0');
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else
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wr_row<=wr_row+1;
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end if;
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end do_write;
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procedure do_read is
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begin
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if (rd_row=DEPTH-1) then -- Roll buffer index for non-power-of-two
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rd_row <= (others=>'0');
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else
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rd_row<=rd_row+1;
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end if;
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end do_read;
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begin
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if (sys_rst_n = '0') then
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current_state <= st_empty;
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rd_row <= (others=>'0');
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wr_row <= (others=>'0');
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elsif (sys_clk'EVENT and sys_clk = '1') then
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if (sys_clk_en='1') then
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if (reset_i='1') then
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current_state <= st_empty;
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wr_row <= (others=>'0');
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rd_row <= (others=>'0');
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else
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case current_state is
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-- When empty, one can only read if also writing
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when st_empty =>
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if (fifo_wr_i='1') then
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do_write;
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if (fifo_rd_i='1') then
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do_read;
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else
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current_state<=st_data;
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end if;
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end if;
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when st_data =>
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if (fifo_wr_i='1') then
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do_write;
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if (fifo_rd_i='0' and fill_level=DEPTH-1) then
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current_state<=st_full;
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end if;
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end if;
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if (fifo_rd_i='1') then
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do_read;
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if (fifo_wr_i='0' and fill_level=1) then
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current_state<=st_empty;
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end if;
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end if;
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-- When full, one can only write if also reading
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when st_full =>
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if (fifo_rd_i='1') then
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do_read;
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if (fifo_wr_i='1') then
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do_write;
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else
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current_state<=st_data;
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end if;
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end if;
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when others => null;
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end case;
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end if;
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end if; -- sys_clk_en
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end if; -- sys_clk
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end process clocked;
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end beh;
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--------------------------------------------------------------
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-- VALIDATION FIFO with fill level output
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--------------------------------------------------------------
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-- Description:
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--
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-- This is the same as "swiss_army_fifo" but it has been given
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-- two head pointers. One of them is used for loading new data,
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-- and the other is used when the loaded data is to be validated,
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-- and for tracking the number of validated data entries contained
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-- within the FIFO.
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--
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-- This FIFO was envisioned for working with packetized data, where
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-- a data validation check is available at the end of the packet, such
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-- as a CRC field.
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--
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-- The principle at work here is that new data bytes are written
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-- using head pointer A, but if at the end of the packet, the data
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-- are deemed to be invalid, then head pointer A is "reset" back
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-- to the last valid point, thereby neatly "throwing away" the
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-- invalid data into the "bit bucket." On the other hand, if the data are
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-- deemed valid, then head pointer B is loaded to be equal to head
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-- pointer A, thereby causing the entire validated packet to become
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-- available for reading.
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--
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-- The read side of the FIFO only presents validated data for reading.
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--
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-- This situation gives rise to two sets of FIFO status outputs,
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-- one set for each side of the FIFO. Thus, there is a write fill
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-- level, and a read fill level, each with full accoutrements.
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--
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-- The validation or invalidation is done by asserting the appropriate
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-- signal during a write cycle. If both signals are asserted at the
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-- same time, the signals are ignored, and no validation or invalidation
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-- is performed.
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--
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-- Validation or invalidation can be performed at any time. If the data
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-- already loaded into the FIFO are validated when the FIFO writing side is
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-- full, then the reading side becomes full at that time. However, no new
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-- data can be written into the FIFO when it is full, for obvious reasons.
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--
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-- On the other hand, if the FIFO is not full, and a new data byte is being
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-- written at the same time that an invalidation is being performed, then the
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-- new data value is technically written into the FIFO RAM, but it can never
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-- be read out of the storage since the pointers are updated at the same time,
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-- effectively cutting the new data value out of the valid FIFO area.
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-- This is as it should be, since the new data are technically considered
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-- invalid in that case.
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--
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-- Further musings:
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-- Because validation/invalidation can happen even when writes are not being
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-- performed, one may consider the wr_dat_good_i and wr_dat_bad_i inputs as
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-- synchronous FIFO pointer load commands. Asserting wr_dat_good_i has the
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-- effect of loading wr_row_b so that it is the same as wr_row_a. Asserting
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-- wr_dat_bad_i has the effect of keeping wr_row_b set to the current wr_row_a
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-- value.
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--
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-- Thus, if one were to tie wr_dat_good_i to '1' and wr_dat_bad_i to '0', then
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-- this "validation" FIFO operates identically to a regular FIFO, in which all
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-- data are considered valid at the time they are written into the FIFO.
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--
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-- Note : When USE_BRAM=0, the behavior when reading the FIFO is to
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305 |
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-- make read data available immediately during the clock cycle
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306 |
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-- in which fifo_rd_i='1'. When USE_BRAM/=0, then an additional
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307 |
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|
-- clock cycle occurs following the fifo_rd_i pulse, before the
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308 |
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-- output data is available.
|
309 |
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-- Please be aware of this.
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310 |
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--
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311 |
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--
|
312 |
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313 |
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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315 |
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use IEEE.NUMERIC_STD.ALL;
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316 |
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use IEEE.MATH_REAL.ALL;
|
317 |
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318 |
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library work;
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use work.function_pack.all;
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320 |
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321 |
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entity validation_fifo is
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generic(
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323 |
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USE_BRAM : integer := 1; -- Set to nonzero value for BRAM, zero for distributed RAM
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324 |
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WIDTH : integer := 8;
|
325 |
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DEPTH : integer := 5;
|
326 |
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FILL_LEVEL_BITS : integer := 3; -- Should be at least int(floor(log2(DEPTH))+1.0)
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327 |
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PF_FULL_POINT : integer := 3;
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328 |
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PF_FLAG_POINT : integer := 2;
|
329 |
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PF_EMPTY_POINT : integer := 0
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330 |
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);
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331 |
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port (
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332 |
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sys_rst_n : in std_logic; -- Asynchronous
|
333 |
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sys_clk : in std_logic;
|
334 |
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sys_clk_en : in std_logic;
|
335 |
|
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|
336 |
|
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reset_i : in std_logic; -- Synchronous
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337 |
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338 |
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-- Write Data Interface
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339 |
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wr_i : in std_logic; -- Data loaded upon assertion
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340 |
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wr_dat_good_i : in std_logic; -- FIFO data validated upon assertion
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341 |
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wr_dat_bad_i : in std_logic; -- FIFO data invalidated upon assertion
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342 |
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wr_dat_i : in unsigned(WIDTH-1 downto 0);
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343 |
|
|
|
344 |
|
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-- Write Side Status
|
345 |
|
|
wr_fill_level_o : out unsigned(FILL_LEVEL_BITS-1 downto 0);
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346 |
|
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wr_full_o : out std_logic;
|
347 |
|
|
wr_empty_o : out std_logic;
|
348 |
|
|
wr_pf_full_o : out std_logic;
|
349 |
|
|
wr_pf_flag_o : out std_logic;
|
350 |
|
|
wr_pf_empty_o : out std_logic;
|
351 |
|
|
|
352 |
|
|
-- Read Data Interface (valid data only)
|
353 |
|
|
rd_i : in std_logic;
|
354 |
|
|
rd_dat_o : out unsigned(WIDTH-1 downto 0);
|
355 |
|
|
|
356 |
|
|
-- Read Side Status
|
357 |
|
|
rd_fill_level_o : out unsigned(FILL_LEVEL_BITS-1 downto 0);
|
358 |
|
|
rd_full_o : out std_logic;
|
359 |
|
|
rd_empty_o : out std_logic;
|
360 |
|
|
rd_pf_full_o : out std_logic;
|
361 |
|
|
rd_pf_flag_o : out std_logic;
|
362 |
|
|
rd_pf_empty_o : out std_logic
|
363 |
|
|
);
|
364 |
|
|
end validation_fifo;
|
365 |
|
|
|
366 |
|
|
architecture beh of validation_fifo is
|
367 |
|
|
|
368 |
|
|
-- Constants
|
369 |
|
|
constant FLG_WIDTH : integer := bit_width(DEPTH); -- Bit Width of memory address. Pointers are one bit wider,
|
370 |
|
|
-- so that fill_level can represent the full quantity of
|
371 |
|
|
-- items stored in the FIFO. This is important when DEPTH
|
372 |
|
|
-- is an even power of 2.
|
373 |
|
|
|
374 |
|
|
-- Signal Declarations
|
375 |
|
|
signal rd_row : unsigned(FLG_WIDTH downto 0);
|
376 |
|
|
signal wr_row_a : unsigned(FLG_WIDTH downto 0);
|
377 |
|
|
signal wr_row_b : unsigned(FLG_WIDTH downto 0);
|
378 |
|
|
signal fill_level_a : unsigned(FLG_WIDTH+1 downto 0);
|
379 |
|
|
signal fill_level_b : unsigned(FLG_WIDTH+1 downto 0);
|
380 |
|
|
signal ram_we_a : std_logic;
|
381 |
|
|
signal ram_dout : unsigned(WIDTH-1 downto 0);
|
382 |
|
|
|
383 |
|
|
TYPE STATE_TYPE IS (st_empty, st_data, st_full);
|
384 |
|
|
signal current_state : STATE_TYPE ;
|
385 |
|
|
|
386 |
|
|
signal bram_dat_b : unsigned(WIDTH-1 downto 0);
|
387 |
|
|
|
388 |
|
|
signal fifo_level_a : unsigned(FILL_LEVEL_BITS-1 downto 0);
|
389 |
|
|
signal fifo_full_a : std_logic;
|
390 |
|
|
signal fifo_empty_a : std_logic;
|
391 |
|
|
signal fifo_pf_full_a : std_logic;
|
392 |
|
|
signal fifo_pf_flag_a : std_logic;
|
393 |
|
|
signal fifo_pf_empty_a : std_logic;
|
394 |
|
|
|
395 |
|
|
signal fifo_level_b : unsigned(FILL_LEVEL_BITS-1 downto 0);
|
396 |
|
|
signal fifo_full_b : std_logic;
|
397 |
|
|
signal fifo_empty_b : std_logic;
|
398 |
|
|
signal fifo_pf_full_b : std_logic;
|
399 |
|
|
signal fifo_pf_flag_b : std_logic;
|
400 |
|
|
signal fifo_pf_empty_b : std_logic;
|
401 |
|
|
|
402 |
|
|
BEGIN
|
403 |
|
|
|
404 |
|
|
fifo_level_a <= resize(fill_level_a,FILL_LEVEL_BITS);
|
405 |
|
|
fifo_full_a <= '1' when (fill_level_a=DEPTH) else '0';
|
406 |
|
|
fifo_empty_a <= '1' when (fill_level_a=0) else '0';
|
407 |
|
|
fifo_pf_full_a <= '1' when (fill_level_a>=PF_FULL_POINT) else '0';
|
408 |
|
|
fifo_pf_flag_a <= '1' when (fill_level_a>=PF_FLAG_POINT) else '0';
|
409 |
|
|
fifo_pf_empty_a <= '1' when (fill_level_a<=PF_EMPTY_POINT) else '0';
|
410 |
|
|
|
411 |
|
|
fifo_level_b <= resize(fill_level_b,FILL_LEVEL_BITS);
|
412 |
|
|
fifo_full_b <= '1' when (fill_level_b=DEPTH) else '0';
|
413 |
|
|
fifo_empty_b <= '1' when (fill_level_b=0) else '0';
|
414 |
|
|
fifo_pf_full_b <= '1' when (fill_level_b>=PF_FULL_POINT) else '0';
|
415 |
|
|
fifo_pf_flag_b <= '1' when (fill_level_b>=PF_FLAG_POINT) else '0';
|
416 |
|
|
fifo_pf_empty_b <= '1' when (fill_level_b<=PF_EMPTY_POINT) else '0';
|
417 |
|
|
|
418 |
|
|
-------------------------
|
419 |
|
|
-- The FIFO Fill Level
|
420 |
|
|
fill_level_a <= (others=>'0') when wr_row_a=rd_row else
|
421 |
|
|
('0' & wr_row_a)-('0' & rd_row) when wr_row_a>rd_row else
|
422 |
|
|
(2**(FLG_WIDTH+1))+(('0' & wr_row_a)-('0' & rd_row));
|
423 |
|
|
|
424 |
|
|
fill_level_b <= (others=>'0') when wr_row_b=rd_row else
|
425 |
|
|
('0' & wr_row_b)-('0' & rd_row) when wr_row_b>rd_row else
|
426 |
|
|
(2**(FLG_WIDTH+1))+(('0' & wr_row_b)-('0' & rd_row));
|
427 |
|
|
|
428 |
|
|
-------------------------
|
429 |
|
|
-- The FIFO memory
|
430 |
|
|
|
431 |
|
|
-- Port A is the write side.
|
432 |
|
|
-- Port B is dedicated to reading only.
|
433 |
|
|
-- The hexfile is used to permit initialization of the RAM
|
434 |
|
|
|
435 |
|
|
fifo_ram : entity work.swiss_army_ram(beh)
|
436 |
|
|
generic map(
|
437 |
|
|
USE_BRAM => USE_BRAM,
|
438 |
|
|
WRITETHRU => 0, -- Set to nonzero value for writethrough mode
|
439 |
|
|
USE_FILE => 0, -- Set to nonzero value to use INIT_FILE
|
440 |
|
|
INIT_VAL => 0,
|
441 |
|
|
INIT_SEL => 0, -- No generate loop here
|
442 |
|
|
INIT_FILE => "foo.txt", -- ASCII hexadecimal init file name (not needed)
|
443 |
|
|
FIL_WIDTH => 32, -- Bit width of init file lines
|
444 |
|
|
ADR_WIDTH => FLG_WIDTH,
|
445 |
|
|
DAT_WIDTH => WIDTH
|
446 |
|
|
)
|
447 |
|
|
port map (
|
448 |
|
|
clk_a => sys_clk,
|
449 |
|
|
clk_b => sys_clk,
|
450 |
|
|
|
451 |
|
|
adr_a_i => wr_row_a(FLG_WIDTH-1 downto 0),
|
452 |
|
|
adr_b_i => rd_row(FLG_WIDTH-1 downto 0),
|
453 |
|
|
|
454 |
|
|
we_a_i => ram_we_a,
|
455 |
|
|
en_a_i => sys_clk_en,
|
456 |
|
|
dat_a_i => wr_dat_i,
|
457 |
|
|
dat_a_o => open,
|
458 |
|
|
|
459 |
|
|
we_b_i => '0',
|
460 |
|
|
en_b_i => sys_clk_en,
|
461 |
|
|
dat_b_i => bram_dat_b,
|
462 |
|
|
dat_b_o => ram_dout
|
463 |
|
|
);
|
464 |
|
|
|
465 |
|
|
bram_dat_b <= (others=>'0');
|
466 |
|
|
ram_we_a <= '1' when wr_i='1' and fifo_full_a='0' else '0';
|
467 |
|
|
rd_dat_o <= ram_dout;
|
468 |
|
|
|
469 |
|
|
-------------------------
|
470 |
|
|
-- The FIFO writing process
|
471 |
|
|
wr_proc : PROCESS(sys_clk, sys_rst_n)
|
472 |
|
|
begin
|
473 |
|
|
if (sys_rst_n = '0') then
|
474 |
|
|
wr_row_a <= (others=>'0'); -- For unvalidated data
|
475 |
|
|
wr_row_b <= (others=>'0'); -- For validated data
|
476 |
|
|
elsif (sys_clk'event and sys_clk = '1') then
|
477 |
|
|
if (sys_clk_en='1') then
|
478 |
|
|
if (reset_i='1') then
|
479 |
|
|
wr_row_a <= (others=>'0');
|
480 |
|
|
wr_row_b <= (others=>'0');
|
481 |
|
|
else
|
482 |
|
|
if (wr_i='1') then
|
483 |
|
|
if (fifo_full_a='1') then
|
484 |
|
|
null; -- FIFO is full! Don't do any writes.
|
485 |
|
|
-- However, still handle validation/invalidation
|
486 |
|
|
if (wr_dat_good_i='1' and wr_dat_bad_i='0') then
|
487 |
|
|
wr_row_b <= wr_row_a;
|
488 |
|
|
end if;
|
489 |
|
|
if (wr_dat_bad_i='1' and wr_dat_good_i='0') then
|
490 |
|
|
wr_row_a <= wr_row_b;
|
491 |
|
|
end if;
|
492 |
|
|
else
|
493 |
|
|
wr_row_a <= wr_row_a+1;
|
494 |
|
|
-- Handle data validation/invalidation during writes
|
495 |
|
|
if (wr_dat_good_i='1' and wr_dat_bad_i='0') then
|
496 |
|
|
wr_row_b <= wr_row_a+1;
|
497 |
|
|
end if;
|
498 |
|
|
if (wr_dat_bad_i='1' and wr_dat_good_i='0') then
|
499 |
|
|
wr_row_a <= wr_row_b;
|
500 |
|
|
end if;
|
501 |
|
|
end if;
|
502 |
|
|
else
|
503 |
|
|
-- Handle validation/invalidation when not writing
|
504 |
|
|
if (wr_dat_good_i='1' and wr_dat_bad_i='0') then
|
505 |
|
|
wr_row_b <= wr_row_a;
|
506 |
|
|
end if;
|
507 |
|
|
if (wr_dat_bad_i='1' and wr_dat_good_i='0') then
|
508 |
|
|
wr_row_a <= wr_row_b;
|
509 |
|
|
end if;
|
510 |
|
|
end if;
|
511 |
|
|
end if;
|
512 |
|
|
end if; -- wr_clk_en
|
513 |
|
|
end if; -- sys_clk
|
514 |
|
|
end process wr_proc;
|
515 |
|
|
|
516 |
|
|
-------------------------
|
517 |
|
|
-- The FIFO reading process
|
518 |
|
|
rd_proc : PROCESS(sys_clk, sys_rst_n)
|
519 |
|
|
begin
|
520 |
|
|
if (sys_rst_n = '0') then
|
521 |
|
|
rd_row <= (others=>'0');
|
522 |
|
|
elsif (sys_clk'event and sys_clk = '1') then
|
523 |
|
|
if (sys_clk_en='1') then
|
524 |
|
|
if (reset_i='1') then
|
525 |
|
|
rd_row <= (others=>'0');
|
526 |
|
|
else
|
527 |
|
|
if (rd_i='1') then
|
528 |
|
|
if (fifo_empty_b='1') then
|
529 |
|
|
null; -- FIFO is empty! Don't read anything.
|
530 |
|
|
else
|
531 |
|
|
rd_row <= rd_row+1;
|
532 |
|
|
end if;
|
533 |
|
|
end if;
|
534 |
|
|
end if;
|
535 |
|
|
end if; -- rd_clk_en
|
536 |
|
|
end if; -- sys_clk
|
537 |
|
|
end process rd_proc;
|
538 |
|
|
|
539 |
|
|
-- Provide Output Status
|
540 |
|
|
wr_fill_level_o <= fifo_level_a;
|
541 |
|
|
wr_full_o <= fifo_full_a;
|
542 |
|
|
wr_empty_o <= fifo_empty_a;
|
543 |
|
|
wr_pf_full_o <= fifo_pf_full_a;
|
544 |
|
|
wr_pf_flag_o <= fifo_pf_flag_a;
|
545 |
|
|
wr_pf_empty_o <= fifo_pf_empty_a;
|
546 |
|
|
|
547 |
|
|
rd_fill_level_o <= fifo_level_b;
|
548 |
|
|
rd_full_o <= fifo_full_b;
|
549 |
|
|
rd_empty_o <= fifo_empty_b;
|
550 |
|
|
rd_pf_full_o <= fifo_pf_full_b;
|
551 |
|
|
rd_pf_flag_o <= fifo_pf_flag_b;
|
552 |
|
|
rd_pf_empty_o <= fifo_pf_empty_b;
|
553 |
|
|
|
554 |
|
|
end beh;
|
555 |
|
|
|
556 |
|
|
--------------------------------------------------------------
|
557 |
|
|
-- FIFO-LIFO with fill level output
|
558 |
|
|
--------------------------------------------------------------
|
559 |
|
|
--
|
560 |
|
|
-- Author: John Clayton
|
561 |
|
|
-- Update: Nov. 16, 2016 Copied "swiss_army_fifo" component, and revised it.
|
562 |
|
|
--
|
563 |
|
|
-- Description
|
564 |
|
|
-------------------------------------------------------------------------------
|
565 |
|
|
-- This is the same as "swiss_army_fifo" but it has been given the ability
|
566 |
|
|
-- to pull the last written data back out of the FIFO. This is where the
|
567 |
|
|
-- "LIFO" function incides, since FIFO signifies "First In, First Out"
|
568 |
|
|
-- videlicet "LIFO" signifies "Last In, First Out." The LIFO function is
|
569 |
|
|
-- also known as a hardware "stack." The stack is a data structure known
|
570 |
|
|
-- to computer programmers in which a "push" operation adds a new data value
|
571 |
|
|
-- to the top of the stack, while a "pop" operation removes the most recently
|
572 |
|
|
-- added data value from the top of the stack.
|
573 |
|
|
--
|
574 |
|
|
-- Initially,about five minutes of coding effort was put into transmogrifying
|
575 |
|
|
-- the "fifo_pack" package into a new package, to be called "stack_pack."
|
576 |
|
|
-- However, it was soon realized by the author that stacks are much less
|
577 |
|
|
-- frequently needed as compared with FIFOs, and that furthermore adding a
|
578 |
|
|
-- LIFO function to a FIFO would be a simple task, not requiring a complete
|
579 |
|
|
-- rewrite of all the components in the fifo_pack. Also, when using the
|
580 |
|
|
-- fifo_lifo as a simple stack or lifo, the fifo read port can be tied to
|
581 |
|
|
-- constant signals, which will result in the FIFO tail pointer being
|
582 |
|
|
-- "optimized out" of the design at synthesis time, resulting in a nice
|
583 |
|
|
-- compact LIFO only function. The same optimization benefit is realized
|
584 |
|
|
-- with regard to the status signals, whenever they are not needed.
|
585 |
|
|
--
|
586 |
|
|
-- As with the swiss_army_fifo, this module is not well suited to crossing
|
587 |
|
|
-- from one clock domain to another. For that purpose, there exist other,
|
588 |
|
|
-- more suitable FIFOs in the world.
|
589 |
|
|
--
|
590 |
|
|
-- Since this module retains characteristics of both a FIFO and a LIFO, it
|
591 |
|
|
-- can be used to implement a "leaky stack" where the older contents can be
|
592 |
|
|
-- emptied out. Alternately, it can be used to implement a FIFO in which
|
593 |
|
|
-- elements of data which have been enqueued can be "uncommitted" and removed
|
594 |
|
|
-- even after they were written into the FIFO.
|
595 |
|
|
--
|
596 |
|
|
-- Ahh, yes, this brings us to the question of what priority is to be given
|
597 |
|
|
-- when a fifo_rd and lifo_rd are both requested at the same time... Well,
|
598 |
|
|
-- in the event that there are at least two items in the FIFO, then both
|
599 |
|
|
-- operations can be performed simultaneously. Also, if there is only one
|
600 |
|
|
-- item in the FIFO, but a write is being performed, then here again both
|
601 |
|
|
-- read operations can be performed simultaneously. However, if only one item
|
602 |
|
|
-- exists inside the FIFO, and both reads are requested at the same time,
|
603 |
|
|
-- and there is no write proffered, then what is to be done? The answer is
|
604 |
|
|
-- that one of the reads must be ignored, and the generic FIFO_RD_FIRST
|
605 |
|
|
-- determines the behavior. If FIFO_RD_FIRST is non-zero, then the module
|
606 |
|
|
-- gives priority to the fifo_rd input. Otherwise, the lifo_rd input is
|
607 |
|
|
-- acted upon. Just as for the case of the plain FIFO, the user is
|
608 |
|
|
-- responsible for determining further error conditions based on the fill
|
609 |
|
|
-- level.
|
610 |
|
|
--
|
611 |
|
|
-- Note : When USE_BRAM=0, the behavior when reading the FIFO is to
|
612 |
|
|
-- make read data available immediately during the clock cycle
|
613 |
|
|
-- in which fifo_rd_i='1'. When USE_BRAM/=0, then an additional
|
614 |
|
|
-- clock cycle occurs following the fifo_rd_i pulse, before the
|
615 |
|
|
-- output data is available.
|
616 |
|
|
-- Please be aware of this.
|
617 |
|
|
--
|
618 |
|
|
--
|
619 |
|
|
|
620 |
|
|
library IEEE;
|
621 |
|
|
use IEEE.STD_LOGIC_1164.ALL;
|
622 |
|
|
use IEEE.NUMERIC_STD.ALL;
|
623 |
|
|
use IEEE.MATH_REAL.ALL;
|
624 |
|
|
|
625 |
|
|
library work;
|
626 |
|
|
use work.function_pack.all;
|
627 |
|
|
|
628 |
|
|
entity fifo_lifo is
|
629 |
|
|
generic(
|
630 |
|
|
USE_BRAM : integer := 1; -- Set to nonzero value for BRAM, zero for distributed RAM
|
631 |
|
|
FIFO_RD_FIRST : integer := 0; -- Set non-zero to have fifo_rd take priority for the single item reading case
|
632 |
|
|
WIDTH : integer := 8;
|
633 |
|
|
DEPTH : integer := 5;
|
634 |
|
|
FILL_LEVEL_BITS : integer := 3; -- Should be at least int(floor(log2(DEPTH))+1.0)
|
635 |
|
|
PF_FULL_POINT : integer := 3;
|
636 |
|
|
PF_FLAG_POINT : integer := 2;
|
637 |
|
|
PF_EMPTY_POINT : integer := 0
|
638 |
|
|
);
|
639 |
|
|
port (
|
640 |
|
|
sys_rst_n : in std_logic; -- Asynchronous
|
641 |
|
|
sys_clk : in std_logic;
|
642 |
|
|
sys_clk_en : in std_logic;
|
643 |
|
|
|
644 |
|
|
reset_i : in std_logic; -- Synchronous
|
645 |
|
|
|
646 |
|
|
-- FIFO/LIFO data input
|
647 |
|
|
fifo_wr_i : in std_logic;
|
648 |
|
|
fifo_din : in unsigned(WIDTH-1 downto 0);
|
649 |
|
|
|
650 |
|
|
-- LIFO data output
|
651 |
|
|
lifo_rd_i : in std_logic;
|
652 |
|
|
lifo_dout : out unsigned(WIDTH-1 downto 0);
|
653 |
|
|
|
654 |
|
|
-- FIFO data output
|
655 |
|
|
fifo_rd_i : in std_logic;
|
656 |
|
|
fifo_dout : out unsigned(WIDTH-1 downto 0);
|
657 |
|
|
|
658 |
|
|
-- FIFO/LIFO status
|
659 |
|
|
fifo_fill_level : out unsigned(FILL_LEVEL_BITS-1 downto 0);
|
660 |
|
|
fifo_full : out std_logic;
|
661 |
|
|
fifo_empty : out std_logic;
|
662 |
|
|
fifo_pf_full : out std_logic;
|
663 |
|
|
fifo_pf_flag : out std_logic;
|
664 |
|
|
fifo_pf_empty : out std_logic
|
665 |
|
|
);
|
666 |
|
|
end fifo_lifo;
|
667 |
|
|
|
668 |
|
|
architecture beh of fifo_lifo is
|
669 |
|
|
|
670 |
|
|
-- Constants
|
671 |
|
|
constant FLG_WIDTH : integer := bit_width(DEPTH); -- Bit Width of memory address. Pointers are one bit wider,
|
672 |
|
|
-- so that fill_level can represent the full quantity of
|
673 |
|
|
-- items stored in the FIFO. This is important when DEPTH
|
674 |
|
|
-- is an even power of 2.
|
675 |
|
|
|
676 |
|
|
-- Signal Declarations
|
677 |
|
|
signal rd_row : unsigned(FLG_WIDTH downto 0);
|
678 |
|
|
signal wr_row : unsigned(FLG_WIDTH downto 0);
|
679 |
|
|
signal lf_row : unsigned(FLG_WIDTH downto 0); -- Used for LIFO read operations.
|
680 |
|
|
signal ra_row : unsigned(FLG_WIDTH downto 0); -- Selection between wr_row and lf_row.
|
681 |
|
|
signal fill_level : unsigned(FLG_WIDTH downto 0);
|
682 |
|
|
signal ram_we_a : std_logic;
|
683 |
|
|
signal ram_dout : unsigned(WIDTH-1 downto 0);
|
684 |
|
|
|
685 |
|
|
type STATE_TYPE IS (st_empty, st_data, st_full);
|
686 |
|
|
signal current_state : STATE_TYPE ;
|
687 |
|
|
|
688 |
|
|
signal bram_dat_b : unsigned(WIDTH-1 downto 0);
|
689 |
|
|
|
690 |
|
|
begin
|
691 |
|
|
|
692 |
|
|
fifo_empty <= '1' when (current_state=st_empty) else '0';
|
693 |
|
|
fifo_full <= '1' when (current_state=st_full) else '0';
|
694 |
|
|
fifo_pf_full <= '1' when (fill_level>=PF_FULL_POINT or current_state=st_full) else '0';
|
695 |
|
|
fifo_pf_flag <= '1' when (fill_level>=PF_FLAG_POINT) else '0';
|
696 |
|
|
fifo_pf_empty <= '1' when (fill_level<=PF_EMPTY_POINT and current_state/=st_full) else '0';
|
697 |
|
|
fifo_fill_level <= resize(fill_level,FILL_LEVEL_BITS);
|
698 |
|
|
|
699 |
|
|
-------------------------
|
700 |
|
|
-- The FIFO Fill Level
|
701 |
|
|
fill_level_proc: process(wr_row, rd_row, current_state)
|
702 |
|
|
begin
|
703 |
|
|
if (current_state=st_empty) then
|
704 |
|
|
fill_level <= (others=>'0');
|
705 |
|
|
elsif (wr_row>rd_row) then
|
706 |
|
|
fill_level <= wr_row-rd_row;
|
707 |
|
|
else
|
708 |
|
|
fill_level <= DEPTH+(wr_row-rd_row);
|
709 |
|
|
end if;
|
710 |
|
|
end process;
|
711 |
|
|
|
712 |
|
|
-------------------------
|
713 |
|
|
-- The FIFO memory
|
714 |
|
|
|
715 |
|
|
-- Port A is the write side.
|
716 |
|
|
-- Port B is dedicated to reading only.
|
717 |
|
|
-- The hexfile is used to permit initialization of the RAM
|
718 |
|
|
|
719 |
|
|
fifo_ram : entity work.swiss_army_ram(beh)
|
720 |
|
|
generic map(
|
721 |
|
|
USE_BRAM => USE_BRAM,
|
722 |
|
|
WRITETHRU => 1, -- Set to nonzero value for writethrough mode
|
723 |
|
|
USE_FILE => 0, -- Set to nonzero value to use INIT_FILE
|
724 |
|
|
INIT_VAL => 0,
|
725 |
|
|
INIT_SEL => 0, -- No generate loop here
|
726 |
|
|
INIT_FILE => "foo.txt", -- ASCII hexadecimal init file name (not needed)
|
727 |
|
|
FIL_WIDTH => 32, -- 4x the number of hex digits per line in INIT_FILE
|
728 |
|
|
ADR_WIDTH => FLG_WIDTH,
|
729 |
|
|
DAT_WIDTH => WIDTH
|
730 |
|
|
)
|
731 |
|
|
port map (
|
732 |
|
|
clk_a => sys_clk,
|
733 |
|
|
clk_b => sys_clk,
|
734 |
|
|
|
735 |
|
|
adr_a_i => ra_row(FLG_WIDTH-1 downto 0),
|
736 |
|
|
adr_b_i => rd_row(FLG_WIDTH-1 downto 0),
|
737 |
|
|
|
738 |
|
|
we_a_i => ram_we_a,
|
739 |
|
|
en_a_i => sys_clk_en,
|
740 |
|
|
dat_a_i => fifo_din,
|
741 |
|
|
dat_a_o => lifo_dout,
|
742 |
|
|
|
743 |
|
|
we_b_i => '0',
|
744 |
|
|
en_b_i => sys_clk_en,
|
745 |
|
|
dat_b_i => bram_dat_b,
|
746 |
|
|
dat_b_o => ram_dout
|
747 |
|
|
);
|
748 |
|
|
-- Select the appropriate write address
|
749 |
|
|
-- This was done so that LIFO reads are ready all the time, but FIFO writes
|
750 |
|
|
-- are still accomodated when requested.
|
751 |
|
|
ra_row <= wr_row when fifo_wr_i='1' else lf_row;
|
752 |
|
|
|
753 |
|
|
-- Formulate the lf_row address, which is one less than the wr_row, because
|
754 |
|
|
-- the wr_row points to a "fresh" location with nothing in it, while the
|
755 |
|
|
-- lf_row selects the most recently written data item (the LI part of LIFO.)
|
756 |
|
|
-- When the fifo_lifo is empty, this admittedly sets the lf_row pointing to
|
757 |
|
|
-- the location in RAM which is before the tail pointer, so that a
|
758 |
|
|
-- meaningless data word is output on the bus. The alternative would be to
|
759 |
|
|
-- add logic to output a known constant on the bus instead.
|
760 |
|
|
lf_row <= wr_row-1;
|
761 |
|
|
|
762 |
|
|
|
763 |
|
|
bram_dat_b <= (others=>'0');
|
764 |
|
|
ram_we_a <= '1' when fifo_wr_i='1' and current_state/=st_full else
|
765 |
|
|
'1' when fifo_wr_i='1' and current_state=st_full and fifo_rd_i='1' else
|
766 |
|
|
'1' when fifo_wr_i='1' and current_state=st_full and lifo_rd_i='1' else
|
767 |
|
|
'0';
|
768 |
|
|
fifo_dout <= ram_dout;
|
769 |
|
|
|
770 |
|
|
|
771 |
|
|
-------------------------
|
772 |
|
|
-- The FIFO state machine
|
773 |
|
|
clocked : process(sys_clk, sys_rst_n)
|
774 |
|
|
|
775 |
|
|
procedure do_write is
|
776 |
|
|
begin
|
777 |
|
|
if (wr_row=DEPTH-1) then -- Roll buffer index for non-power-of-two
|
778 |
|
|
wr_row <= (others=>'0');
|
779 |
|
|
else
|
780 |
|
|
wr_row<=wr_row+1;
|
781 |
|
|
end if;
|
782 |
|
|
end do_write;
|
783 |
|
|
|
784 |
|
|
procedure do_read is
|
785 |
|
|
begin
|
786 |
|
|
if (rd_row=DEPTH-1) then -- Roll buffer index for non-power-of-two
|
787 |
|
|
rd_row <= (others=>'0');
|
788 |
|
|
else
|
789 |
|
|
rd_row<=rd_row+1;
|
790 |
|
|
end if;
|
791 |
|
|
end do_read;
|
792 |
|
|
|
793 |
|
|
begin
|
794 |
|
|
if (sys_rst_n = '0') then
|
795 |
|
|
current_state <= st_empty;
|
796 |
|
|
rd_row <= (others=>'0');
|
797 |
|
|
wr_row <= (others=>'0');
|
798 |
|
|
|
799 |
|
|
elsif (sys_clk'EVENT and sys_clk = '1') then
|
800 |
|
|
if (sys_clk_en='1') then
|
801 |
|
|
if (reset_i='1') then
|
802 |
|
|
current_state <= st_empty;
|
803 |
|
|
wr_row <= (others=>'0');
|
804 |
|
|
rd_row <= (others=>'0');
|
805 |
|
|
else
|
806 |
|
|
case current_state is
|
807 |
|
|
|
808 |
|
|
-- When empty, one can only read if also writing
|
809 |
|
|
when st_empty =>
|
810 |
|
|
if (fifo_wr_i='1') then
|
811 |
|
|
if (lifo_rd_i='0' and fifo_rd_i='0') then
|
812 |
|
|
do_write;
|
813 |
|
|
current_state <= st_data;
|
814 |
|
|
elsif (lifo_rd_i='0' and fifo_rd_i='1') then
|
815 |
|
|
do_read;
|
816 |
|
|
do_write;
|
817 |
|
|
elsif (lifo_rd_i='1' and fifo_rd_i='0') then
|
818 |
|
|
-- Here, the wr_row remains unchanged.
|
819 |
|
|
null;
|
820 |
|
|
elsif (lifo_rd_i='1' and fifo_rd_i='1') then
|
821 |
|
|
-- This is a condition in which one of the read requests
|
822 |
|
|
-- must, of necessity, be ignored.
|
823 |
|
|
if (FIFO_RD_FIRST/=0) then
|
824 |
|
|
do_write;
|
825 |
|
|
do_read;
|
826 |
|
|
else
|
827 |
|
|
-- Here, the wr_row remains unchanged.
|
828 |
|
|
null;
|
829 |
|
|
end if;
|
830 |
|
|
end if;
|
831 |
|
|
end if;
|
832 |
|
|
|
833 |
|
|
when st_data =>
|
834 |
|
|
-- As a coding choice, it has been decided to cut here with
|
835 |
|
|
-- the fill level "analytical knife" first and then
|
836 |
|
|
-- fully decode the read combinations as the second
|
837 |
|
|
-- "analytical knife," making the treatment of writing the
|
838 |
|
|
-- third "analytical knife" to be used. Then, the fourth
|
839 |
|
|
-- analytical knife is the treatment of FIFO_RD_FIRST.
|
840 |
|
|
-- The same logic can, of course, also be coded up correctly
|
841 |
|
|
-- by applying the same knives in a different order, do you
|
842 |
|
|
-- know it? BTW, the reference to analytical knives has been
|
843 |
|
|
-- taken from Robert M. Pirsig's book
|
844 |
|
|
-- "Zen and the Art of Motorcycle Maintenance."
|
845 |
|
|
if (fill_level>1) then
|
846 |
|
|
if (lifo_rd_i='0' and fifo_rd_i='0') then
|
847 |
|
|
-- In this case can the full state be reached
|
848 |
|
|
if (fifo_wr_i='1') then
|
849 |
|
|
do_write;
|
850 |
|
|
if (fill_level=DEPTH-1) then
|
851 |
|
|
current_state <= st_full;
|
852 |
|
|
end if;
|
853 |
|
|
end if;
|
854 |
|
|
elsif (lifo_rd_i='0' and fifo_rd_i='1') then
|
855 |
|
|
if (fifo_wr_i='1') then
|
856 |
|
|
do_read;
|
857 |
|
|
do_write;
|
858 |
|
|
else
|
859 |
|
|
do_read;
|
860 |
|
|
end if;
|
861 |
|
|
elsif (lifo_rd_i='1' and fifo_rd_i='0') then
|
862 |
|
|
if (fifo_wr_i='1') then
|
863 |
|
|
null;
|
864 |
|
|
else
|
865 |
|
|
wr_row <= wr_row-1;
|
866 |
|
|
end if;
|
867 |
|
|
elsif (lifo_rd_i='1' and fifo_rd_i='1') then
|
868 |
|
|
if (fifo_wr_i='1') then
|
869 |
|
|
-- Here, the write and both reads get done, and the wr_row
|
870 |
|
|
-- remains unchanged.
|
871 |
|
|
do_read;
|
872 |
|
|
else
|
873 |
|
|
wr_row <= wr_row-1;
|
874 |
|
|
do_read;
|
875 |
|
|
end if;
|
876 |
|
|
end if;
|
877 |
|
|
|
878 |
|
|
elsif (fill_level=1) then
|
879 |
|
|
if (lifo_rd_i='0' and fifo_rd_i='0') then
|
880 |
|
|
if (fifo_wr_i='1') then
|
881 |
|
|
do_write;
|
882 |
|
|
if (fill_level=DEPTH-1) then
|
883 |
|
|
current_state <= st_full;
|
884 |
|
|
end if;
|
885 |
|
|
end if;
|
886 |
|
|
elsif (lifo_rd_i='0' and fifo_rd_i='1') then
|
887 |
|
|
if (fifo_wr_i='1') then
|
888 |
|
|
do_read;
|
889 |
|
|
do_write;
|
890 |
|
|
else
|
891 |
|
|
do_read;
|
892 |
|
|
current_state <= st_empty;
|
893 |
|
|
end if;
|
894 |
|
|
elsif (lifo_rd_i='1' and fifo_rd_i='0') then
|
895 |
|
|
if (fifo_wr_i='1') then
|
896 |
|
|
null;
|
897 |
|
|
else
|
898 |
|
|
wr_row <= wr_row-1;
|
899 |
|
|
current_state <= st_empty;
|
900 |
|
|
end if;
|
901 |
|
|
elsif (lifo_rd_i='1' and fifo_rd_i='1') then
|
902 |
|
|
if (fifo_wr_i='1') then
|
903 |
|
|
-- Here, the write and both reads get done, and the wr_row
|
904 |
|
|
-- remains unchanged.
|
905 |
|
|
do_read;
|
906 |
|
|
current_state <= st_empty;
|
907 |
|
|
else
|
908 |
|
|
-- This is a condition in which one of the read requests
|
909 |
|
|
-- must, of necessity, be ignored.
|
910 |
|
|
if (FIFO_RD_FIRST/=0) then
|
911 |
|
|
do_read;
|
912 |
|
|
current_state <= st_empty;
|
913 |
|
|
else
|
914 |
|
|
wr_row <= wr_row-1;
|
915 |
|
|
current_state <= st_empty;
|
916 |
|
|
end if;
|
917 |
|
|
end if;
|
918 |
|
|
end if;
|
919 |
|
|
end if;
|
920 |
|
|
|
921 |
|
|
-- When full, one can only write if also reading
|
922 |
|
|
when st_full =>
|
923 |
|
|
if (lifo_rd_i='0' and fifo_rd_i='0') then
|
924 |
|
|
null;
|
925 |
|
|
elsif (lifo_rd_i='0' and fifo_rd_i='1') then
|
926 |
|
|
if (fifo_wr_i='1') then
|
927 |
|
|
do_read;
|
928 |
|
|
do_write;
|
929 |
|
|
else
|
930 |
|
|
do_read;
|
931 |
|
|
current_state <= st_data;
|
932 |
|
|
end if;
|
933 |
|
|
elsif (lifo_rd_i='1' and fifo_rd_i='0') then
|
934 |
|
|
-- Here, wr_row remains unchanged.
|
935 |
|
|
-- Other logic makes the write happen, however.
|
936 |
|
|
null;
|
937 |
|
|
elsif (lifo_rd_i='1' and fifo_rd_i='1') then
|
938 |
|
|
wr_row <= wr_row-1;
|
939 |
|
|
do_read;
|
940 |
|
|
current_state <= st_data;
|
941 |
|
|
end if;
|
942 |
|
|
|
943 |
|
|
when others => null;
|
944 |
|
|
end case;
|
945 |
|
|
|
946 |
|
|
end if;
|
947 |
|
|
end if; -- sys_clk_en
|
948 |
|
|
end if; -- sys_clk
|
949 |
|
|
end process clocked;
|
950 |
|
|
|
951 |
|
|
|
952 |
|
|
end beh;
|
953 |
|
|
|