OpenCores
URL https://opencores.org/ocsvn/pairing/pairing/trunk

Subversion Repositories pairing

[/] [pairing/] [trunk/] [rtl/] [f33m.v] - Blame information for rev 8

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 homer.xing 
`include "inc.v"
2 
 
3 8 homer.xing 
// out = (v1 & l1) | (v2 & l2)
4 
module f33m_mux2(v1, l1, v2, l2, out);
5 
    input [`W3:0] v1, v2;
6 
    input l1, l2;
7 
    output [`W3:0] out;
8 
    genvar i;
9 
    generate
10 
        for(i=0;i<=`W3;i=i+1)
11 
          begin : label
12 
            assign out[i] = (v1[i] & l1) | (v2[i] & l2);
13 
          end
14 
    endgenerate
15 
endmodule
16 
 
17 
// out = (v1 & l1) | (v2 & l2) | (v3 & l3)
18 
module f33m_mux3(v1, l1, v2, l2, v3, l3, out);
19 
    input [`W3:0] v1, v2, v3;
20 
    input l1, l2, l3;
21 
    output [`W3:0] out;
22 
    genvar i;
23 
    generate
24 
        for(i=0;i<=`W3;i=i+1)
25 
          begin : label
26 
            assign out[i] = (v1[i] & l1) | (v2[i] & l2) | (v3[i] & l3);
27 
          end
28 
    endgenerate
29 
endmodule
30 
 
31 3 homer.xing 
// c == a+b in GF(3^{3*M})
32 
module f33m_add(a, b, c);
33 
    input [`W3:0] a,b;
34 
    output [`W3:0] c;
35 
    wire [`WIDTH:0] a0,a1,a2,b0,b1,b2,c0,c1,c2;
36 
    assign {a2,a1,a0} = a;
37 
    assign {b2,b1,b0} = b;
38 
    assign c = {c2,c1,c0};
39 
    f3m_add
40 
        ins1 (a0,b0,c0),
41 
        ins2 (a1,b1,c1),
42 
        ins3 (a2,b2,c2);
43 
endmodule
44 
 
45 8 homer.xing 
// c == -a in GF(3^{3*M})
46 
module f33m_neg(a, c);
47 
    input [`W3:0] a;
48 3 homer.xing 
    output [`W3:0] c;
49 8 homer.xing 
    wire [`WIDTH:0] a0,a1,a2,c0,c1,c2;
50 3 homer.xing 
    assign {a2,a1,a0} = a;
51 
    assign c = {c2,c1,c0};
52 8 homer.xing 
    f3m_neg
53 
        ins1 (a0,c0),
54 
        ins2 (a1,c1),
55 
        ins3 (a2,c2);
56 3 homer.xing 
endmodule
57 
 
58 
// c == a*b in GF(3^{3*M})
59 
module f33m_mult(clk, reset, a, b, c, done);
60 
    input clk, reset;
61 
    input [`W3:0] a, b;
62 
    output reg [`W3:0] c;
63 
    output reg done;
64 
 
65 
    reg [`WIDTH:0] x0, x1, x2, x3, x4, x5;
66 
    wire [`WIDTH:0]  a0, a1, a2,
67 
                     b0, b1, b2,
68 
                     c0, c1, c2,
69 
                     v1, v2, v3, v4, v5, v6,
70 
                     nx0, nx2, nx5,
71 
                     d0, d1, d2, d3, d4;
72 
    reg [6:0] K;
73 
    wire e0, e1, e2,
74 
         e3, e4, e5,
75 
         mult_done, p, rst;
76 
    wire [`WIDTH:0] in0, in1;
77 
    wire [`WIDTH:0] o;
78 
    reg mult_reset, delay1, delay2;
79 
 
80 
    assign {e0,e1,e2,e3,e4,e5} = K[6:1];
81 
    assign {a2,a1,a0} = a;
82 
    assign {b2,b1,b0} = b;
83 
    assign d4 = x0;
84 
    assign d0 = x5;
85 
    assign rst = delay2;
86 
 
87 
    f3m_mux6
88 
        ins1 (a2,v1,a1,v3,v5,a0,e0,e1,e2,e3,e4,e5,in0), // $in0$ is the first input
89 
        ins2 (b2,v2,b1,v4,v6,b0,e0,e1,e2,e3,e4,e5,in1); // $in1$ is the second input
90 
    f3m_mult
91 
        ins3 (clk, mult_reset, in0, in1, o, mult_done); // o == in0 * in1
92 
    func6
93 8 homer.xing 
        ins4 (clk, reset, mult_done, p);
94 3 homer.xing 
    f3m_add
95 
        ins5 (a1, a2, v1), // v1 == a1+a2
96 
        ins6 (b1, b2, v2), // v2 == b1+b2
97 
        ins7 (a0, a2, v3), // v3 == a0+a2
98 
        ins8 (b0, b2, v4), // v4 == b0+b2
99 
        ins9 (a0, a1, v5), // v5 == a0+a1
100 
        ins10 (b0, b1, v6), // v6 == b0+b1
101 
        ins11 (d0, d3, c0), // c0 == d0+d3
102 
        ins12 (d2, d4, c2); // c2 == d2+d4
103 
    f3m_neg
104 
        ins13 (x0, nx0), // nx0 == -x0
105 
        ins14 (x2, nx2), // nx2 == -x2
106 
        ins15 (x5, nx5); // nx5 == -x5
107 
    f3m_add3
108 
        ins16 (x1, nx0, nx2, d3), // d3 == x1-x0-x2
109 
        ins17 (x4, nx2, nx5, d1), // d1 == x4-x2-x5
110 
        ins18 (d1, d3, d4, c1); // c1 == d1+d3+d4
111 
    f3m_add4
112 
        ins19 (x3, x2, nx0, nx5, d2); // d2 == x3+x2-x0-x5
113 
 
114 
    always @ (posedge clk)
115 
      begin
116 
        if (reset) K <= 7'b1000000;
117 8 homer.xing 
        else if (p|K[0]) K <= {1'b0,K[6:1]};
118 3 homer.xing 
      end
119 
 
120 
    always @ (posedge clk)
121 
      begin
122 
        if (e0) x0 <= o; // x0 == a2*b2
123 
        if (e1) x1 <= o; // x1 == (a2+a1)*(b2+b1)
124 
        if (e2) x2 <= o; // x2 == a1*b1
125 
        if (e3) x3 <= o; // x3 == (a2+a0)*(b2+b0)
126 
        if (e4) x4 <= o; // x4 == (a1+a0)*(b1+b0)
127 
        if (e5) x5 <= o; // x5 == a0*b0
128 
      end
129 
 
130 
    always @ (posedge clk)
131 
      begin
132 
        if (reset) done <= 0;
133 
        else if (K[0])
134 
          begin
135 
            done <= 1; c <= {c2,c1,c0};
136 
          end
137 
      end
138 
 
139 
    always @ (posedge clk)
140 
      begin
141 
        if (rst) mult_reset <= 1;
142 
        else if (mult_done) mult_reset <= 1;
143 
        else mult_reset <= 0;
144 
      end
145 
 
146 
    always @ (posedge clk)
147 
      begin
148 
        delay2 <= delay1; delay1 <= reset;
149 
      end
150 
endmodule
151 
 
152 8 homer.xing 
// c0 == a0*b0; c1 == a1*b1; c2 == a2*b2; all in GF(3^{3*M})
153 
module f33m_mult3(clk, reset,
154 
                 a0, b0, c0,
155 
                 a1, b1, c1,
156 
                 a2, b2, c2,
157 
                 done);
158 
    input clk, reset;
159 
    input [`W3:0] a0, b0, a1, b1, a2, b2;
160 
    output reg [`W3:0] c0, c1, c2;
161 
    output reg done;
162 
    reg [3:0] K;
163 
    reg mult_reset, delay1, delay2;
164 
    wire e1, e2, e3, mult_done, delay3, rst;
165 
    wire [`W3:0] in1, in2, o;
166 
 
167 
    assign rst = delay2;
168 
    assign {e1,e2,e3} = K[3:1];
169 
 
170 
    f33m_mux3
171 
        ins9 (a0, e1, a1, e2, a2, e3, in1),
172 
        ins10 (b0, e1, b1, e2, b2, e3, in2);
173 
    f33m_mult
174 
        ins11 (clk, mult_reset, in1, in2, o, mult_done); // o == in1 * in2
175 
    func6
176 
        ins12 (clk, reset, mult_done, delay3);
177 
 
178 
    always @ (posedge clk)
179 
      begin
180 
        if (e1) c0 <= o;
181 
        if (e2) c1 <= o;
182 
        if (e3) c2 <= o;
183 
      end
184 
 
185 
    always @ (posedge clk)
186 
        if (reset) K <= 4'b1000;
187 
        else if (delay3|K[0]) K <= {1'b0,K[3:1]};
188 
 
189 
    always @ (posedge clk)
190 
      begin
191 
        if (rst) mult_reset <= 1;
192 
        else if (mult_done) mult_reset <= 1;
193 
        else mult_reset <= 0;
194 
      end
195 
 
196 
    always @ (posedge clk)
197 
        if (reset)     done <= 0;
198 
        else if (K[0]) done <= 1;
199 
 
200 
    always @ (posedge clk)
201 
      begin
202 
        delay2 <= delay1; delay1 <= reset;
203 
      end
204 
endmodule
205 
 
206 
// c0 == a0*b0; c1 == a1*b1; both in GF(3^{3*M})
207 
module f33m_mult2(clk, reset,
208 
                 a0, b0, c0,
209 
                 a1, b1, c1,
210 
                 done);
211 
    input clk, reset;
212 
    input [`W3:0] a0, b0, a1, b1;
213 
    output reg [`W3:0] c0, c1;
214 
    output reg done;
215 
    reg [2:0] K;
216 
    reg mult_reset, delay1, delay2;
217 
    wire e1, e2, mult_done, delay3, rst;
218 
    wire [`W3:0] in1, in2, o;
219 
 
220 
    assign rst = delay2;
221 
    assign {e1,e2} = K[2:1];
222 
 
223 
    f33m_mux2
224 
        ins9 (a0, e1, a1, e2, in1),
225 
        ins10 (b0, e1, b1, e2, in2);
226 
    f33m_mult
227 
        ins11 (clk, mult_reset, in1, in2, o, mult_done); // o == in1 * in2
228 
    func6
229 
        ins12 (clk, reset, mult_done, delay3);
230 
 
231 
    always @ (posedge clk)
232 
      begin
233 
        if (e1) c0 <= o;
234 
        if (e2) c1 <= o;
235 
      end
236 
 
237 
    always @ (posedge clk)
238 
        if (reset) K <= 3'b100;
239 
        else if (delay3|K[0]) K <= {1'b0,K[2:1]};
240 
 
241 
    always @ (posedge clk)
242 
      begin
243 
        if (rst) mult_reset <= 1;
244 
        else if (mult_done) mult_reset <= 1;
245 
        else mult_reset <= 0;
246 
      end
247 
 
248 
    always @ (posedge clk)
249 
        if (reset)     done <= 0;
250 
        else if (K[0]) done <= 1;
251 
 
252 
    always @ (posedge clk)
253 
      begin
254 
        delay2 <= delay1; delay1 <= reset;
255 
      end
256 
endmodule
257 
 
258 6 homer.xing 
// c == a^{-1} in GF(3^{3*M})
259 7 homer.xing 
module f33m_inv(clk, reset, a, c, done);
260 
    input clk, reset;
261 
    input [`W3:0] a;
262 
    output reg [`W3:0] c;
263 
    output reg done;
264 
 
265 
    wire [`WIDTH:0] a0, a1, a2,
266 
                    c0, c1, c2,
267 
                    v0, v1, v2, v3, v4, v5,
268 
                    v6, v7, v8, v9, v10, v11,
269 
                    v12, v13, v14, v15, v16,
270 
                    v17, nv2, nv11, nv14;
271 
    wire rst1, rst2, rst3, rst4,
272 
         done1, done2, done3, done4,
273 
         dummy;
274 
    reg [4:0] K;
275 
 
276 
    assign {a2, a1, a0} = a;
277 
    assign rst1 = reset;
278 
 
279 
    f3m_mult3
280 
        ins1 (clk, rst1,
281 
              a0, a0, v0, // v0 == a0^2
282 
              a1, a1, v1, // v1 == a1^2
283 
              a2, a2, v2, // v2 == a2^2
284 
              done1),
285 
        ins2 (clk, rst2,
286 
              v0, v3, v6,  // v6 == (a0-a2)*(a0^2)
287 
              v1, v4, v7,  // v7 == (a1-a0)*(a1^2)
288 
              v2, v5, v8,  // v8 == (a0-a1+a2)*(a2^2)
289 
              done2),
290 
        ins3 (clk, rst1,
291 
              a0, a2, v11, // v11 == a0*a2
292 
              a0, a1, v12, // v12 == a0*a1
293 
              a1, a2, v13, // v13 == a1*a2
294 
              dummy),
295 
        ins4 (clk, rst4,
296 
              v10, v15, c0,
297 
              v10, v16, c1,
298 
              v10, v17, c2,
299 
              done4);
300 
    f3m_sub
301 
        ins5 (a0, a2, v3), // v3 == a0-a2
302 
        ins6 (a1, a0, v4), // v4 == a1-a0
303 
        ins7 (a2, v4, v5); // v5 == a2-v4 == a0-a1+a2
304 
    f3m_add3
305 
        ins8 (v6, v7, v8, v9),    // v9 == v6+v7+v8
306 
        ins9 (v11, v1, v13, v14), // v14 == v11+v1+v13
307 
        ins10 (nv14, v0, v2, v15),  // v15 == v0+v2-(v11+v1+v13)
308 
        ins11 (v1, nv2, nv11, v17); // v17 == a1^2-a0*a2-a2^2
309 
    f3m_neg
310 
        ins12 (v2,  nv2),  // nv2 == -v2
311 
        ins13 (v11, nv11), // nv11 == -v11
312 
        ins14 (v14, nv14); // nv14 == -v14 == -(v11+v1+v13)
313 
    f3m_sub
314 
        ins15 (v2, v12, v16); // v16 == a2^2-a0*a1
315 
    f3m_inv
316 
        ins16 (clk, rst3, v9, v10, done3); // v10 == v9^(-1)
317 
    func6
318 8 homer.xing 
        ins17 (clk, reset, done1, rst2),
319 
        ins18 (clk, reset, done2, rst3),
320 
        ins19 (clk, reset, done3, rst4);
321 7 homer.xing 
 
322 
    always @ (posedge clk)
323 
        if (reset) K <= 5'h10;
324 8 homer.xing 
        else if ((K[4]&rst2)|(K[3]&rst3)|(K[2]&rst4)|(K[1]&done4)|K[0])
325 7 homer.xing 
            K <= K >> 1;
326 
 
327 
    always @ (posedge clk)
328 
        if (reset) done <= 0;
329 
        else if (K[0])
330 
          begin
331 
            done <= 1; c <= {c2,c1,c0};
332 
          end
333 
endmodule
334 8 homer.xing 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.