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[/] [pairing/] [trunk/] [rtl/] [f36m.v] - Blame information for rev 10

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Line No. Rev Author Line
1 2 homer.xing 
`include "inc.v"
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3 
// c == a*b in GF(3^{6M})
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module f36m_mult(clk, reset, a, b, c, done);
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    input clk, reset;
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    input [`W6:0] a, b;
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    output reg [`W6:0] c;
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    output reg done;
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    reg [`W2:0] x0, x1, x2, x3, x4, x5;
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    wire [`W2:0] a0, a1, a2,
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                 b0, b1, b2,
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                 c0, c1, c2,
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                 v1, v2, v3, v4, v5, v6,
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                 nx0, nx2, nx5,
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                 d0, d1, d2, d3, d4;
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    reg [6:0] K;
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    wire e0, e1, e2,
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         e3, e4, e5,
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         mult_done, p, rst;
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    wire [`W2:0] in0, in1;
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    wire [`W2:0] o;
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    reg mult_reset, delay1, delay2;
24 10 homer.xing 
    reg [`W2:0] in0d,in1d;
25 2 homer.xing 
 
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    assign {e0,e1,e2,e3,e4,e5} = K[6:1];
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    assign {a2,a1,a0} = a;
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    assign {b2,b1,b0} = b;
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    assign d4 = x0;
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    assign d0 = x5;
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    assign rst = delay2;
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33 3 homer.xing 
    f32m_mux6
34 2 homer.xing 
        ins1 (a2,v1,a1,v3,v5,a0,e0,e1,e2,e3,e4,e5,in0), // $in0$ is the first input
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        ins2 (b2,v2,b1,v4,v6,b0,e0,e1,e2,e3,e4,e5,in1); // $in1$ is the second input
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    f32m_mult
37 10 homer.xing 
        ins3 (clk, mult_reset, in0d, in1d, o, mult_done); // o == in0 * in1
38 2 homer.xing 
    func6
39 8 homer.xing 
        ins4 (clk, reset, mult_done, p);
40 2 homer.xing 
    f32m_add
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        ins5 (a1, a2, v1), // v1 == a1+a2
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        ins6 (b1, b2, v2), // v2 == b1+b2
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        ins7 (a0, a2, v3), // v3 == a0+a2
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        ins8 (b0, b2, v4), // v4 == b0+b2
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        ins9 (a0, a1, v5), // v5 == a0+a1
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        ins10 (b0, b1, v6), // v6 == b0+b1
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        ins11 (d0, d3, c0), // c0 == d0+d3
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        ins12 (d2, d4, c2); // c2 == d2+d4
49 3 homer.xing 
    f32m_neg
50 2 homer.xing 
        ins13 (x0, nx0), // nx0 == -x0
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        ins14 (x2, nx2), // nx2 == -x2
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        ins15 (x5, nx5); // nx5 == -x5
53 3 homer.xing 
    f32m_add3
54 2 homer.xing 
        ins16 (x1, nx0, nx2, d3), // d3 == x1-x0-x2
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        ins17 (x4, nx2, nx5, d1), // d1 == x4-x2-x5
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        ins18 (d1, d3, d4, c1); // c1 == d1+d3+d4
57 3 homer.xing 
    f32m_add4
58 2 homer.xing 
        ins19 (x3, x2, nx0, nx5, d2); // d2 == x3+x2-x0-x5
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    always @ (posedge clk)
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      begin
62 10 homer.xing 
        in0d <= in0; in1d <= in1;
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      end
64 
 
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    always @ (posedge clk)
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      begin
67 2 homer.xing 
        if (reset) K <= 7'b1000000;
68 8 homer.xing 
        else if (p | K[0]) K <= {1'b0,K[6:1]};
69 2 homer.xing 
      end
70 
 
71 
    always @ (posedge clk)
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      begin
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        if (e0) x0 <= o; // x0 == a2*b2
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        if (e1) x1 <= o; // x1 == (a2+a1)*(b2+b1)
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        if (e2) x2 <= o; // x2 == a1*b1
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        if (e3) x3 <= o; // x3 == (a2+a0)*(b2+b0)
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        if (e4) x4 <= o; // x4 == (a1+a0)*(b1+b0)
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        if (e5) x5 <= o; // x5 == a0*b0
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      end
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    always @ (posedge clk)
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      begin
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        if (reset) done <= 0;
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        else if (K[0])
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          begin
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            done <= 1; c <= {c2,c1,c0};
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          end
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      end
89 
 
90 
    always @ (posedge clk)
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      begin
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        if (rst) mult_reset <= 1;
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        else if (mult_done) mult_reset <= 1;
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        else mult_reset <= 0;
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      end
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97 
    always @ (posedge clk)
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      begin
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        delay2 <= delay1; delay1 <= reset;
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      end
101 
endmodule
102 
 
103 
// c == a^3 in GF(3^{6M})
104 
module f36m_cubic(clk, a, c);
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    input clk;
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    input [`W6:0] a;
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    output reg [`W6:0] c;
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    wire [`W2:0] a0,a1,a2,v0,v1,v2,v3,c0,c1,c2;
109 
 
110 
    assign {a2,a1,a0} = a;
111 
    assign c2 = v2; // c2 == a2^3
112 
 
113 
    f32m_cubic
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        ins1 (clk, a0, v0), // v0 == a0^3
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        ins2 (clk, a1, v1), // v0 == a1^3
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        ins3 (clk, a2, v2); // v0 == a2^3
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    f32m_add
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        ins4 (v0, v1, v3), // v3 == v0+v1 = a0^3 + a1^3
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        ins5 (v2, v3, c0); // c0 == a0^3 + a1^3 + a2^3
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    f32m_sub
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        ins6 (v1, v2, c1); // c1 == a1^3 - a2^3
122 
 
123 
    always @ (posedge clk)
124 
        c <= {c2,c1,c0};
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endmodule
126 8 homer.xing 
 
127 
// c == a ^ { 3^{3*M} - 1 } in GF(3^{6M})
128 
module second_part(clk, reset, a, c, done);
129 
    input clk, reset;
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    input [`W6:0] a;
131 
    output reg [`W6:0] c;
132 
    output reg done;
133 
 
134 
    reg [3:0] K;
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    wire [`WIDTH:0] d0,d1,d2,d3,d4,d5,
136 
                    c0,c1,c2,c3,c4,c5;
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    wire [`W3:0] a0,a1,b0,b1,
138 
                 v1,v2,v3,v4,v5,v6,v7,v8,nv6;
139 
    wire [1:0] v9,v10;
140 
    wire rst1, rst2, rst3, done1, done2, done3;
141 
 
142 
    assign {d5,d4,d3,d2,d1,d0} = a;
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    assign {a1,a0} = {d5,d3,d1,d4,d2,d0}; // change basis
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    assign {b1,b0} = {{v8[`W3:2],v10}, {v7[`W3:2],v9}};
145 
    assign {c5,c3,c1,c4,c2,c0} = {b1,b0}; // change basis back
146 
    assign rst1 = reset;
147 
 
148 
    f33m_mult2
149 
        ins1 (clk, rst1,
150 
              a0, a0, v1, // v1 == a0^2
151 
              a1, a1, v2, // v2 == a1^2
152 
              done1);
153 
    f33m_add
154 
        ins2 (v1, v2, v3), // v3 == v1+v2 == a0^2+a1^2
155 
        ins3 (a0, a1, v5); // v5 == a0+a1
156 
    f33m_inv
157 
        ins4 (clk, rst2, v3, v4, done2); // v4 == v3^{-1} == (a0^2+a1^2)^{-1}
158 
    f33m_neg
159 
        ins5 (v6, nv6); // nv6 == -v6 == -(a0+a1)^2
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    f33m_mult3 // ****** $v8$ depends on $v6$ ******
161 
        ins6 (clk, rst3,
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              v5, v5, v6, // v6 == v5^2 == (a0+a1)^2
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              v2, v4, v7, // v7 == v2*v4 == (a1^2)*{(a0^2+a1^2)^{-1}}
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              nv6, v4, v8, // v8 == -v6*v4
165 
              done3);
166 
    f3_add1
167 
        ins7 (v7[1:0], v9), // v9 == v7[1:0]+1
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        ins8 (v8[1:0], v10); // v10 == v8[1:0]+1
169 
    func6
170 
        ins9  (clk, reset, done1, rst2),
171 
        ins10 (clk, reset, done2, rst3);
172 
 
173 
    always @ (posedge clk)
174 
        if (reset) K <= 4'b1000;
175 
        else if ((K[3]&rst2)|(K[2]&rst3)|(K[1]&done3)|K[0])
176 
            K <= K >> 1;
177 
 
178 
    always @ (posedge clk)
179 
        if (reset) done <= 0;
180 
        else if (K[0])
181 
          begin
182 
            done <= 1; c <= {c5,c4,c3,c2,c1,c0};
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          end
184 
endmodule

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