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doru |
-- <File header>
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-- Project
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-- pAVR (pipelined AVR) is an 8 bit RISC controller, compatible with Atmel's
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-- AVR core, but about 3x faster in terms of both clock frequency and MIPS.
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-- The increase in speed comes from a relatively deep pipeline. The original
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-- AVR core has only two pipeline stages (fetch and execute), while pAVR has
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-- 6 pipeline stages:
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-- 1. PM (read Program Memory)
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-- 2. INSTR (load Instruction)
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-- 3. RFRD (decode Instruction and read Register File)
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-- 4. OPS (load Operands)
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-- 5. ALU (execute ALU opcode or access Unified Memory)
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-- 6. RFWR (write Register File)
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-- Version
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-- 0.32
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-- Date
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-- 2002 August 07
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-- Author
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-- Doru Cuturela, doruu@yahoo.com
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-- License
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-- </File header>
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-- <File info>
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-- This tests the utilities defined in `std_util.vhd':
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-- - cmp_std_logic_vector (asynchronous function)
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-- - sign_extend (asynchronous function)
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-- - zero_extend (asynchronous function)
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-- </File info>
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-- <File body>
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library ieee;
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use ieee.std_logic_1164.all;
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library work;
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use work.std_util.all;
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entity test_std_util is
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end;
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architecture arch_test_std_util of test_std_util is
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signal clk: std_logic;
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-- Comparision output
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signal flag1: std_logic;
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-- Candidates to sign/zero extension and comparision
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signal v2_1, v2_2, v2_3: std_logic_vector( 1 downto 0);
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signal v50_1, v50_2, v50_3: std_logic_vector(49 downto 0);
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begin
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generate_clock:
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process
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begin
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clk <= '1';
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wait for 50 ns;
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clk <= '0';
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wait for 50 ns;
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end process generate_clock;
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test_main:
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process
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begin
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-- Set up default inputs.
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v2_1 <= "10";
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v2_2 <= "01";
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for i in 0 to 49 loop
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v50_1(i) <= '0';
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v50_2(i) <= '0';
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end loop;
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v50_1(49) <= '1';
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v50_1(3 downto 0) <= "1001";
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v50_2(3 downto 0) <= "1010";
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wait for 110 ns;
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-- TEST 1
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-- Test function `cmp_std_logic_vector'
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-- Try to compare 2 vectors with different lengths; this should assert the dedicated error.
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--flag1 <= cmp_std_logic_vector(v2_1, v50_1);
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--wait until clk'event and clk='1';
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-- Typical situations
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-- Shouldn't match
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flag1 <= cmp_std_logic_vector(v50_1, v50_2);
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wait until clk'event and clk='1';
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-- Should match
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flag1 <= cmp_std_logic_vector(v50_1, v50_1);
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wait until clk'event and clk='1';
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-- Shouldn't match
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flag1 <= cmp_std_logic_vector(sign_extend(v2_1, v50_1'length), zero_extend(v2_1, v50_1'length));
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wait until clk'event and clk='1';
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-- Should match
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flag1 <= cmp_std_logic_vector(sign_extend(v2_2, v50_1'length), zero_extend(v2_2, v50_1'length));
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wait until clk'event and clk='1';
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-- TEST 2
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-- Test function `sign_extend' and `zero_extend', negative input.
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-- Extremal case that should work. For length 2, typical case = extremal case.
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v2_3 <= sign_extend(v2_1, v2_3'length);
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wait until clk'event and clk='1';
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v2_3 <= zero_extend(v2_1, v2_3'length);
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wait until clk'event and clk='1';
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-- Some stupid length that should generate an error
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--v2_3 <= sign_extend(v2_1, 7);
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--wait until clk'event and clk='1';
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--v2_3 <= zero_extend(v2_1, 7);
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--wait until clk'event and clk='1';
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-- The same with width 50
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-- Typical case
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v50_3 <= sign_extend(v2_1, v50_3'length);
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wait until clk'event and clk='1';
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v50_3 <= zero_extend(v2_1, v50_3'length);
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wait until clk'event and clk='1';
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-- Extremal case that should work
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v50_3 <= sign_extend(v50_1, v50_3'length);
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wait until clk'event and clk='1';
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v50_3 <= zero_extend(v50_1, v50_3'length);
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wait until clk'event and clk='1';
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-- Some stupid length that should generate an error
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--v50_3 <= sign_extend(v50_1, 7);
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--wait until clk'event and clk='1';
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--v50_3 <= zero_extend(v50_1, 7);
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--wait until clk'event and clk='1';
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-- TEST 1
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-- Test function `sign_extend' and `zero_extend', positive input.
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-- Extremal case that should work. For length 2, typical case = extremal case.
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v2_3 <= sign_extend(v2_2, v2_3'length);
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wait until clk'event and clk='1';
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v2_3 <= zero_extend(v2_2, v2_3'length);
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wait until clk'event and clk='1';
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-- Some stupid length that should generate an error
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--v2_3 <= sign_extend(v2_2, 7);
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--wait until clk'event and clk='1';
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--v2_3 <= zero_extend(v2_2, 7);
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--wait until clk'event and clk='1';
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-- The same with width 50
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-- Typical case
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v50_3 <= sign_extend(v2_2, v50_3'length);
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wait until clk'event and clk='1';
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v50_3 <= zero_extend(v2_2, v50_3'length);
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wait until clk'event and clk='1';
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-- Extremal case that should work
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v50_3 <= sign_extend(v50_2, v50_3'length);
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wait until clk'event and clk='1';
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v50_3 <= zero_extend(v50_2, v50_3'length);
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wait until clk'event and clk='1';
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-- Some stupid length that should generate an error
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--v50_3 <= sign_extend(v50_2, 7);
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--wait until clk'event and clk='1';
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--v50_3 <= zero_extend(v50_2, 7);
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--wait until clk'event and clk='1';
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end process test_main;
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end;
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-- </File body>
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