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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
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<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
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<title>Todo List</title>
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<link href="doxygen.css" rel="stylesheet" type="text/css">
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<!-- Generated by Doxygen 1.2.16 -->
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<center>
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<a class="qindex" href="main.html">Main Page</a> <a class="qindex" href="modules.html">Modules</a> <a class="qindex" href="pages.html">Related Pages</a> </center>
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<hr><a name="todo"><h2>Todo List</h2></a>
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<dl compact>
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<dt><a name="_todo000001"></a>Group <a class="el" href="group__pavr__avrarch.html">pavr_avrarch</a> <dd>Add some AVR kernel schematics. <br>
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Add some AVR general considerations.
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</dl>
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<p>
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<dl compact>
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<dt><a name="_todo000002"></a>Group <a class="el" href="group__pavr__control.html">pavr_control</a> <dd><ul>
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<li> Branch prediction with hashed branch prediction table and 2 bit predictor. <li> Super-RAM interfacing to Program Memory. <br>
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A super-RAM is a classic RAM with two supplemental lines: a mem_rq input and a mem_ack output. The device that writes/reads the super-RAM knows that it can place an access request when the memory signalizes it's ready via mem_ack. Only then, it can place an access request via mem_rq. <br>
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A super-RAM is a super-class for classic RAM. That is, a super-RAM becomes classic RAM if the RAM ignores mem_rq and keeps continousely mem_ack to 1. <br>
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The super-RAM protocol is so flexible that, as an extreme example, it can serially (!) interface the Program Memory to the controller. That is, about 2-3 wires instead of 38 wires, without needing to modify anything in the controller. Of course, that would come with a very large speed penalty, but it allows choosing the most advantageous compromise between the number of wires and speed. The only thing to be done is to add a serial to parallel converter, that complies to the super-RAM protocol. <br>
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After pAVR is made super-RAM compatible, it can run anyway from a regular RAM, as it runs now, by ignoring the two extra lines. Thus, nothing is removed, it's only added. No speed penalty should be payed. <br>
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A simple way to add the super-RAM interface is to force nops into the pipeline as long as the serial-to-parallel converter works on an instruction word. <br>
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<li> Modify stall handling so that no nops are required <b>after</b> the instruction wavefront. The instructions could take care of themselves. The idea is that a request to a hardware resource that is already in use by an older instruction, could <b>automatically</b> generate a stall. <br>
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That would: <ul>
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<li> generally simplify instruction handling <li> make average instruction execution slightly faster. </ul>
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</ul>
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</dl>
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<p>
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<dl compact>
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<dt><a name="_todo000003"></a>Group <a class="el" href="group__pavr__src.html">pavr_src</a> <dd>Replace `next_...' signals family with a (pretty wide) state decoder.
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</dl>
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<hr><address align="right"><small>Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by
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<a href="http://www.doxygen.org/index.html">
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<img src="doxygen.png" alt="doxygen" align="middle" border=0
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width=110 height=53></a>1.2.16 </small></address>
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