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1 4 doru
-- <File header>
2
-- Project
3
--    pAVR (pipelined AVR) is an 8 bit RISC controller, compatible with Atmel's
4
--    AVR core, but about 3x faster in terms of both clock frequency and MIPS.
5
--    The increase in speed comes from a relatively deep pipeline. The original
6
--    AVR core has only two pipeline stages (fetch and execute), while pAVR has
7
--    6 pipeline stages:
8
--       1. PM    (read Program Memory)
9
--       2. INSTR (load Instruction)
10
--       3. RFRD  (decode Instruction and read Register File)
11
--       4. OPS   (load Operands)
12
--       5. ALU   (execute ALU opcode or access Unified Memory)
13
--       6. RFWR  (write Register File)
14
-- Version
15
--    0.32
16
-- Date
17
--    2002 August 07
18
-- Author
19
--    Doru Cuturela, doruu@yahoo.com
20
-- License
21
--    This program is free software; you can redistribute it and/or modify
22
--    it under the terms of the GNU General Public License as published by
23
--    the Free Software Foundation; either version 2 of the License, or
24
--    (at your option) any later version.
25
--    This program is distributed in the hope that it will be useful,
26
--    but WITHOUT ANY WARRANTY; without even the implied warranty of
27
--    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
28
--    GNU General Public License for more details.
29
--    You should have received a copy of the GNU General Public License
30
--    along with this program; if not, write to the Free Software
31
--    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
32
-- </File header>
33
 
34
 
35
 
36
-- <File info>
37
-- This defines pAVR's IO File.
38
-- The IO File is composed of a set of discrete registers, that are grouped
39
--    in a memory-like entity. The IO File has a general write/read port that is
40
--    byte-oriented, and separate read and write ports for each register in the
41
--    IO File.
42
-- The general IO File port is a little bit more elaborated than a simple
43
--    read/write port. It can read bytes from IO registers to output and write
44
--    bytes from input to IO registers. Also, it can do some bit processing: load
45
--    bits (from SREG to output), store bits (from input to SREG), set IO bits,
46
--    clear IO bits. Bit loading/storing is done through the T bit in SREG.
47
--    An opcode has to be provided to specify one of the actions that this port
48
--    is capable of. The following opcodes are implemented for the IO File general
49
--    port:
50
--    - read byte (needed by instructions IN, SBIC, SBIS)
51
--    - write byte (OUT)
52
--    - clear bit (CBI)
53
--    - set bit (SBI)
54
--    - load bit (BLD)
55
--    - store bit (BST)
56
-- </File info>
57
 
58
 
59
 
60
-- <File body>
61
library work;
62
use work.std_util.all;
63
use work.pavr_util.all;
64
use work.pavr_constants.all;
65
library IEEE;
66
use IEEE.std_logic_1164.all;
67
 
68
 
69
 
70
entity pavr_iof is
71
   port(
72
      pavr_iof_clk      : in std_logic;
73
      pavr_iof_res      : in std_logic;
74
      pavr_iof_syncres  : in std_logic;
75
 
76
      -- General IO file port
77
      pavr_iof_opcode   : in  std_logic_vector(pavr_iof_opcode_w - 1 downto 0);
78
      pavr_iof_addr     : in  std_logic_vector(5 downto 0);
79
      pavr_iof_di       : in  std_logic_vector(7 downto 0);
80
      pavr_iof_do       : out std_logic_vector(7 downto 0);
81
      pavr_iof_bitout   : out std_logic;
82
      pavr_iof_bitaddr  : in  std_logic_vector(2 downto 0);
83
 
84
      -- AVR kernel register ports
85
      -- Status register (SREG)
86
      pavr_iof_sreg     : out std_logic_vector(7 downto 0);
87
      pavr_iof_sreg_wr  : in  std_logic;
88
      pavr_iof_sreg_di  : in  std_logic_vector(7 downto 0);
89
 
90
      -- Stack pointer (SP = SPH&SPL)
91
      pavr_iof_sph      : out std_logic_vector(7 downto 0);
92
      pavr_iof_sph_wr   : in  std_logic;
93
      pavr_iof_sph_di   : in  std_logic_vector(7 downto 0);
94
      pavr_iof_spl      : out std_logic_vector(7 downto 0);
95
      pavr_iof_spl_wr   : in  std_logic;
96
      pavr_iof_spl_di   : in  std_logic_vector(7 downto 0);
97
 
98
      -- Pointer registers extensions (RAMPX, RAMPY, RAMPZ)
99
      pavr_iof_rampx    : out std_logic_vector(7 downto 0);
100
      pavr_iof_rampx_wr : in  std_logic;
101
      pavr_iof_rampx_di : in  std_logic_vector(7 downto 0);
102
 
103
      pavr_iof_rampy    : out std_logic_vector(7 downto 0);
104
      pavr_iof_rampy_wr : in  std_logic;
105
      pavr_iof_rampy_di : in  std_logic_vector(7 downto 0);
106
 
107
      pavr_iof_rampz    : out std_logic_vector(7 downto 0);
108
      pavr_iof_rampz_wr : in  std_logic;
109
      pavr_iof_rampz_di : in  std_logic_vector(7 downto 0);
110
 
111
      -- Data Memory extension address register (RAMPD)
112
      pavr_iof_rampd    : out std_logic_vector(7 downto 0);
113
      pavr_iof_rampd_wr : in  std_logic;
114
      pavr_iof_rampd_di : in  std_logic_vector(7 downto 0);
115
 
116
      -- Program Memory extension address register (EIND)
117
      pavr_iof_eind     : out std_logic_vector(7 downto 0);
118
      pavr_iof_eind_wr  : in  std_logic;
119
      pavr_iof_eind_di  : in  std_logic_vector(7 downto 0);
120
 
121
      -- AVR non-kernel (feature) register ports
122
      -- Port A
123
      pavr_iof_pa: inout std_logic_vector(7 downto 0);
124
 
125
      -- Interrupt-related interface signals to control module (to the pipeline).
126
      pavr_disable_int  : in  std_logic;                       -- Is the pipeline ready to process a new interrupt?
127
      pavr_int_rq       : out std_logic;                       -- Ask the pipeline to process an interrupt.
128
      pavr_int_vec      : out std_logic_vector(21 downto 0)    -- Tell the pipeline what is the interrupt vector.
129
   );
130
end;
131
 
132
 
133
 
134
architecture pavr_iof_arch of pavr_iof is
135
   -- Kernel registers
136
   signal pavr_iof_sreg_int:   std_logic_vector(7 downto 0);
137
   signal pavr_iof_sph_int:    std_logic_vector(7 downto 0);
138
   signal pavr_iof_spl_int:    std_logic_vector(7 downto 0);
139
   signal pavr_iof_rampx_int:  std_logic_vector(7 downto 0);
140
   signal pavr_iof_rampy_int:  std_logic_vector(7 downto 0);
141
   signal pavr_iof_rampz_int:  std_logic_vector(7 downto 0);
142
   signal pavr_iof_rampd_int:  std_logic_vector(7 downto 0);
143
   signal pavr_iof_eind_int:   std_logic_vector(7 downto 0);
144
 
145
   -- Feature registers
146
   -- Microcontroller control
147
   signal pavr_iof_mcucr:  std_logic_vector(7 downto 0);
148
   -- General interrupt mask
149
   signal pavr_iof_gimsk:  std_logic_vector(7 downto 0);
150
   -- General interrupt flags
151
   signal pavr_iof_gifr:   std_logic_vector(7 downto 0);
152
   -- Timer 0
153
   signal pavr_iof_tcnt0:  std_logic_vector(8 downto 0);    -- *** 9 bits wide, to manage overflow.
154
   signal pavr_iof_tccr0:  std_logic_vector(7 downto 0);
155
   signal pavr_iof_tifr:   std_logic_vector(7 downto 0);
156
   signal pavr_iof_timsk:  std_logic_vector(7 downto 0);
157
   -- Port A
158
   signal pavr_iof_porta:  std_logic_vector(7 downto 0);
159
   signal pavr_iof_ddra:   std_logic_vector(7 downto 0);
160
   signal pavr_iof_pina:   std_logic_vector(7 downto 0);    -- *** This is not a register; these are just wires.
161
 
162
   -- Local wires
163
   signal pavr_tmpdi:      std_logic_vector(7 downto 0);
164
   signal pavr_int_flgs:      std_logic_vector(31 downto 0);   -- !!! Can it be introduced into process as var?
165
   signal pavr_int_flgs_dcd:  std_logic_vector(31 downto 0);   -- -"-
166
 
167
   signal pavr_int0_clk: std_logic;
168
 
169
   signal pavr_t0_clk, next_pavr_t0_clk: std_logic;
170
   signal clk_t0_cnt: std_logic_vector(9 downto 0);
171
 
172
begin
173
 
174
   -- Build interrupt flags vector and decode that vector. That is, prioritize
175
   --    interrupts and find what interrupt has to be processed.
176
   process(pavr_disable_int,
177
           pavr_int_flgs,
178
           pavr_iof_sreg_int,
179
           pavr_iof_gifr, pavr_iof_gimsk,
180
           pavr_iof_tifr, pavr_iof_timsk)
181
   begin
182
      pavr_int_flgs     <= int_to_std_logic_vector(0, pavr_int_flgs'length);
183
      pavr_int_flgs_dcd <= int_to_std_logic_vector(0, pavr_int_flgs'length);
184
 
185
      -- Build active interrupts flags vector
186
      -- First, check if the pipeline is ready to process an interrupt.
187
      if (pavr_disable_int = '0') then
188
          -- Check if interrupts are globally enabled.
189
         if (pavr_iof_sreg_int(7) = '1') then
190
            -- Check all interrupts sources if active and enabled.
191
            pavr_int_flgs(pavr_int0_int_pri) <= pavr_iof_gifr(6) and pavr_iof_gimsk(6);
192
            pavr_int_flgs(pavr_tov0_int_pri) <= pavr_iof_tifr(1) and pavr_iof_timsk(1);
193
         end if;
194
      end if;
195
 
196
      -- Prioritize interrupts
197
      pavr_int_flgs_dcd <= prioritize_int(pavr_int_flgs);
198
   end process;
199
 
200
 
201
 
202
   -- Build Timer 0 clock.
203
   t0_clk:
204
   process(pavr_iof_clk, clk_t0_cnt, pavr_iof_pina, pavr_iof_tccr0)
205
   begin
206
      next_pavr_t0_clk <= '0';
207
      case pavr_iof_tccr0(2 downto 0) is
208
         when "000" =>
209
            null;
210
         when "001" =>
211
            next_pavr_t0_clk <= pavr_iof_clk;
212
         when "010" =>
213
            next_pavr_t0_clk <= clk_t0_cnt(2);
214
         when "011" =>
215
            next_pavr_t0_clk <= clk_t0_cnt(5);
216
         when "100" =>
217
            next_pavr_t0_clk <= clk_t0_cnt(7);
218
         when "101" =>
219
            next_pavr_t0_clk <= clk_t0_cnt(9);
220
         when "110" =>
221
            next_pavr_t0_clk <= not pavr_iof_pina(1);
222
         when others =>
223
            next_pavr_t0_clk <= pavr_iof_pina(1);
224
      end case;
225
   end process t0_clk;
226
 
227
 
228
 
229
   -- Manage IOF data in.
230
   manage_iof_di:
231
   process(pavr_iof_opcode, pavr_iof_bitaddr, pavr_iof_di)
232
   begin
233
      pavr_tmpdi <= int_to_std_logic_vector(0, 8);
234
 
235
      case pavr_iof_opcode is
236
         when pavr_iof_opcode_wrbyte =>
237
            pavr_tmpdi <= pavr_iof_di;
238
         when pavr_iof_opcode_clrbit =>
239
            pavr_tmpdi <= pavr_iof_di;
240
            pavr_tmpdi(std_logic_vector_to_nat(pavr_iof_bitaddr)) <= '0';
241
         when pavr_iof_opcode_setbit =>
242
            pavr_tmpdi <= pavr_iof_di;
243
            pavr_tmpdi(std_logic_vector_to_nat(pavr_iof_bitaddr)) <= '1';
244
         when others =>
245
            null;
246
      end case;
247
   end process manage_iof_di;
248
 
249
 
250
 
251
   -- Managing IOF registers
252
   manage_iof_regs:
253
   process(pavr_iof_clk, pavr_iof_res, pavr_iof_syncres,
254
           pavr_iof_opcode, pavr_iof_addr, pavr_iof_di, pavr_iof_bitaddr,
255
           pavr_tmpdi,
256
           pavr_iof_sreg_wr, pavr_iof_sreg_di,
257
           pavr_iof_sph_wr, pavr_iof_sph_di,
258
           pavr_iof_spl_wr, pavr_iof_spl_di,
259
           pavr_iof_rampx_wr, pavr_iof_rampx_di,
260
           pavr_iof_rampy_wr, pavr_iof_rampy_di,
261
           pavr_iof_rampz_wr, pavr_iof_rampz_di,
262
           pavr_iof_rampd_wr, pavr_iof_rampd_di,
263
           pavr_iof_eind_wr, pavr_iof_eind_di,
264
           pavr_int_flgs_dcd,
265
           pavr_t0_clk, next_pavr_t0_clk, clk_t0_cnt,
266
           pavr_int0_clk,
267
           pavr_iof_sreg_int,
268
           pavr_iof_sph_int, pavr_iof_spl_int,
269
           pavr_iof_rampx_int, pavr_iof_rampy_int, pavr_iof_rampz_int,
270
           pavr_iof_rampd_int,
271
           pavr_iof_eind_int,
272
           pavr_iof_mcucr,
273
           pavr_iof_gimsk, pavr_iof_gifr,
274
           pavr_iof_timsk, pavr_iof_tifr,
275
           pavr_iof_tcnt0, pavr_iof_tccr0,
276
           pavr_iof_porta, pavr_iof_ddra,  pavr_iof_pina, pavr_iof_pa
277
          )
278
      variable pavr_iof_portaz: std_logic_vector(pavr_iof_porta'length - 1 downto 0);
279
   begin
280
 
281
      -- Port A asynchronous circuitry.
282
      for i in 0 to 7 loop
283
         if pavr_iof_ddra(i)='1' then
284
            pavr_iof_portaz(i) := pavr_iof_porta(i);
285
         else
286
            -- *** When synthesizing, to check if the technology permits weak
287
            --    pull-ups and high Z. If it doesn't, workaround these lines.
288
            if pavr_iof_porta(i)='1' then
289
               -- Weak pull-ups
290
               pavr_iof_portaz(i) := 'H';
291
            else
292
               -- High Z
293
               pavr_iof_portaz(i) := 'Z';
294
            end if;
295
         end if;
296
      end loop;
297
      pavr_iof_pa    <= pavr_iof_portaz;
298
      pavr_iof_pina  <= pavr_iof_pa;
299
 
300
      if (pavr_iof_res = '1') then
301
         -- Reset
302
         -- IOF registers
303
         pavr_iof_sreg_int    <= int_to_std_logic_vector(0, 8);
304
         pavr_iof_sph_int     <= int_to_std_logic_vector(0, 8);
305
         pavr_iof_spl_int     <= int_to_std_logic_vector(0, 8);
306
         pavr_iof_rampx_int   <= int_to_std_logic_vector(0, 8);
307
         pavr_iof_rampy_int   <= int_to_std_logic_vector(0, 8);
308
         pavr_iof_rampz_int   <= int_to_std_logic_vector(0, 8);
309
         pavr_iof_rampd_int   <= int_to_std_logic_vector(0, 8);
310
         pavr_iof_eind_int    <= int_to_std_logic_vector(0, 8);
311
 
312
         pavr_iof_mcucr       <= int_to_std_logic_vector(0, 8);
313
         pavr_iof_gimsk       <= int_to_std_logic_vector(0, 8);
314
         pavr_iof_gifr        <= int_to_std_logic_vector(0, 8);
315
 
316
         pavr_iof_tcnt0       <= int_to_std_logic_vector(0, 9);
317
         pavr_iof_tccr0       <= int_to_std_logic_vector(0, 8);
318
         pavr_iof_tifr        <= int_to_std_logic_vector(0, 8);
319
         pavr_iof_timsk       <= int_to_std_logic_vector(0, 8);
320
 
321
         pavr_iof_porta       <= int_to_std_logic_vector(0, 8);
322
         pavr_iof_ddra        <= int_to_std_logic_vector(0, 8);
323
 
324
         -- Local registers
325
         clk_t0_cnt <= int_to_std_logic_vector(0, clk_t0_cnt'length);
326
         pavr_t0_clk <= '0';
327
         pavr_int0_clk <= '0';
328
      elsif pavr_iof_clk'event and pavr_iof_clk = '1' then
329
 
330
         pavr_iof_bitout <= '0';
331
         pavr_int_rq  <= '0';
332
         pavr_int_vec <= int_to_std_logic_vector(0, 22);
333
 
334
 
335
         -- Feature registers-related circuitry -------------------------------
336
         -- External interrupt 0
337
         case pavr_iof_mcucr(1 downto 0) is
338
            when "00" =>
339
               -- Trigger external interrupt 0 on low level.
340
               if pavr_iof_pa(0)='0' then
341
                  pavr_iof_gifr(6) <= '1';
342
               end if;
343
            when "01" =>
344
               -- Not used.
345
               null;
346
            when "10" =>
347
               -- Trigger external interrupt 0 on negative edge.
348
               if pavr_int0_clk='1' and pavr_iof_pa(0)='0' then
349
                  pavr_iof_gifr(6) <= '1';
350
               end if;
351
            when others =>
352
               -- Trigger external interrupt 0 on positive edge.
353
               if pavr_int0_clk='0' and pavr_iof_pa(0)='1' then
354
                  pavr_iof_gifr(6) <= '1';
355
               end if;
356
         end case;
357
         pavr_int0_clk <= pavr_iof_pa(0);
358
 
359
         -- Timer 0
360
         -- Build timer 0's clock.
361
         -- Update counter 0.
362
         case pavr_iof_tccr0(2 downto 0) is
363
            when "000" =>
364
               null;
365
            when "001" =>
366
               pavr_iof_tcnt0 <= pavr_iof_tcnt0 + 1;
367
            when others =>
368
               if pavr_t0_clk='0' and next_pavr_t0_clk='1' then
369
                  pavr_iof_tcnt0 <= pavr_iof_tcnt0 + 1;
370
               end if;
371
         end case;
372
         -- Capture timer 0 overflow event.
373
         if pavr_iof_tcnt0(8) = '1' then
374
            -- Set timer 0 overflow flag in TIFR register.
375
            pavr_iof_tifr(1)  <= '1';
376
            -- Reset overflow (MSBit) in TCNT0 register, because we don't want to
377
            --    set overflow flag over and over again from now on.
378
            pavr_iof_tcnt0(8) <= '0';
379
         end if;
380
         pavr_t0_clk <= next_pavr_t0_clk;
381
         clk_t0_cnt <= clk_t0_cnt+1;
382
 
383
 
384
         -- Interrupt Manager -------------------------------------------------
385
         -- If interrupt 0 is decoded as a winner interrupt, then acknowledge it.
386
         if pavr_int_flgs_dcd(pavr_int0_int_pri) = '1' then
387
            pavr_iof_gifr(6) <= '0';
388
            pavr_int_rq      <= '1';
389
            pavr_int_vec     <= int_to_std_logic_vector(pavr_int0_int_vec, 22);
390
         end if;
391
 
392
         -- If timer 0 overflow interrupt is decoded as a winner interrupt, then
393
         --    acknowledge it.
394
         if pavr_int_flgs_dcd(pavr_tov0_int_pri) = '1' then
395
            pavr_iof_tifr(1) <= '0';
396
            pavr_int_rq      <= '1';
397
            pavr_int_vec     <= int_to_std_logic_vector(pavr_tov0_int_vec, 22);
398
         end if;
399
 
400
 
401
         -- Check IOF opcode and process it. ----------------------------------
402
         case pavr_iof_opcode is
403
            -- Read byte.
404
            when pavr_iof_opcode_rdbyte =>
405
               case std_logic_vector_to_nat(pavr_iof_addr) is
406
                  when pavr_sreg_addr =>
407
                     pavr_iof_do <= pavr_iof_sreg_int;
408
                  when pavr_sph_addr =>
409
                     pavr_iof_do <= pavr_iof_sph_int;
410
                  when pavr_spl_addr =>
411
                     pavr_iof_do <= pavr_iof_spl_int;
412
                  when pavr_rampx_addr =>
413
                     pavr_iof_do <= pavr_iof_rampx_int;
414
                  when pavr_rampy_addr =>
415
                     pavr_iof_do <= pavr_iof_rampy_int;
416
                  when pavr_rampz_addr =>
417
                     pavr_iof_do <= pavr_iof_rampz_int;
418
                  when pavr_rampd_addr =>
419
                     pavr_iof_do <= pavr_iof_rampd_int;
420
                  when pavr_eind_addr =>
421
                     pavr_iof_do <= pavr_iof_eind_int;
422
                  when pavr_mcucr_addr =>
423
                     pavr_iof_do <= pavr_iof_mcucr;
424
                  when pavr_gimsk_addr =>
425
                     pavr_iof_do <= pavr_iof_gimsk;
426
                  when pavr_gifr_addr =>
427
                     pavr_iof_do <= pavr_iof_gifr;
428
                  when pavr_tcnt0_addr =>
429
                     pavr_iof_do <= pavr_iof_tcnt0(7 downto 0);
430
                  when pavr_tccr0_addr =>
431
                     pavr_iof_do <= pavr_iof_tccr0;
432
                  when pavr_tifr_addr =>
433
                     pavr_iof_do <= pavr_iof_tifr;
434
                  when pavr_timsk_addr =>
435
                     pavr_iof_do <= pavr_iof_timsk;
436
                  when pavr_porta_addr =>
437
                     pavr_iof_do <= pavr_iof_porta;
438
                  when pavr_ddra_addr =>
439
                     pavr_iof_do <= pavr_iof_ddra;
440
                  when pavr_pina_addr =>
441
                     pavr_iof_do <= pavr_iof_pina;
442
                  when others =>
443
                     null;
444
               end case;
445
            -- Write byte | clear bit | set bit.
446
            when pavr_iof_opcode_wrbyte | pavr_iof_opcode_clrbit | pavr_iof_opcode_setbit =>
447
               case std_logic_vector_to_nat(pavr_iof_addr) is
448
                  when pavr_sreg_addr =>
449
                     pavr_iof_sreg_int <= pavr_tmpdi;
450
                  when pavr_sph_addr =>
451
                     pavr_iof_sph_int <= pavr_tmpdi;
452
                  when pavr_spl_addr =>
453
                     pavr_iof_spl_int <= pavr_tmpdi;
454
                  when pavr_rampx_addr =>
455
                     pavr_iof_rampx_int <= pavr_tmpdi;
456
                  when pavr_rampy_addr =>
457
                     pavr_iof_rampy_int <= pavr_tmpdi;
458
                  when pavr_rampz_addr =>
459
                     pavr_iof_rampz_int <= pavr_tmpdi;
460
                  when pavr_rampd_addr =>
461
                     pavr_iof_rampd_int <= pavr_tmpdi;
462
                  when pavr_eind_addr =>
463
                     pavr_iof_eind_int <= pavr_tmpdi;
464
                  when pavr_mcucr_addr =>
465
                     pavr_iof_mcucr <= pavr_tmpdi;
466
                  when pavr_gimsk_addr =>
467
                     pavr_iof_gimsk <= pavr_tmpdi;
468
                  when pavr_gifr_addr =>
469
                     pavr_iof_gifr <= pavr_tmpdi;
470
                  when pavr_tcnt0_addr =>
471
                     pavr_iof_tcnt0(         8) <= '0';
472
                     pavr_iof_tcnt0(7 downto 0) <= pavr_tmpdi;
473
                  when pavr_tccr0_addr =>
474
                     pavr_iof_tccr0 <= pavr_tmpdi;
475
                  when pavr_tifr_addr =>
476
                     pavr_iof_tifr <= pavr_tmpdi;
477
                  when pavr_timsk_addr =>
478
                     pavr_iof_timsk <= pavr_tmpdi;
479
                  when pavr_porta_addr =>
480
                     pavr_iof_porta <= pavr_tmpdi;
481
                  when pavr_ddra_addr =>
482
                     pavr_iof_ddra <= pavr_tmpdi;
483
                  when pavr_pina_addr =>
484
                     -- PinA is just a read-only wire.
485
                     null;
486
                  when others =>
487
                     null;
488
               end case;
489
            -- Load bit.
490
            when pavr_iof_opcode_ldbit =>
491
               pavr_iof_do <= pavr_iof_di;
492
               pavr_iof_do(std_logic_vector_to_nat(pavr_iof_bitaddr)) <= pavr_iof_sreg_int(6);
493
            -- Store bit.
494
            when pavr_iof_opcode_stbit =>
495
               pavr_iof_sreg_int(6) <= pavr_iof_di(std_logic_vector_to_nat(pavr_iof_bitaddr));
496
            -- pavr_iof_opcode_nop
497
            when others =>
498
               null;
499
         end case;
500
 
501
         -- Kernel registers ports --------------------------------------------
502
         -- Status register (SREG) port
503
         if (pavr_iof_sreg_wr = '1') then
504
            pavr_iof_sreg_int <= pavr_iof_sreg_di;
505
         end if;
506
 
507
         -- Stack pointer (SPH&SPL) ports
508
         if (pavr_iof_sph_wr = '1') then
509
            pavr_iof_sph_int <= pavr_iof_sph_di;
510
         end if;
511
         if (pavr_iof_spl_wr = '1') then
512
            pavr_iof_spl_int <= pavr_iof_spl_di;
513
         end if;
514
 
515
         -- Pointer registers X extension (RAMPX) port
516
         if (pavr_iof_rampx_wr = '1') then
517
            pavr_iof_rampx_int <= pavr_iof_rampx_di;
518
         end if;
519
 
520
         -- Pointer registers Y extension (RAMPY) port
521
         if (pavr_iof_rampy_wr = '1') then
522
            pavr_iof_rampy_int <= pavr_iof_rampy_di;
523
         end if;
524
 
525
         -- Pointer registers Z extension (RAMPZ) port
526
         if (pavr_iof_rampz_wr = '1') then
527
            pavr_iof_rampz_int <= pavr_iof_rampz_di;
528
         end if;
529
 
530
         -- Data Memory extension address (RAMPD) register
531
         if (pavr_iof_rampd_wr = '1') then
532
            pavr_iof_rampd_int <= pavr_iof_rampd_di;
533
         end if;
534
 
535
         -- Program Memory extension address (EIND) register
536
         if (pavr_iof_eind_wr = '1') then
537
            pavr_iof_eind_int <= pavr_iof_eind_di;
538
         end if;
539
 
540
         if (pavr_iof_syncres = '1') then
541
            -- Synchronous reset
542
            -- IOF registers
543
            pavr_iof_sreg_int    <= int_to_std_logic_vector(0, 8);
544
            pavr_iof_sph_int     <= int_to_std_logic_vector(0, 8);
545
            pavr_iof_spl_int     <= int_to_std_logic_vector(0, 8);
546
            pavr_iof_rampx_int   <= int_to_std_logic_vector(0, 8);
547
            pavr_iof_rampy_int   <= int_to_std_logic_vector(0, 8);
548
            pavr_iof_rampz_int   <= int_to_std_logic_vector(0, 8);
549
            pavr_iof_rampd_int   <= int_to_std_logic_vector(0, 8);
550
            pavr_iof_eind_int    <= int_to_std_logic_vector(0, 8);
551
 
552
            pavr_iof_mcucr       <= int_to_std_logic_vector(0, 8);
553
            pavr_iof_gimsk       <= int_to_std_logic_vector(0, 8);
554
            pavr_iof_gifr        <= int_to_std_logic_vector(0, 8);
555
 
556
            pavr_iof_tcnt0       <= int_to_std_logic_vector(0, 9);
557
            pavr_iof_tccr0       <= int_to_std_logic_vector(0, 8);
558
            pavr_iof_tifr        <= int_to_std_logic_vector(0, 8);
559
            pavr_iof_timsk       <= int_to_std_logic_vector(0, 8);
560
 
561
            pavr_iof_porta       <= int_to_std_logic_vector(0, 8);
562
            pavr_iof_ddra        <= int_to_std_logic_vector(0, 8);
563
 
564
            -- Local registers
565
            clk_t0_cnt <= int_to_std_logic_vector(0, clk_t0_cnt'length);
566
            pavr_t0_clk <= '0';
567
            pavr_int0_clk <= '0';
568
         end if;
569
      end if;
570
   end process manage_iof_regs;
571
 
572
 
573
 
574
   -- Zero-level assignments.
575
   pavr_iof_sreg  <= pavr_iof_sreg_int;
576
   pavr_iof_sph   <= pavr_iof_sph_int;
577
   pavr_iof_spl   <= pavr_iof_spl_int;
578
   pavr_iof_rampx <= pavr_iof_rampx_int;
579
   pavr_iof_rampy <= pavr_iof_rampy_int;
580
   pavr_iof_rampz <= pavr_iof_rampz_int;
581
   pavr_iof_rampd <= pavr_iof_rampd_int;
582
   pavr_iof_eind  <= pavr_iof_eind_int;
583
 
584
end;
585
-- </File body>

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