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doru |
-- <File header>
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-- Project
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-- pAVR (pipelined AVR) is an 8 bit RISC controller, compatible with Atmel's
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-- AVR core, but about 3x faster in terms of both clock frequency and MIPS.
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-- The increase in speed comes from a relatively deep pipeline. The original
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-- AVR core has only two pipeline stages (fetch and execute), while pAVR has
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-- 6 pipeline stages:
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-- 1. PM (read Program Memory)
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-- 2. INSTR (load Instruction)
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-- 3. RFRD (decode Instruction and read Register File)
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-- 4. OPS (load Operands)
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-- 5. ALU (execute ALU opcode or access Unified Memory)
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-- 6. RFWR (write Register File)
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-- Version
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-- 0.32
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-- Date
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-- 2002 August 07
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-- Author
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-- Doru Cuturela, doruu@yahoo.com
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-- License
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-- </File header>
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-- <File info>
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-- This defines pAVR's Register File.
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-- The Register File has 3 ports: 2 for reading and 1 for writing. All these
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-- access all 32 locations in the register file. Apart from these 3 ports,
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-- there are 3 special ports that access 16 bit pointer registers X, Y, Z, for
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-- both reading and writing. The pointer registers are mapped on the register
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-- file, at addresses 26-27 (pointer register X), 28-29 (Y) and 30-31 (Z).
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-- Physically, the register file consists of a memory-like entity with 26 8 bit
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-- locations, and 3 16 bit registers. Together, these form the 32 locations
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-- of the register file. The physical separation of locations <26 and >=26 is
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-- is invisible from outside.
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-- Writing on the write port and on every pointer register port can be done
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-- in parallel. However, if writing at the same time a location via the write
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-- port and one of the pointer registers, writing via pointer register port
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-- has priority.
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-- </File info>
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-- <File body>
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library work;
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use work.std_util.all;
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use work.pavr_util.all;
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use work.pavr_constants.all;
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity pavr_rf is
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port(
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pavr_rf_clk: in std_logic;
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pavr_rf_res: in std_logic;
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pavr_rf_syncres: in std_logic;
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-- Read port 1
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pavr_rf_rd1_addr: in std_logic_vector(4 downto 0);
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pavr_rf_rd1_rd: in std_logic;
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pavr_rf_rd1_do: out std_logic_vector(7 downto 0);
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-- Read port 2
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pavr_rf_rd2_addr: in std_logic_vector(4 downto 0);
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pavr_rf_rd2_rd: in std_logic;
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pavr_rf_rd2_do: out std_logic_vector(7 downto 0);
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-- Write port
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pavr_rf_wr_addr: in std_logic_vector(4 downto 0);
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pavr_rf_wr_wr: in std_logic;
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pavr_rf_wr_di: in std_logic_vector(7 downto 0);
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-- Pointer registers
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pavr_rf_x: out std_logic_vector(15 downto 0);
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pavr_rf_x_wr: in std_logic;
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pavr_rf_x_di: in std_logic_vector(15 downto 0);
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pavr_rf_y: out std_logic_vector(15 downto 0);
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pavr_rf_y_wr: in std_logic;
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pavr_rf_y_di: in std_logic_vector(15 downto 0);
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pavr_rf_z: out std_logic_vector(15 downto 0);
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pavr_rf_z_wr: in std_logic;
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pavr_rf_z_di: in std_logic_vector(15 downto 0)
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);
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end;
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architecture pavr_rf_arch of pavr_rf is
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signal pavr_rf_x_int: std_logic_vector(15 downto 0);
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signal pavr_rf_y_int: std_logic_vector(15 downto 0);
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signal pavr_rf_z_int: std_logic_vector(15 downto 0);
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type t_pavr_rf_data_array is array (0 to 25) of std_logic_vector(7 downto 0);
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signal pavr_rf_data_array: t_pavr_rf_data_array;
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begin
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-- Read port 1
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process
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variable is_x, is_y, is_z: std_logic;
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variable tv: std_logic_vector(2 downto 0);
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begin
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tv := int_to_std_logic_vector(0, 3);
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wait until ((pavr_rf_clk'event) and (pavr_rf_clk = '1'));
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if (pavr_rf_rd1_addr(4 downto 1) = "1101") then
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is_x := '1';
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else
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is_x := '0';
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end if;
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if (pavr_rf_rd1_addr(4 downto 1) = "1110") then
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is_y := '1';
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else
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is_y := '0';
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end if;
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if (pavr_rf_rd1_addr(4 downto 1) = "1111") then
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is_z := '1';
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else
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is_z := '0';
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end if;
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if (pavr_rf_rd1_rd = '1') then
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tv := is_x & is_y & is_z;
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case tv is
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when "000" =>
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pavr_rf_rd1_do <= pavr_rf_data_array(std_logic_vector_to_nat(pavr_rf_rd1_addr));
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when "100" =>
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if (pavr_rf_rd1_addr(0) = '0') then
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pavr_rf_rd1_do <= pavr_rf_x_int(7 downto 0);
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else
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pavr_rf_rd1_do <= pavr_rf_x_int(15 downto 8);
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end if;
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when "010" =>
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if (pavr_rf_rd1_addr(0) = '0') then
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pavr_rf_rd1_do <= pavr_rf_y_int(7 downto 0);
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else
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pavr_rf_rd1_do <= pavr_rf_y_int(15 downto 8);
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end if;
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when others =>
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if (pavr_rf_rd1_addr(0) = '0') then
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pavr_rf_rd1_do <= pavr_rf_z_int(7 downto 0);
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else
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pavr_rf_rd1_do <= pavr_rf_z_int(15 downto 8);
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end if;
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end case;
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end if;
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end process;
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-- Read port 2
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process
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variable is_x, is_y, is_z: std_logic;
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variable tv: std_logic_vector(2 downto 0);
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begin
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tv := int_to_std_logic_vector(0, 3);
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wait until ((pavr_rf_clk'event) and (pavr_rf_clk = '1'));
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if (pavr_rf_rd2_addr(4 downto 1) = "1101") then
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is_x := '1';
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else
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is_x := '0';
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end if;
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if (pavr_rf_rd2_addr(4 downto 1) = "1110") then
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is_y := '1';
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else
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is_y := '0';
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end if;
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if (pavr_rf_rd2_addr(4 downto 1) = "1111") then
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is_z := '1';
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else
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is_z := '0';
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end if;
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if (pavr_rf_rd2_rd = '1') then
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tv := is_x & is_y & is_z;
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case tv is
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when "000" =>
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pavr_rf_rd2_do <= pavr_rf_data_array(std_logic_vector_to_nat(pavr_rf_rd2_addr));
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when "100" =>
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if (pavr_rf_rd2_addr(0) = '0') then
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pavr_rf_rd2_do <= pavr_rf_x_int(7 downto 0);
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else
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pavr_rf_rd2_do <= pavr_rf_x_int(15 downto 8);
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end if;
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when "010" =>
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if (pavr_rf_rd2_addr(0) = '0') then
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pavr_rf_rd2_do <= pavr_rf_y_int(7 downto 0);
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else
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pavr_rf_rd2_do <= pavr_rf_y_int(15 downto 8);
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end if;
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when others =>
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if (pavr_rf_rd2_addr(0) = '0') then
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pavr_rf_rd2_do <= pavr_rf_z_int(7 downto 0);
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else
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pavr_rf_rd2_do <= pavr_rf_z_int(15 downto 8);
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end if;
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end case;
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end if;
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end process;
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-- Write port and pointer registers
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process(pavr_rf_clk, pavr_rf_res, pavr_rf_syncres,
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pavr_rf_wr_addr, pavr_rf_wr_wr, pavr_rf_wr_di, pavr_rf_x_wr, pavr_rf_y_wr, pavr_rf_z_wr,
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pavr_rf_x_di, pavr_rf_y_di, pavr_rf_z_di)
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variable is_x, is_y, is_z: std_logic;
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variable tv: std_logic_vector(2 downto 0);
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begin
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tv := int_to_std_logic_vector(0, 3);
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if (pavr_rf_wr_addr(4 downto 1) = "1101") then
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is_x := '1';
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else
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is_x := '0';
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end if;
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if (pavr_rf_wr_addr(4 downto 1) = "1110") then
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is_y := '1';
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else
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is_y := '0';
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end if;
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if (pavr_rf_wr_addr(4 downto 1) = "1111") then
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is_z := '1';
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else
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is_z := '0';
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end if;
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if (pavr_rf_res = '1') then
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-- Asynchronous reset
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pavr_rf_x_int <= int_to_std_logic_vector(0, 16);
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pavr_rf_y_int <= int_to_std_logic_vector(0, 16);
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pavr_rf_z_int <= int_to_std_logic_vector(0, 16);
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elsif ((pavr_rf_clk'event) and (pavr_rf_clk = '1')) then
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-- Write port
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if (pavr_rf_wr_wr = '1') then
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tv := is_x & is_y & is_z;
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case tv is
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when "000" =>
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pavr_rf_data_array(std_logic_vector_to_nat(pavr_rf_wr_addr)) <= pavr_rf_wr_di;
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when "100" =>
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if (pavr_rf_wr_addr(0) = '0') then
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pavr_rf_x_int(7 downto 0) <= pavr_rf_wr_di;
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else
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pavr_rf_x_int(15 downto 8) <= pavr_rf_wr_di;
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end if;
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when "010" =>
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if (pavr_rf_wr_addr(0) = '0') then
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pavr_rf_y_int(7 downto 0) <= pavr_rf_wr_di;
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else
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pavr_rf_y_int(15 downto 8) <= pavr_rf_wr_di;
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end if;
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when others =>
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if (pavr_rf_wr_addr(0) = '0') then
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pavr_rf_z_int(7 downto 0) <= pavr_rf_wr_di;
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else
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pavr_rf_z_int(15 downto 8) <= pavr_rf_wr_di;
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end if;
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end case;
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end if;
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-- Write pointer registers. Possibly overwrite the above write.
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if (pavr_rf_x_wr = '1') then
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pavr_rf_x_int <= pavr_rf_x_di;
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end if;
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if (pavr_rf_y_wr = '1') then
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pavr_rf_y_int <= pavr_rf_y_di;
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end if;
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if (pavr_rf_z_wr = '1') then
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pavr_rf_z_int <= pavr_rf_z_di;
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end if;
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if (pavr_rf_syncres = '1') then
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-- Synchronous reset
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pavr_rf_x_int <= int_to_std_logic_vector(0, 16);
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pavr_rf_y_int <= int_to_std_logic_vector(0, 16);
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pavr_rf_z_int <= int_to_std_logic_vector(0, 16);
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end if;
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end if;
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end process;
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-- Zero-level assignments
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pavr_rf_x <= pavr_rf_x_int;
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pavr_rf_y <= pavr_rf_y_int;
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pavr_rf_z <= pavr_rf_z_int;
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end;
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-- </File body>
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