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NikosAl |
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-- Copyright (C) 2010 Nikolaos Ch. Alachiotis --
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-- --
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-- Engineer: Nikolaos Ch. Alachiotis --
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-- --
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-- Contact: alachiot@cs.tum.edu --
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-- n.alachiotis@gmail.com --
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-- --
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-- Create Date: 14:45:39 11/27/2009 --
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-- Module Name: IPV4_PACKET_TRANSMITTER --
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-- Target Devices: Virtex 5 FPGAs --
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-- Tool versions: ISE 10.1 --
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-- Description: This component can be used to send IPv4 Ethernet Packets. --
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-- Additional Comments: The look-up table contains the header fields of the IP packet, --
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-- so please keep in mind that you have to reinitialize this LUT. --
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-- --
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-----------------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity IPV4_PACKET_TRANSMITTER is
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Port ( rst : in STD_LOGIC;
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clk_125MHz : in STD_LOGIC;
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transmit_start_enable : in STD_LOGIC;
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transmit_data_length : in STD_LOGIC_VECTOR (15 downto 0);
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usr_data_trans_phase_on : out STD_LOGIC;
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transmit_data_input_bus : in STD_LOGIC_VECTOR (7 downto 0);
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start_of_frame_O : out STD_LOGIC;
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end_of_frame_O : out STD_LOGIC;
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source_ready : out STD_LOGIC;
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transmit_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0);
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flex_wren: in STD_LOGIC;
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flex_wraddr: in STD_LOGIC_VECTOR(5 downto 0);
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flex_wrdata: in STD_LOGIC_VECTOR(7 downto 0);
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flex_checksum_baseval: in std_logic_vector(15 downto 0)
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);
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end IPV4_PACKET_TRANSMITTER;
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architecture Behavioral of IPV4_PACKET_TRANSMITTER is
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-----------------------------------------------------------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------------------------------------------------------------
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-- IPv4 PACKET STRUCTURE : --
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-- Size | Description | Transmission Order | Position --
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-- -----------------------------------------------------------------------------------------------------------
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-- 6 bytes | Destin MAC Address (PC) | 0 1 2 3 4 5 | LUT --
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-- | X-X-X-X-X-X | | --
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-- | | | --
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-- 6 bytes | Source MAC Address (FPGA) | 6 7 8 9 10 11 | LUT --
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-- | 11111111-11111111-11111111-11111111-... | | --
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-- 2 bytes | Ethernet Type * | 12 13 | LUT --
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-- | (fixed to 00001000-00000000 :=> | | --
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-- | Internet Protocol, Version 4 (IPv4)) | | --
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-- -- Start of IPv4 Packet ** - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- | --
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-- 1 byte | 4 MSBs = Version , 4 LSBs = Header Length | 14 | LUT --
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-- | 0100 0101 | | --
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-- 1 byte | Differentiated Services | 15 | LUT --
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-- | 00000000 | | --
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-- 2 bytes | Total Length | 16 17 | REG --
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-- | 00000000-00100100 (base: 20 + 8 + datalength)| | --
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-- 2 bytes | Identification | 18 19 | LUT --
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-- | 00000000-00000000 | | --
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-- 2 bytes | 3 MSBs = Flags , 13 LSBs = Fragment Offset | 20 21 | LUT --
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-- | 010 - 0000000000000 | | --
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-- 1 byte | Time to Live | 22 | LUT --
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-- | 01000000 | | --
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-- 1 byte | Protocol | 23 | LUT --
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-- | 00010001 | | --
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-- 2 bytes | Header Checksum | 24 25 | REG --
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-- | 10110111 01111101 (base value) | | --
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-- 4 bytes | Source IP Address | 26 27 28 29 | LUT --
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-- | X-X-X-X - FPGA | | --
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-- 4 bytes | Destin IP Address | 30 31 32 33 | LUT --
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-- | X-X-X-X - PC | | --
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-- -- Start of UDP Packet *** - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- | --
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-- 2 bytes | Source Port | 34 35 | LUT --
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-- | X-X | | --
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-- 2 bytes | Destination Port | 36 37 | LUT --
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-- | X-X | | --
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-- 2 bytes | Length | 38 39 | REG --
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-- | 00000000 - 00010000 (8 + # data bytes) | | --
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-- 2 bytes | Checksum | 40 41 | LUT --
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-- | 00000000 - 00000000 | | --
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-- X bytes | Data | 42 .. X | from input --
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-- | | | --
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-----------------------------------------------------------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------------------------------------------------------------
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-- * More details about the Ethernet Type value you can find here:
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-- http://en.wikipedia.org/wiki/Ethertype
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-- ** More details about the Internet Protocol, Version 4 (IPv4) you can find here:
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-- http://en.wikipedia.org/wiki/IPv4
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-- *** More details about the Internet Protocol, Version 4 (IPv4) you can find here:
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-- http://en.wikipedia.org/wiki/User_Datagram_Protocol
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-----------------------------------------------------------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------------------------------------------------------------
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--------------------------------------------------------------------------------------
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-- COMPONENT DECLARATION
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--------------------------------------------------------------------------------------
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component REG_16B_WREN is
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Port ( rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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wren : in STD_LOGIC;
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input : in STD_LOGIC_VECTOR (15 downto 0);
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output : out STD_LOGIC_VECTOR (15 downto 0));
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end component;
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component IPV4_LUT_INDEXER is
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Port ( rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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transmit_enable : in STD_LOGIC;
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LUT_index : out STD_LOGIC_VECTOR (5 downto 0));
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end component;
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--component dist_mem_64x8 is
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-- port (
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-- clk : in STD_LOGIC := 'X';
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-- a : in STD_LOGIC_VECTOR ( 5 downto 0 );
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-- qspo : out STD_LOGIC_VECTOR ( 7 downto 0 )
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-- );
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--end component;
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component dist_mem_64x8 is
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port (
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clk : in STD_LOGIC := 'X';
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we : in STD_LOGIC := 'X';
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a : in STD_LOGIC_VECTOR ( 5 downto 0 );
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d : in STD_LOGIC_VECTOR ( 7 downto 0 );
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qspo : out STD_LOGIC_VECTOR ( 7 downto 0 )
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);
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end component;
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component OVERRIDE_LUT_CONTROL is
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Port ( clk : in STD_LOGIC;
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input_addr : in STD_LOGIC_VECTOR (5 downto 0);
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sel_total_length_MSBs : out STD_LOGIC;
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sel_total_length_LSBs : out STD_LOGIC;
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sel_header_checksum_MSBs : out STD_LOGIC;
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sel_header_checksum_LSBs : out STD_LOGIC;
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sel_length_MSBs : out STD_LOGIC;
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sel_length_LSBs : out STD_LOGIC
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);
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end component;
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component TARGET_EOF is
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Port ( rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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start : in STD_LOGIC;
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total_length_from_reg : in STD_LOGIC_VECTOR(15 downto 0);
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eof_O : out STD_LOGIC);
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end component;
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component ENABLE_USER_DATA_TRANSMISSION is
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Port ( rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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start_usr_data_trans : in STD_LOGIC;
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stop_usr_data_trans : in STD_LOGIC;
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usr_data_sel : out STD_LOGIC);
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end component;
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component ALLOW_ZERO_UDP_CHECKSUM is
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Port ( clk : in STD_LOGIC;
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input : in STD_LOGIC;
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output_to_readen : out STD_LOGIC;
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output_to_datasel : out STD_LOGIC);
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end component;
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--------------------------------------------------------------------------------------
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-- SIGNAL DECLARATION
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--------------------------------------------------------------------------------------
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signal transmit_start_enable_tmp,
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sel_total_length_MSBs,
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sel_total_length_LSBs,
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sel_header_checksum_MSBs,
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sel_header_checksum_LSBs,
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sel_length_MSBs,
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sel_length_LSBs,
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lut_out_sel,
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source_ready_previous_value,
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end_of_frame_O_tmp,
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transmit_start_enable_reg,
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usr_data_sel_sig,
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start_usr_data_read,
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start_usr_data_trans : STD_LOGIC;
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signal LUT_addr,
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LUT_addr_dual,
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sel_rd,
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sel_wr: STD_LOGIC_VECTOR(5 downto 0);
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signal transmit_data_input_bus_tmp,
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transmit_data_output_bus_tmp,
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sel_total_length_MSBs_vec,
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sel_total_length_LSBs_vec,
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sel_header_checksum_MSBs_vec,
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sel_header_checksum_LSBs_vec,
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sel_length_MSBs_vec,
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sel_length_LSBs_vec,
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lut_out_sel_vec,
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transmit_data_output_bus_no_usr_data,
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usr_data_not_sel_vec,
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usr_data_sel_vec : STD_LOGIC_VECTOR(7 downto 0);
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signal transmit_data_length_tmp,
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data_length_regout,
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tmp_total_length,
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tmp_header_checksum,
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tmp_header_checksum_baseval,
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tmp_length : STD_LOGIC_VECTOR(15 downto 0);
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begin
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transmit_start_enable_tmp<=transmit_start_enable;
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transmit_data_length_tmp<=transmit_data_length;
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transmit_data_input_bus_tmp<=transmit_data_input_bus;
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----------------------------------------------------------------------------------------------------
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-- start_of_frame_O signal
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----------------------------------------------------------------------------------------------------
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-- Description: start_of_frame_O is active low
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-- We connect it to the delayed for one clock cycle transmit_start_enable input signal
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-- through a NOT gate since transmit_start_enable is active high.
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process(clk_125MHz)
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begin
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if clk_125MHz'event and clk_125MHz='1' then
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transmit_start_enable_reg<=transmit_start_enable_tmp; -- Delay transmit_start_enable one cycle.
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end if;
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end process;
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start_of_frame_O<=not transmit_start_enable_reg;
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----------------------------------------------------------------------------------------------------
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-- end_of_frame_O signal
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----------------------------------------------------------------------------------------------------
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-- Description: end_of_frame_O is active low
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-- The TARGET_EOF module targets the last byte of the packet that is being transmitted
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-- based on a counter that counts the number of transmitted bytes and a comparator that
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-- detects the last byte which is the <tmp_total_length>th byte.
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TARGET_EOF_port_map: TARGET_EOF port map
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(
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rst =>rst,
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clk =>clk_125MHz,
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start =>transmit_start_enable_reg,
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total_length_from_reg =>tmp_total_length,
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eof_O =>end_of_frame_O_tmp
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);
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--* The counter in TARGET_EOF starts from -X, where X is the number of bytes transmitted before the
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-- IPv4 packet. (MAC addresses + Ethernet Type)
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end_of_frame_O<=end_of_frame_O_tmp;
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----------------------------------------------------------------------------------------------------
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-- source_ready signal
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----------------------------------------------------------------------------------------------------
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-- Description: source_ready is active low
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-- This signal is idle(high). (based on rst and end_of_frame_O_tmp).
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-- This signal is active(low). (based on transmit_start_enable and end_of_frame_O_tmp).
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process(clk_125MHz)
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begin
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if rst='1' then
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source_ready<='1';
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source_ready_previous_value<='1';
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else
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if clk_125MHz'event and clk_125MHz='1' then
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if (transmit_start_enable_tmp='1' and source_ready_previous_value='1') then
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source_ready<='0';
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source_ready_previous_value<='0';
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else
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if (end_of_frame_O_tmp='0' and source_ready_previous_value='0') then
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source_ready<='1';
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source_ready_previous_value<='1';
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end if;
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end if;
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end if;
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end if;
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end process;
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----------------------------------------------------------------------------------------------------
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-- transmit_data_output_bus
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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-- Component Name: REG_16B_WREN
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-- Instance Name: NUMBER_OR_DATA_IN_BYTES_REGISTER
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-- Description: Register that holds the number of bytes of input data
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-- that will be transmitted in the packet.
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----------------------------------------------------------------------------------------------------
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NUMBER_OR_DATA_IN_BYTES_REGISTER : REG_16B_WREN port map
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(
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rst =>rst,
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clk =>clk_125MHz,
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wren =>transmit_start_enable_tmp, -- The transmit_start_enable input signal can be used as wren.
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input =>transmit_data_length_tmp,
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output =>data_length_regout
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);
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----------------------------------------------------------------------------------------------------
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tmp_total_length<="0000000000011100" + data_length_regout;
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tmp_header_checksum_baseval<=flex_checksum_baseval;
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--tmp_header_checksum_baseval<="1011011101111101"; -- CHANGE VALUE! : You have to change this value!
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tmp_header_checksum<=tmp_header_checksum_baseval - data_length_regout;
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tmp_length<="0000000000001000" + data_length_regout;
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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-- Component Name: IPV4_LUT_INDEXER
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-- Instance Name: IPV4_LUT_INDEXER_port_map
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337 |
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-- Description: When transmit_enable is high for one cycle IPV4_LUT_INDEXER generates the
|
338 |
|
|
-- addresses to the LUT that contains the header section of the IP packet.
|
339 |
|
|
----------------------------------------------------------------------------------------------------
|
340 |
|
|
IPV4_LUT_INDEXER_port_map : IPV4_LUT_INDEXER port map
|
341 |
|
|
(
|
342 |
|
|
rst =>rst,
|
343 |
|
|
clk =>clk_125MHz,
|
344 |
|
|
transmit_enable =>transmit_start_enable_tmp,
|
345 |
|
|
LUT_index =>LUT_addr
|
346 |
|
|
);
|
347 |
|
|
----------------------------------------------------------------------------------------------------
|
348 |
|
|
|
349 |
|
|
----------------------------------------------------------------------------------------------------
|
350 |
|
|
-- Component Name: dist_mem_64x8
|
351 |
|
|
-- Instance Name: LUT_MEM
|
352 |
|
|
-- Description: LUT that contains the header section.
|
353 |
|
|
----------------------------------------------------------------------------------------------------
|
354 |
|
|
LUT_addr_dual <= (LUT_addr and sel_rd) or (flex_wraddr and sel_wr);
|
355 |
|
|
|
356 |
|
|
sel_rd <= (others=> not flex_wren);
|
357 |
|
|
sel_wr <= (others=> flex_wren);
|
358 |
|
|
|
359 |
|
|
LUT_MEM : dist_mem_64x8 port map
|
360 |
|
|
(
|
361 |
|
|
--clk =>clk_125MHz,
|
362 |
|
|
--a =>LUT_addr_dual,
|
363 |
|
|
--qspo =>transmit_data_output_bus_tmp
|
364 |
|
|
|
365 |
|
|
clk =>clk_125MHz,
|
366 |
|
|
we =>flex_wren,
|
367 |
|
|
a => LUT_addr_dual,
|
368 |
|
|
d => flex_wrdata,
|
369 |
|
|
qspo =>transmit_data_output_bus_tmp
|
370 |
|
|
|
371 |
|
|
|
372 |
|
|
);
|
373 |
|
|
|
374 |
|
|
|
375 |
|
|
|
376 |
|
|
|
377 |
|
|
|
378 |
|
|
|
379 |
|
|
|
380 |
|
|
----------------------------------------------------------------------------------------------------
|
381 |
|
|
|
382 |
|
|
----------------------------------------------------------------------------------------------------
|
383 |
|
|
-- Component Name: OVERRIDE_LUT_CONTROL
|
384 |
|
|
-- Instance Name: OVERRIDE_LUT_CONTROL_port_map
|
385 |
|
|
-- Description: Decides whether the output byte will come from the LUT or not.
|
386 |
|
|
----------------------------------------------------------------------------------------------------
|
387 |
|
|
OVERRIDE_LUT_CONTROL_port_map : OVERRIDE_LUT_CONTROL port map
|
388 |
|
|
(
|
389 |
|
|
clk =>clk_125MHz,
|
390 |
|
|
input_addr =>LUT_addr,
|
391 |
|
|
sel_total_length_MSBs =>sel_total_length_MSBs,
|
392 |
|
|
sel_total_length_LSBs =>sel_total_length_LSBs,
|
393 |
|
|
sel_header_checksum_MSBs =>sel_header_checksum_MSBs,
|
394 |
|
|
sel_header_checksum_LSBs =>sel_header_checksum_LSBs,
|
395 |
|
|
sel_length_MSBs =>sel_length_MSBs,
|
396 |
|
|
sel_length_LSBs =>sel_length_LSBs
|
397 |
|
|
);
|
398 |
|
|
----------------------------------------------------------------------------------------------------
|
399 |
|
|
|
400 |
|
|
----------------------------------------------------------------------------------------------------
|
401 |
|
|
-- MUX 7 to 1
|
402 |
|
|
sel_total_length_MSBs_vec<=(others=>sel_total_length_MSBs);
|
403 |
|
|
sel_total_length_LSBs_vec<=(others=>sel_total_length_LSBs);
|
404 |
|
|
sel_header_checksum_MSBs_vec<=(others=>sel_header_checksum_MSBs);
|
405 |
|
|
sel_header_checksum_LSBs_vec<=(others=>sel_header_checksum_LSBs);
|
406 |
|
|
sel_length_MSBs_vec<=(others=>sel_length_MSBs);
|
407 |
|
|
sel_length_LSBs_vec<=(others=>sel_length_LSBs);
|
408 |
|
|
lut_out_sel_vec <= (others=>lut_out_sel);
|
409 |
|
|
|
410 |
|
|
lut_out_sel<=(not sel_total_length_MSBs) and (not sel_total_length_LSBs) and
|
411 |
|
|
(not sel_header_checksum_MSBs) and (not sel_header_checksum_LSBs) and
|
412 |
|
|
(not sel_length_MSBs) and (not sel_length_LSBs);
|
413 |
|
|
|
414 |
|
|
-- MUX output
|
415 |
|
|
transmit_data_output_bus_no_usr_data<= (transmit_data_output_bus_tmp and lut_out_sel_vec) or
|
416 |
|
|
(tmp_total_length(15 downto 8) and sel_total_length_MSBs_vec) or
|
417 |
|
|
(tmp_total_length(7 downto 0) and sel_total_length_LSBs_vec) or
|
418 |
|
|
(tmp_header_checksum(15 downto 8) and sel_header_checksum_MSBs_vec) or
|
419 |
|
|
(tmp_header_checksum(7 downto 0) and sel_header_checksum_LSBs_vec) or
|
420 |
|
|
(tmp_length(15 downto 8) and sel_length_MSBs_vec) or
|
421 |
|
|
(tmp_length(7 downto 0) and sel_length_LSBs_vec);
|
422 |
|
|
----------------------------------------------------------------------------------------------------
|
423 |
|
|
|
424 |
|
|
----------------------------------------------------------------------------------------------------
|
425 |
|
|
-- Component Name: ALLOW_ZERO_UDP_CHECKSUM
|
426 |
|
|
-- Instance Name: ALLOW_ZERO_UDP_CHECKSUM_port_map
|
427 |
|
|
-- Description: Delays the user data transmition phase in order to transmit two bytes with zero
|
428 |
|
|
-- first.
|
429 |
|
|
----------------------------------------------------------------------------------------------------
|
430 |
|
|
ALLOW_ZERO_UDP_CHECKSUM_port_map: ALLOW_ZERO_UDP_CHECKSUM port map
|
431 |
|
|
(
|
432 |
|
|
clk =>clk_125MHz,
|
433 |
|
|
input =>sel_length_LSBs,
|
434 |
|
|
output_to_readen =>start_usr_data_read,
|
435 |
|
|
output_to_datasel =>start_usr_data_trans
|
436 |
|
|
);
|
437 |
|
|
----------------------------------------------------------------------------------------------------
|
438 |
|
|
|
439 |
|
|
----------------------------------------------------------------------------------------------------
|
440 |
|
|
-- Component Name: ENABLE_USER_DATA_TRANSMISSION
|
441 |
|
|
-- Instance Name: ENABLE_USER_DATA_READ_port_map
|
442 |
|
|
-- Description: Sets usr_data_trans_phase_on signal one cycle before the transmittion of the
|
443 |
|
|
-- first user byte.
|
444 |
|
|
----------------------------------------------------------------------------------------------------
|
445 |
|
|
ENABLE_USER_DATA_READ_port_map: ENABLE_USER_DATA_TRANSMISSION port map
|
446 |
|
|
( rst =>rst,
|
447 |
|
|
clk =>clk_125MHz,
|
448 |
|
|
start_usr_data_trans =>start_usr_data_read,
|
449 |
|
|
stop_usr_data_trans =>end_of_frame_O_tmp,
|
450 |
|
|
usr_data_sel =>usr_data_trans_phase_on
|
451 |
|
|
);
|
452 |
|
|
----------------------------------------------------------------------------------------------------
|
453 |
|
|
|
454 |
|
|
----------------------------------------------------------------------------------------------------
|
455 |
|
|
-- Component Name: ENABLE_USER_DATA_TRANSMISSION
|
456 |
|
|
-- Instance Name: ENABLE_USER_DATA_TRANSMISSION_port_map
|
457 |
|
|
-- Description: Sets usr_data_sel_sig signal to select user data for transmittion.
|
458 |
|
|
----------------------------------------------------------------------------------------------------
|
459 |
|
|
ENABLE_USER_DATA_TRANSMISSION_port_map: ENABLE_USER_DATA_TRANSMISSION port map
|
460 |
|
|
( rst =>rst,
|
461 |
|
|
clk =>clk_125MHz,
|
462 |
|
|
start_usr_data_trans =>start_usr_data_trans,
|
463 |
|
|
stop_usr_data_trans =>end_of_frame_O_tmp,
|
464 |
|
|
usr_data_sel =>usr_data_sel_sig
|
465 |
|
|
);
|
466 |
|
|
----------------------------------------------------------------------------------------------------
|
467 |
|
|
|
468 |
|
|
----------------------------------------------------------------------------------------------------
|
469 |
|
|
-- MUX 2 to 1
|
470 |
|
|
usr_data_not_sel_vec<=(others=>not usr_data_sel_sig);
|
471 |
|
|
usr_data_sel_vec<=(others=>usr_data_sel_sig);
|
472 |
|
|
|
473 |
|
|
-- MUX output
|
474 |
|
|
transmit_data_output_bus<=(transmit_data_output_bus_no_usr_data and usr_data_not_sel_vec) or
|
475 |
|
|
(transmit_data_input_bus and usr_data_sel_vec);
|
476 |
|
|
----------------------------------------------------------------------------------------------------
|
477 |
|
|
|
478 |
|
|
end Behavioral;
|