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[/] [pc_fpga_com/] [trunk/] [UDP_IP_CORE_FLEX_Virtex5/] [wraddr_lut_mem.vhd] - Blame information for rev 2

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Line No. Rev Author Line
1 2 NikosAl 
--------------------------------------------------------------------------------
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-- Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
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--------------------------------------------------------------------------------
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--   ____  ____
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--  /   /\/   /
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-- /___/  \  /    Vendor: Xilinx
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-- \   \   \/     Version: K.39
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--  \   \         Application: netgen
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--  /   /         Filename: wraddr_lut_mem.vhd
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-- /___/   /\     Timestamp: Sat Feb 12 13:38:28 2011
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-- \   \  /  \
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--  \___\/\___\
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--
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-- Command      : -intstyle ise -w -sim -ofmt vhdl "C:\VERIFICATION PLATFORM\UDP_IP_FLEX\COREGEN\tmp\_cg\wraddr_lut_mem.ngc" "C:\VERIFICATION PLATFORM\UDP_IP_FLEX\COREGEN\tmp\_cg\wraddr_lut_mem.vhd"
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-- Device       : 5vsx95tff1136-1
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-- Input file   : C:/VERIFICATION PLATFORM/UDP_IP_FLEX/COREGEN/tmp/_cg/wraddr_lut_mem.ngc
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-- Output file  : C:/VERIFICATION PLATFORM/UDP_IP_FLEX/COREGEN/tmp/_cg/wraddr_lut_mem.vhd
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-- # of Entities        : 1
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-- Design Name  : wraddr_lut_mem
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-- Xilinx       : C:\Xilinx\10.1\ISE
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--
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-- Purpose:
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--     This VHDL netlist is a verification model and uses simulation
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--     primitives which may not represent the true implementation of the
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--     device, however the netlist is functionally correct and should not
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--     be modified. This file cannot be synthesized and should only be used
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--     with supported simulation tools.
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--
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-- Reference:
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--     Development System Reference Guide, Chapter 23
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--     Synthesis and Simulation Design Guide, Chapter 6
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--
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--------------------------------------------------------------------------------
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35 
 
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-- synthesis translate_off
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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library UNISIM;
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use UNISIM.VCOMPONENTS.ALL;
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use UNISIM.VPKG.ALL;
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entity wraddr_lut_mem is
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  port (
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    clk : in STD_LOGIC := 'X';
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    a : in STD_LOGIC_VECTOR ( 5 downto 0 );
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    qspo : out STD_LOGIC_VECTOR ( 5 downto 0 )
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  );
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end wraddr_lut_mem;
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architecture STRUCTURE of wraddr_lut_mem is
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  signal N0 : STD_LOGIC;
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  signal N1 : STD_LOGIC;
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  signal a_2 : STD_LOGIC_VECTOR ( 5 downto 0 );
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  signal qspo_3 : STD_LOGIC_VECTOR ( 5 downto 0 );
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  signal BU2_U0_gen_rom_rom_inst_spo_int : STD_LOGIC_VECTOR ( 5 downto 0 );
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  signal BU2_qdpo : STD_LOGIC_VECTOR ( 0 downto 0 );
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begin
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  a_2(5) <= a(5);
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  a_2(4) <= a(4);
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  a_2(3) <= a(3);
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  a_2(2) <= a(2);
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  a_2(1) <= a(1);
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  a_2(0) <= a(0);
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  qspo(5) <= qspo_3(5);
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  qspo(4) <= qspo_3(4);
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  qspo(3) <= qspo_3(3);
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  qspo(2) <= qspo_3(2);
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  qspo(1) <= qspo_3(1);
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  qspo(0) <= qspo_3(0);
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  VCC_0 : VCC
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    port map (
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      P => N1
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    );
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  GND_1 : GND
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    port map (
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      G => N0
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    );
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  BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000041 : LUT5
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    generic map(
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      INIT => X"31266226"
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    )
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    port map (
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      I0 => a_2(4),
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      I1 => a_2(5),
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      I2 => a_2(1),
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      I3 => a_2(2),
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      I4 => a_2(3),
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      O => BU2_U0_gen_rom_rom_inst_spo_int(4)
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    );
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  BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000051 : LUT5
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    generic map(
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      INIT => X"16063662"
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    )
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    port map (
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      I0 => a_2(4),
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      I1 => a_2(5),
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      I2 => a_2(3),
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      I3 => a_2(2),
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      I4 => a_2(1),
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      O => BU2_U0_gen_rom_rom_inst_spo_int(5)
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    );
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  BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom0000111 : LUT5
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    generic map(
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      INIT => X"31276723"
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    )
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    port map (
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      I0 => a_2(4),
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      I1 => a_2(5),
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      I2 => a_2(1),
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      I3 => a_2(2),
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      I4 => a_2(3),
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      O => BU2_U0_gen_rom_rom_inst_spo_int(1)
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    );
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  BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000021 : LUT5
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    generic map(
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      INIT => X"13166627"
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    )
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    port map (
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      I0 => a_2(4),
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      I1 => a_2(5),
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      I2 => a_2(2),
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      I3 => a_2(1),
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      I4 => a_2(3),
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      O => BU2_U0_gen_rom_rom_inst_spo_int(2)
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    );
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  BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000031 : LUT5
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    generic map(
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      INIT => X"32166336"
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    )
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    port map (
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      I0 => a_2(4),
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      I1 => a_2(5),
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      I2 => a_2(2),
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      I3 => a_2(1),
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      I4 => a_2(3),
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      O => BU2_U0_gen_rom_rom_inst_spo_int(3)
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    );
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  BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000011 : LUT6
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    generic map(
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      INIT => X"1B161F061F043F2C"
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    )
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    port map (
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      I0 => a_2(3),
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      I1 => a_2(4),
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      I2 => a_2(5),
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      I3 => a_2(0),
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      I4 => a_2(1),
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      I5 => a_2(2),
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      O => BU2_U0_gen_rom_rom_inst_spo_int(0)
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    );
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  BU2_U0_gen_rom_rom_inst_qspo_int_5 : FD
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    generic map(
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      INIT => '0'
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    )
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    port map (
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      C => clk,
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      D => BU2_U0_gen_rom_rom_inst_spo_int(5),
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      Q => qspo_3(5)
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    );
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  BU2_U0_gen_rom_rom_inst_qspo_int_4 : FD
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    generic map(
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      INIT => '0'
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    )
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    port map (
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      C => clk,
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      D => BU2_U0_gen_rom_rom_inst_spo_int(4),
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      Q => qspo_3(4)
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    );
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  BU2_U0_gen_rom_rom_inst_qspo_int_3 : FD
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    generic map(
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      INIT => '0'
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    )
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    port map (
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      C => clk,
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      D => BU2_U0_gen_rom_rom_inst_spo_int(3),
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      Q => qspo_3(3)
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    );
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  BU2_U0_gen_rom_rom_inst_qspo_int_2 : FD
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    generic map(
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      INIT => '0'
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    )
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    port map (
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      C => clk,
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      D => BU2_U0_gen_rom_rom_inst_spo_int(2),
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      Q => qspo_3(2)
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    );
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  BU2_U0_gen_rom_rom_inst_qspo_int_1 : FD
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    generic map(
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      INIT => '0'
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    )
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    port map (
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      C => clk,
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      D => BU2_U0_gen_rom_rom_inst_spo_int(1),
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      Q => qspo_3(1)
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    );
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  BU2_U0_gen_rom_rom_inst_qspo_int_0 : FD
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    generic map(
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      INIT => '0'
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    )
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    port map (
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      C => clk,
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      D => BU2_U0_gen_rom_rom_inst_spo_int(0),
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      Q => qspo_3(0)
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    );
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  BU2_XST_GND : GND
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    port map (
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      G => BU2_qdpo(0)
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    );
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end STRUCTURE;
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-- synthesis translate_on

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