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[/] [pci/] [tags/] [asyst_2/] [rtl/] [verilog/] [pci_constants.v] - Blame information for rev 154

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Line No. Rev Author Line
1 18 mihad
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  File name "pci_constants.v"                                 ////
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////                                                              ////
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////  This file is part of the "PCI bridge" project               ////
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////  http://www.opencores.org/cores/pci/                         ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Miha Dolenc (mihad@opencores.org)                     ////
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////      - Tadej Markovic (tadej@opencores.org)                  ////
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////                                                              ////
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////  All additional information is avaliable in the README.txt   ////
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////  file.                                                       ////
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////                                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org          ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
46 132 mihad
// Revision 1.1  2002/02/01 14:43:31  mihad
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// *** empty log message ***
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//
49 18 mihad
// Revision 1.2  2001/10/05 08:14:28  mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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// Revision 1.1.1.1  2001/10/02 15:33:46  mihad
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// New project directory structure
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//
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// first include user definable parameters
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`ifdef REGRESSION // Used only for regression testing purposes!!!
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        `include "pci_regression_constants.v"
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`else
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        `include "pci_user_constants.v"
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`endif
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////////////////////////////////////////////////////////////////////////
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////                                                                ////
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//// FIFO parameters define behaviour of FIFO control logic and     ////
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//// FIFO depths.                                                   ////
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////                                                                ////
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////////////////////////////////////////////////////////////////////////
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`define WBW_DEPTH (1 << `WBW_ADDR_LENGTH)
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`define WBR_DEPTH (1 << `WBR_ADDR_LENGTH)
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`define PCIW_DEPTH (1 << `PCIW_ADDR_LENGTH)
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`define PCIR_DEPTH (1 << `PCIR_ADDR_LENGTH)
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// defines on which bit in control bus means what
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`define ADDR_CTRL_BIT 3
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`define LAST_CTRL_BIT 0
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`define DATA_ERROR_CTRL_BIT 1
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`define UNUSED_CTRL_BIT 2
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`define BURST_BIT 2
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// MAX Retry counter value for PCI Master state-machine
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//      This value is 8-bit because of 8-bit retry counter !!!
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//`define PCI_RTY_CNT_MAX                       8'h08
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// Value of address mask for WB configuration image. This has to be defined always, since it is a value, that is not changable in runtime.
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// !!!!!!!!!!!!!!!!!!!!!!!If this is not defined, WB configuration access will not be possible!!!!!!!!!!!!!!!!!!!!!1
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`define WB_AM0 20'hffff_f
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// PCI target & WB slave ADDRESS names for configuration space !!!
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// This does not include address offsets of PCI Header registers - they starts at offset 0 (see PCI spec.)
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//   ALL VALUES are without 2 LSBits AND there is required that address bit [8] is set while
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//   accessing this registers, otherwise the configuration header will be accessed !!!
93 132 mihad
`define PCI_CAP_PTR_VAL         8'h80
94 18 mihad
`define P_IMG_CTRL0_ADDR                6'h00   //      Address offset = h 100
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`define P_BA0_ADDR                              6'h01   //      Address offset = h 104
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`define P_AM0_ADDR                              6'h02   //      Address offset = h 108
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`define P_TA0_ADDR                              6'h03   //      Address offset = h 10c
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`define P_IMG_CTRL1_ADDR        6'h04   //      Address offset = h 110
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`define P_BA1_ADDR                              6'h05   //      Address offset = h 114
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`define P_AM1_ADDR                              6'h06   //      Address offset = h 118
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`define P_TA1_ADDR                              6'h07   //      Address offset = h 11c
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`define P_IMG_CTRL2_ADDR                6'h08   //      Address offset = h 120
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`define P_BA2_ADDR                              6'h09   //      Address offset = h 124
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`define P_AM2_ADDR                              6'h0a   //      Address offset = h 128
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`define P_TA2_ADDR                              6'h0b   //      Address offset = h 12c
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`define P_IMG_CTRL3_ADDR                6'h0c   //      Address offset = h 130
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`define P_BA3_ADDR                              6'h0d   //      Address offset = h 134
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`define P_AM3_ADDR                              6'h0e   //      Address offset = h 138
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`define P_TA3_ADDR                              6'h0f   //      Address offset = h 13c
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`define P_IMG_CTRL4_ADDR                6'h10   //      Address offset = h 140
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`define P_BA4_ADDR                              6'h11   //      Address offset = h 144
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`define P_AM4_ADDR                              6'h12   //      Address offset = h 148
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`define P_TA4_ADDR                              6'h13   //      Address offset = h 14c
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`define P_IMG_CTRL5_ADDR                6'h14   //      Address offset = h 150
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`define P_BA5_ADDR                              6'h15   //      Address offset = h 154
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`define P_AM5_ADDR                              6'h16   //      Address offset = h 158
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`define P_TA5_ADDR                              6'h17   //      Address offset = h 15c
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`define P_ERR_CS_ADDR                   6'h18   //      Address offset = h 160
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`define P_ERR_ADDR_ADDR                 6'h19   //      Address offset = h 164
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`define P_ERR_DATA_ADDR                 6'h1a   //      Address offset = h 168
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`define WB_CONF_SPC_BAR_ADDR    6'h20   //      Address offset = h 180
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`define W_IMG_CTRL1_ADDR                6'h21   //      Address offset = h 184
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`define W_BA1_ADDR                              6'h22   //      Address offset = h 188
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`define W_AM1_ADDR                              6'h23   //      Address offset = h 18c
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`define W_TA1_ADDR                              6'h24   //      Address offset = h 190
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`define W_IMG_CTRL2_ADDR                6'h25   //      Address offset = h 194
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`define W_BA2_ADDR                              6'h26   //      Address offset = h 198
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`define W_AM2_ADDR                              6'h27   //      Address offset = h 19c
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`define W_TA2_ADDR                              6'h28   //      Address offset = h 1a0
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`define W_IMG_CTRL3_ADDR                6'h29   //      Address offset = h 1a4
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`define W_BA3_ADDR                              6'h2a   //      Address offset = h 1a8
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`define W_AM3_ADDR                              6'h2b   //      Address offset = h 1ac
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`define W_TA3_ADDR                              6'h2c   //      Address offset = h 1b0
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`define W_IMG_CTRL4_ADDR                6'h2d   //      Address offset = h 1b4
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`define W_BA4_ADDR                              6'h2e   //      Address offset = h 1b8
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`define W_AM4_ADDR                              6'h2f   //      Address offset = h 1bc
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`define W_TA4_ADDR                              6'h30   //      Address offset = h 1c0
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`define W_IMG_CTRL5_ADDR                6'h31   //      Address offset = h 1c4
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`define W_BA5_ADDR                              6'h32   //      Address offset = h 1c8
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`define W_AM5_ADDR                              6'h33   //      Address offset = h 1cc
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`define W_TA5_ADDR                              6'h34   //      Address offset = h 1d0
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`define W_ERR_CS_ADDR                   6'h35   //      Address offset = h 1d4
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`define W_ERR_ADDR_ADDR                 6'h36   //      Address offset = h 1d8
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`define W_ERR_DATA_ADDR                 6'h37   //      Address offset = h 1dc
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`define CNF_ADDR_ADDR                   6'h38   //      Address offset = h 1e0
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// Following two registers are not implemented in a configuration space but in a WishBone unit!
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`define CNF_DATA_ADDR                   6'h39   //      Address offset = h 1e4
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`define INT_ACK_ADDR                    6'h3a   //      Address offset = h 1e8
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// -------------------------------------
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`define ICR_ADDR                                6'h3b   //      Address offset = h 1ec
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`define ISR_ADDR                        6'h3c   //      Address offset = h 1f0
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`ifdef PCI33
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    `define HEADER_66MHz        1'b0
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`else
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`ifdef PCI66
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    `define HEADER_66MHz        1'b1
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`endif
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`endif
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// all flip-flops in the design have this inter-assignment delay
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`define FF_DELAY 1
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