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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name "pci_io_mux.v"                                    ////
////                                                              ////
////  This file is part of the "PCI bridge" project               ////
////  http://www.opencores.org/cores/pci/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Miha Dolenc (mihad@opencores.org)                     ////
////                                                              ////
////  All additional information is avaliable in the README       ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4  2003/01/27 16:49:31  mihad
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
//
// Revision 1.3  2002/02/01 15:25:12  mihad
// Repaired a few bugs, updated specification, added test bench files and design document
//
// Revision 1.2  2001/10/05 08:14:29  mihad
// Updated all files with inclusion of timescale file for simulation purposes.
//
// Revision 1.1.1.1  2001/10/02 15:33:46  mihad
// New project directory structure
//
//
 
// this module instantiates output flip flops for PCI interface and
// some fanout downsizing logic because of heavily constrained PCI signals
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
module pci_io_mux
(
    reset_in,
    clk_in,
    frame_in,
    frame_en_in,
    frame_load_in,
    irdy_in,
    irdy_en_in,
    devsel_in,
    devsel_en_in,
    trdy_in,
    trdy_en_in,
    stop_in,
    stop_en_in,
    master_load_in,
    master_load_on_transfer_in,
    target_load_in,
    target_load_on_transfer_in,
    cbe_in,
    cbe_en_in,
    mas_ad_in,
    tar_ad_in,
 
    par_in,
    par_en_in,
    perr_in,
    perr_en_in,
    serr_in,
    serr_en_in,
 
    req_in,
 
    mas_ad_en_in,
    tar_ad_en_in,
    tar_ad_en_reg_in,
 
    ad_en_out,
    frame_en_out,
    irdy_en_out,
    devsel_en_out,
    trdy_en_out,
    stop_en_out,
    cbe_en_out,
 
    frame_out,
    irdy_out,
    devsel_out,
    trdy_out,
    stop_out,
    cbe_out,
    ad_out,
    ad_load_out,
    ad_en_unregistered_out,
 
    par_out,
    par_en_out,
    perr_out,
    perr_en_out,
    serr_out,
    serr_en_out,
 
    req_out,
    req_en_out,
    pci_trdy_in,
    pci_irdy_in,
    pci_frame_in,
    pci_stop_in,
 
    init_complete_in
);
 
input reset_in, clk_in ;
 
input           frame_in ;
input           frame_en_in ;
input           frame_load_in ;
input           irdy_in ;
input           irdy_en_in ;
input           devsel_in ;
input           devsel_en_in ;
input           trdy_in ;
input           trdy_en_in ;
input           stop_in ;
input           stop_en_in ;
input           master_load_in ;
input           target_load_in ;
 
input [3:0]     cbe_in ;
input           cbe_en_in ;
input [31:0]    mas_ad_in ;
input [31:0]    tar_ad_in ;
 
input           mas_ad_en_in ;
input           tar_ad_en_in ;
input           tar_ad_en_reg_in ;
 
input par_in ;
input par_en_in ;
input perr_in ;
input perr_en_in ;
input serr_in ;
input serr_en_in ;
 
output          frame_en_out ;
output          irdy_en_out ;
output          devsel_en_out ;
output          trdy_en_out ;
output          stop_en_out ;
output [31:0]   ad_en_out ;
output [3:0]    cbe_en_out ;
 
output          frame_out ;
output          irdy_out ;
output          devsel_out ;
output          trdy_out ;
output          stop_out ;
output [3:0]    cbe_out ;
output [31:0]   ad_out ;
output          ad_load_out ;
output          ad_en_unregistered_out ;
 
output          par_out ;
output          par_en_out ;
output          perr_out ;
output          perr_en_out ;
output          serr_out ;
output          serr_en_out ;
 
input           req_in ;
 
output          req_out ;
output          req_en_out ;
 
input           pci_trdy_in,
                pci_irdy_in,
                pci_frame_in,
                pci_stop_in ;
 
input           master_load_on_transfer_in ;
input           target_load_on_transfer_in ;
 
input           init_complete_in    ;
 
wire   [31:0]   temp_ad = tar_ad_en_reg_in ? tar_ad_in : mas_ad_in ;
 
wire ad_en_ctrl_low ;
 
wire ad_en_ctrl_mlow ;
 
wire ad_en_ctrl_mhigh ;
 
wire ad_en_ctrl_high ;
 
wire ad_enable_internal = mas_ad_en_in || tar_ad_en_in ;
 
pci_io_mux_ad_en_crit ad_en_low_gen
(
    .ad_en_in       (ad_enable_internal),
    .pci_frame_in   (pci_frame_in),
    .pci_trdy_in    (pci_trdy_in),
    .pci_stop_in    (pci_stop_in),
    .ad_en_out      (ad_en_ctrl_low)
);
 
pci_io_mux_ad_en_crit ad_en_mlow_gen
(
    .ad_en_in       (ad_enable_internal),
    .pci_frame_in   (pci_frame_in),
    .pci_trdy_in    (pci_trdy_in),
    .pci_stop_in    (pci_stop_in),
    .ad_en_out      (ad_en_ctrl_mlow)
);
 
pci_io_mux_ad_en_crit ad_en_mhigh_gen
(
    .ad_en_in       (ad_enable_internal),
    .pci_frame_in   (pci_frame_in),
    .pci_trdy_in    (pci_trdy_in),
    .pci_stop_in    (pci_stop_in),
    .ad_en_out      (ad_en_ctrl_mhigh)
);
 
pci_io_mux_ad_en_crit ad_en_high_gen
(
    .ad_en_in       (ad_enable_internal),
    .pci_frame_in   (pci_frame_in),
    .pci_trdy_in    (pci_trdy_in),
    .pci_stop_in    (pci_stop_in),
    .ad_en_out      (ad_en_ctrl_high)
);
 
assign ad_en_unregistered_out = ad_en_ctrl_high ;
 
wire load = master_load_in || target_load_in ;
wire load_on_transfer = master_load_on_transfer_in || target_load_on_transfer_in ;
 
wire   ad_load_ctrl_low ;
wire   ad_load_ctrl_mlow ;
wire   ad_load_ctrl_mhigh ;
wire   ad_load_ctrl_high ;
 
assign ad_load_out = ad_load_ctrl_high ;
 
pci_io_mux_ad_load_crit ad_load_low_gen
(
    .load_in(load),
    .load_on_transfer_in(load_on_transfer),
    .pci_irdy_in(pci_irdy_in),
    .pci_trdy_in(pci_trdy_in),
    .load_out(ad_load_ctrl_low)
);
 
pci_io_mux_ad_load_crit ad_load_mlow_gen
(
    .load_in(load),
    .load_on_transfer_in(load_on_transfer),
    .pci_irdy_in(pci_irdy_in),
    .pci_trdy_in(pci_trdy_in),
    .load_out(ad_load_ctrl_mlow)
);
 
pci_io_mux_ad_load_crit ad_load_mhigh_gen
(
    .load_in(load),
    .load_on_transfer_in(load_on_transfer),
    .pci_irdy_in(pci_irdy_in),
    .pci_trdy_in(pci_trdy_in),
    .load_out(ad_load_ctrl_mhigh)
);
 
pci_io_mux_ad_load_crit ad_load_high_gen
(
    .load_in(load),
    .load_on_transfer_in(load_on_transfer),
    .pci_irdy_in(pci_irdy_in),
    .pci_trdy_in(pci_trdy_in),
    .load_out(ad_load_ctrl_high)
);
 
pci_out_reg ad_iob0
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_low ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[0] ) ,
    .en_in        ( ad_en_ctrl_low ) ,
    .en_out       ( ad_en_out[0] ),
    .dat_out      ( ad_out[0] )
);
 
pci_out_reg ad_iob1
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_low ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[1] ) ,
    .en_in        ( ad_en_ctrl_low ) ,
    .en_out       ( ad_en_out[1] ),
    .dat_out      ( ad_out[1] )
);
 
pci_out_reg ad_iob2
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_low ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[2] ) ,
    .en_in        ( ad_en_ctrl_low ) ,
    .en_out       ( ad_en_out[2] ),
    .dat_out      ( ad_out[2] )
);
 
pci_out_reg ad_iob3
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_low ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[3] ) ,
    .en_in        ( ad_en_ctrl_low ) ,
    .en_out       ( ad_en_out[3] ),
    .dat_out      ( ad_out[3] )
);
 
pci_out_reg ad_iob4
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_low ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[4] ) ,
    .en_in        ( ad_en_ctrl_low ) ,
    .en_out       ( ad_en_out[4] ),
    .dat_out      ( ad_out[4] )
);
 
pci_out_reg ad_iob5
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_low ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[5] ) ,
    .en_in        ( ad_en_ctrl_low ) ,
    .en_out       ( ad_en_out[5] ),
    .dat_out      ( ad_out[5] )
);
 
pci_out_reg ad_iob6
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_low ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[6] ) ,
    .en_in        ( ad_en_ctrl_low ) ,
    .en_out       ( ad_en_out[6] ),
    .dat_out      ( ad_out[6] )
);
 
pci_out_reg ad_iob7
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_low ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[7] ) ,
    .en_in        ( ad_en_ctrl_low ) ,
    .en_out       ( ad_en_out[7] ),
    .dat_out      ( ad_out[7] )
);
 
pci_out_reg ad_iob8
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mlow ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[8] ) ,
    .en_in        ( ad_en_ctrl_mlow ) ,
    .en_out       ( ad_en_out[8] ),
    .dat_out      ( ad_out[8] )
);
 
pci_out_reg ad_iob9
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mlow ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[9] ) ,
    .en_in        ( ad_en_ctrl_mlow ) ,
    .en_out       ( ad_en_out[9] ),
    .dat_out      ( ad_out[9] )
);
 
pci_out_reg ad_iob10
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mlow ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[10] ) ,
    .en_in        ( ad_en_ctrl_mlow ) ,
    .en_out       ( ad_en_out[10] ),
    .dat_out      ( ad_out[10] )
);
 
pci_out_reg ad_iob11
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mlow ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[11] ) ,
    .en_in        ( ad_en_ctrl_mlow ) ,
    .en_out       ( ad_en_out[11] ),
    .dat_out      ( ad_out[11] )
);
 
pci_out_reg ad_iob12
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mlow ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[12] ) ,
    .en_in        ( ad_en_ctrl_mlow ) ,
    .en_out       ( ad_en_out[12] ),
    .dat_out      ( ad_out[12] )
);
 
pci_out_reg ad_iob13
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mlow ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[13] ) ,
    .en_in        ( ad_en_ctrl_mlow ) ,
    .en_out       ( ad_en_out[13] ),
    .dat_out      ( ad_out[13] )
);
 
pci_out_reg ad_iob14
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mlow ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[14] ) ,
    .en_in        ( ad_en_ctrl_mlow ) ,
    .en_out       ( ad_en_out[14] ),
    .dat_out      ( ad_out[14] )
);
 
pci_out_reg ad_iob15
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mlow ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[15] ) ,
    .en_in        ( ad_en_ctrl_mlow ) ,
    .en_out       ( ad_en_out[15] ),
    .dat_out      ( ad_out[15] )
);
 
pci_out_reg ad_iob16
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mhigh ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[16] ) ,
    .en_in        ( ad_en_ctrl_mhigh ) ,
    .en_out       ( ad_en_out[16] ),
    .dat_out      ( ad_out[16] )
);
 
pci_out_reg ad_iob17
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mhigh ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[17] ) ,
    .en_in        ( ad_en_ctrl_mhigh ) ,
    .en_out       ( ad_en_out[17] ),
    .dat_out      ( ad_out[17] )
);
 
pci_out_reg ad_iob18
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mhigh ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[18] ) ,
    .en_in        ( ad_en_ctrl_mhigh ) ,
    .en_out       ( ad_en_out[18] ),
    .dat_out      ( ad_out[18] )
);
 
pci_out_reg ad_iob19
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mhigh ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[19] ) ,
    .en_in        ( ad_en_ctrl_mhigh ) ,
    .en_out       ( ad_en_out[19] ),
    .dat_out      ( ad_out[19] )
);
 
pci_out_reg ad_iob20
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mhigh ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[20] ) ,
    .en_in        ( ad_en_ctrl_mhigh ) ,
    .en_out       ( ad_en_out[20] ),
    .dat_out      ( ad_out[20] )
);
 
pci_out_reg ad_iob21
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mhigh ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[21] ) ,
    .en_in        ( ad_en_ctrl_mhigh ) ,
    .en_out       ( ad_en_out[21] ),
    .dat_out      ( ad_out[21] )
);
 
pci_out_reg ad_iob22
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mhigh ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[22] ) ,
    .en_in        ( ad_en_ctrl_mhigh ) ,
    .en_out       ( ad_en_out[22] ),
    .dat_out      ( ad_out[22] )
);
 
pci_out_reg ad_iob23
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mhigh ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[23] ) ,
    .en_in        ( ad_en_ctrl_mhigh ) ,
    .en_out       ( ad_en_out[23] ),
    .dat_out      ( ad_out[23] )
);
 
pci_out_reg ad_iob24
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_high ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[24] ) ,
    .en_in        ( ad_en_ctrl_high ) ,
    .en_out       ( ad_en_out[24] ),
    .dat_out      ( ad_out[24] )
);
 
pci_out_reg ad_iob25
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_high ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[25] ) ,
    .en_in        ( ad_en_ctrl_high ) ,
    .en_out       ( ad_en_out[25] ),
    .dat_out      ( ad_out[25] )
);
 
pci_out_reg ad_iob26
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_high ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[26] ) ,
    .en_in        ( ad_en_ctrl_high ) ,
    .en_out       ( ad_en_out[26] ),
    .dat_out      ( ad_out[26] )
);
 
pci_out_reg ad_iob27
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_high ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[27] ) ,
    .en_in        ( ad_en_ctrl_high ) ,
    .en_out       ( ad_en_out[27] ),
    .dat_out      ( ad_out[27] )
);
 
pci_out_reg ad_iob28
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_high ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[28] ) ,
    .en_in        ( ad_en_ctrl_high ) ,
    .en_out       ( ad_en_out[28] ),
    .dat_out      ( ad_out[28] )
);
 
pci_out_reg ad_iob29
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_high ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[29] ) ,
    .en_in        ( ad_en_ctrl_high ) ,
    .en_out       ( ad_en_out[29] ),
    .dat_out      ( ad_out[29] )
);
 
pci_out_reg ad_iob30
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_high ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[30] ) ,
    .en_in        ( ad_en_ctrl_high ) ,
    .en_out       ( ad_en_out[30] ),
    .dat_out      ( ad_out[30] )
);
 
pci_out_reg ad_iob31
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_high ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[31] ) ,
    .en_in        ( ad_en_ctrl_high ) ,
    .en_out       ( ad_en_out[31] ),
    .dat_out      ( ad_out[31] )
);
 
wire [3:0] cbe_load_ctrl = {4{ master_load_in }} ;
wire [3:0] cbe_en_ctrl   = {4{ cbe_en_in }} ;
 
pci_out_reg cbe_iob0
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( cbe_load_ctrl[0] ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( cbe_in[0] ) ,
    .en_in        ( cbe_en_ctrl[0] ) ,
    .en_out       ( cbe_en_out[0] ),
    .dat_out      ( cbe_out[0] )
);
 
pci_out_reg cbe_iob1
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( cbe_load_ctrl[1] ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( cbe_in[1] ) ,
    .en_in        ( cbe_en_ctrl[1] ) ,
    .en_out       ( cbe_en_out[1] ),
    .dat_out      ( cbe_out[1] )
);
 
pci_out_reg cbe_iob2
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( cbe_load_ctrl[2] ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( cbe_in[2] ) ,
    .en_in        ( cbe_en_ctrl[2] ) ,
    .en_out       ( cbe_en_out[2] ),
    .dat_out      ( cbe_out[2] )
);
 
pci_out_reg cbe_iob3
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( cbe_load_ctrl[3] ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( cbe_in[3] ) ,
    .en_in        ( cbe_en_ctrl[3] ) ,
    .en_out       ( cbe_en_out[3] ),
    .dat_out      ( cbe_out[3] )
);
 
pci_out_reg frame_iob
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( frame_load_in ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( frame_in ) ,
    .en_in        ( frame_en_in ) ,
    .en_out       ( frame_en_out ),
    .dat_out      ( frame_out )
);
 
pci_out_reg irdy_iob
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( 1'b1 ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( irdy_in ) ,
    .en_in        ( irdy_en_in ) ,
    .en_out       ( irdy_en_out ),
    .dat_out      ( irdy_out )
);
 
pci_out_reg trdy_iob
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( 1'b1 ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( trdy_in ) ,
    .en_in        ( trdy_en_in ) ,
    .en_out       ( trdy_en_out ),
    .dat_out      ( trdy_out )
);
 
pci_out_reg stop_iob
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( 1'b1 ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( stop_in ) ,
    .en_in        ( stop_en_in ) ,
    .en_out       ( stop_en_out ),
    .dat_out      ( stop_out )
);
 
pci_out_reg devsel_iob
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( 1'b1 ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( devsel_in ) ,
    .en_in        ( devsel_en_in ) ,
    .en_out       ( devsel_en_out ),
    .dat_out      ( devsel_out )
);
 
pci_out_reg par_iob
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( 1'b1 ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( par_in ) ,
    .en_in        ( par_en_in ) ,
    .en_out       ( par_en_out ),
    .dat_out      ( par_out )
);
 
pci_out_reg perr_iob
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( 1'b1 ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( perr_in ) ,
    .en_in        ( perr_en_in ) ,
    .en_out       ( perr_en_out ),
    .dat_out      ( perr_out )
);
 
pci_out_reg serr_iob
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( 1'b1 ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( serr_in ) ,
    .en_in        ( serr_en_in ) ,
    .en_out       ( serr_en_out ),
    .dat_out      ( serr_out )
);
 
pci_out_reg req_iob
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( 1'b1 ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( req_in ) ,
    .en_in        ( init_complete_in ) ,
    .en_out       ( req_en_out ),
    .dat_out      ( req_out )
);
 
endmodule

Line No.	Rev	Author	Line
1	2	mihad	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// File name "pci_io_mux.v" ////`
4			`//// ////`
5			`//// This file is part of the "PCI bridge" project ////`
6			`//// http://www.opencores.org/cores/pci/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Miha Dolenc (mihad@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the README ////`
12			`//// file. ////`
13			`//// ////`
14			`//// ////`
15			`//////////////////////////////////////////////////////////////////////`
16			`//// ////`
17			`//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////`
18			`//// ////`
19			`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer. ////`
23			`//// ////`
24			`//// This source file is free software; you can redistribute it ////`
25			`//// and/or modify it under the terms of the GNU Lesser General ////`
26			`//// Public License as published by the Free Software Foundation; ////`
27			`//// either version 2.1 of the License, or (at your option) any ////`
28			`//// later version. ////`
29			`//// ////`
30			`//// This source is distributed in the hope that it will be ////`
31			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
32			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
33			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
34			`//// details. ////`
35			`//// ////`
36			`//// You should have received a copy of the GNU Lesser General ////`
37			`//// Public License along with this source; if not, download it ////`
38			`//// from http://www.opencores.org/lgpl.shtml ////`
39			`//// ////`
40			`//////////////////////////////////////////////////////////////////////`
41			`//`
42			`// CVS Revision History`
43			`//`
44			`// $Log: not supported by cvs2svn $`
45	132	mihad	`// Revision 1.4 2003/01/27 16:49:31 mihad`
46			`// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.`
47			`//`
48	77	mihad	`// Revision 1.3 2002/02/01 15:25:12 mihad`
49			`// Repaired a few bugs, updated specification, added test bench files and design document`
50			`//`
51	21	mihad	`// Revision 1.2 2001/10/05 08:14:29 mihad`
52			`// Updated all files with inclusion of timescale file for simulation purposes.`
53			`//`
54	6	mihad	`// Revision 1.1.1.1 2001/10/02 15:33:46 mihad`
55			`// New project directory structure`
56	2	mihad	`//`
57	6	mihad	`//`
58	2	mihad
59			`// this module instantiates output flip flops for PCI interface and`
60			`// some fanout downsizing logic because of heavily constrained PCI signals`
61	21	mihad
62			`// synopsys translate_off`
63	6	mihad	`include "timescale.v"
64	21	mihad	`// synopsys translate_on`
65	6	mihad
66	77	mihad	`module pci_io_mux`
67	2	mihad	`(`
68			`reset_in,`
69			`clk_in,`
70			`frame_in,`
71			`frame_en_in,`
72			`frame_load_in,`
73			`irdy_in,`
74			`irdy_en_in,`
75			`devsel_in,`
76			`devsel_en_in,`
77			`trdy_in,`
78			`trdy_en_in,`
79			`stop_in,`
80			`stop_en_in,`
81			`master_load_in,`
82	21	mihad	`master_load_on_transfer_in,`
83	2	mihad	`target_load_in,`
84	21	mihad	`target_load_on_transfer_in,`
85	2	mihad	`cbe_in,`
86			`cbe_en_in,`
87			`mas_ad_in,`
88			`tar_ad_in,`
89
90			`par_in,`
91			`par_en_in,`
92			`perr_in,`
93			`perr_en_in,`
94			`serr_in,`
95			`serr_en_in,`
96
97			`req_in,`
98	21	mihad
99	2	mihad	`mas_ad_en_in,`
100			`tar_ad_en_in,`
101			`tar_ad_en_reg_in,`
102	21	mihad
103	2	mihad	`ad_en_out,`
104			`frame_en_out,`
105			`irdy_en_out,`
106			`devsel_en_out,`
107			`trdy_en_out,`
108			`stop_en_out,`
109			`cbe_en_out,`
110
111			`frame_out,`
112			`irdy_out,`
113			`devsel_out,`
114			`trdy_out,`
115			`stop_out,`
116			`cbe_out,`
117			`ad_out,`
118	21	mihad	`ad_load_out,`
119			`ad_en_unregistered_out,`
120
121	2	mihad	`par_out,`
122			`par_en_out,`
123			`perr_out,`
124			`perr_en_out,`
125			`serr_out,`
126			`serr_en_out,`
127
128			`req_out,`
129	21	mihad	`req_en_out,`
130			`pci_trdy_in,`
131			`pci_irdy_in,`
132			`pci_frame_in,`
133	132	mihad	`pci_stop_in,`
134
135			`init_complete_in`
136	2	mihad	`);`
137
138			`input reset_in, clk_in ;`
139
140			`input frame_in ;`
141			`input frame_en_in ;`
142			`input frame_load_in ;`
143			`input irdy_in ;`
144			`input irdy_en_in ;`
145			`input devsel_in ;`
146			`input devsel_en_in ;`
147			`input trdy_in ;`
148			`input trdy_en_in ;`
149			`input stop_in ;`
150			`input stop_en_in ;`
151			`input master_load_in ;`
152			`input target_load_in ;`
153
154			`input [3:0] cbe_in ;`
155			`input cbe_en_in ;`
156			`input [31:0] mas_ad_in ;`
157			`input [31:0] tar_ad_in ;`
158
159			`input mas_ad_en_in ;`
160			`input tar_ad_en_in ;`
161			`input tar_ad_en_reg_in ;`
162
163			`input par_in ;`
164			`input par_en_in ;`
165	21	mihad	`input perr_in ;`
166	2	mihad	`input perr_en_in ;`
167	21	mihad	`input serr_in ;`
168	2	mihad	`input serr_en_in ;`
169
170			`output frame_en_out ;`
171			`output irdy_en_out ;`
172			`output devsel_en_out ;`
173			`output trdy_en_out ;`
174			`output stop_en_out ;`
175			`output [31:0] ad_en_out ;`
176			`output [3:0] cbe_en_out ;`
177
178			`output frame_out ;`
179			`output irdy_out ;`
180			`output devsel_out ;`
181			`output trdy_out ;`
182			`output stop_out ;`
183			`output [3:0] cbe_out ;`
184			`output [31:0] ad_out ;`
185	21	mihad	`output ad_load_out ;`
186			`output ad_en_unregistered_out ;`
187	2	mihad
188			`output par_out ;`
189			`output par_en_out ;`
190	21	mihad	`output perr_out ;`
191	2	mihad	`output perr_en_out ;`
192	21	mihad	`output serr_out ;`
193	2	mihad	`output serr_en_out ;`
194
195			`input req_in ;`
196
197			`output req_out ;`
198			`output req_en_out ;`
199
200	21	mihad	`input pci_trdy_in,`
201			`pci_irdy_in,`
202			`pci_frame_in,`
203			`pci_stop_in ;`
204	2	mihad
205	21	mihad	`input master_load_on_transfer_in ;`
206			`input target_load_on_transfer_in ;`
207
208	132	mihad	`input init_complete_in ;`
209
210	2	mihad	`wire [31:0] temp_ad = tar_ad_en_reg_in ? tar_ad_in : mas_ad_in ;`
211
212			`wire ad_en_ctrl_low ;`
213
214			`wire ad_en_ctrl_mlow ;`
215
216			`wire ad_en_ctrl_mhigh ;`
217
218			`wire ad_en_ctrl_high ;`
219
220	21	mihad	`wire ad_enable_internal = mas_ad_en_in \|\| tar_ad_en_in ;`
221	2	mihad
222	77	mihad	`pci_io_mux_ad_en_crit ad_en_low_gen`
223	21	mihad	`(`
224			`.ad_en_in (ad_enable_internal),`
225			`.pci_frame_in (pci_frame_in),`
226			`.pci_trdy_in (pci_trdy_in),`
227			`.pci_stop_in (pci_stop_in),`
228			`.ad_en_out (ad_en_ctrl_low)`
229			`);`
230	2	mihad
231	77	mihad	`pci_io_mux_ad_en_crit ad_en_mlow_gen`
232	21	mihad	`(`
233			`.ad_en_in (ad_enable_internal),`
234			`.pci_frame_in (pci_frame_in),`
235			`.pci_trdy_in (pci_trdy_in),`
236			`.pci_stop_in (pci_stop_in),`
237			`.ad_en_out (ad_en_ctrl_mlow)`
238			`);`
239	2	mihad
240	77	mihad	`pci_io_mux_ad_en_crit ad_en_mhigh_gen`
241	21	mihad	`(`
242			`.ad_en_in (ad_enable_internal),`
243			`.pci_frame_in (pci_frame_in),`
244			`.pci_trdy_in (pci_trdy_in),`
245			`.pci_stop_in (pci_stop_in),`
246			`.ad_en_out (ad_en_ctrl_mhigh)`
247			`);`
248	2	mihad
249	77	mihad	`pci_io_mux_ad_en_crit ad_en_high_gen`
250	21	mihad	`(`
251			`.ad_en_in (ad_enable_internal),`
252			`.pci_frame_in (pci_frame_in),`
253			`.pci_trdy_in (pci_trdy_in),`
254			`.pci_stop_in (pci_stop_in),`
255			`.ad_en_out (ad_en_ctrl_high)`
256			`);`
257
258			`assign ad_en_unregistered_out = ad_en_ctrl_high ;`
259
260			`wire load = master_load_in \|\| target_load_in ;`
261			`wire load_on_transfer = master_load_on_transfer_in \|\| target_load_on_transfer_in ;`
262
263			`wire ad_load_ctrl_low ;`
264			`wire ad_load_ctrl_mlow ;`
265			`wire ad_load_ctrl_mhigh ;`
266			`wire ad_load_ctrl_high ;`
267
268			`assign ad_load_out = ad_load_ctrl_high ;`
269
270	77	mihad	`pci_io_mux_ad_load_crit ad_load_low_gen`
271	21	mihad	`(`
272			`.load_in(load),`
273			`.load_on_transfer_in(load_on_transfer),`
274			`.pci_irdy_in(pci_irdy_in),`
275			`.pci_trdy_in(pci_trdy_in),`
276			`.load_out(ad_load_ctrl_low)`
277			`);`
278
279	77	mihad	`pci_io_mux_ad_load_crit ad_load_mlow_gen`
280	21	mihad	`(`
281			`.load_in(load),`
282			`.load_on_transfer_in(load_on_transfer),`
283			`.pci_irdy_in(pci_irdy_in),`
284			`.pci_trdy_in(pci_trdy_in),`
285			`.load_out(ad_load_ctrl_mlow)`
286			`);`
287
288	77	mihad	`pci_io_mux_ad_load_crit ad_load_mhigh_gen`
289	21	mihad	`(`
290			`.load_in(load),`
291			`.load_on_transfer_in(load_on_transfer),`
292			`.pci_irdy_in(pci_irdy_in),`
293			`.pci_trdy_in(pci_trdy_in),`
294			`.load_out(ad_load_ctrl_mhigh)`
295			`);`
296
297	77	mihad	`pci_io_mux_ad_load_crit ad_load_high_gen`
298	21	mihad	`(`
299			`.load_in(load),`
300			`.load_on_transfer_in(load_on_transfer),`
301			`.pci_irdy_in(pci_irdy_in),`
302			`.pci_trdy_in(pci_trdy_in),`
303			`.load_out(ad_load_ctrl_high)`
304			`);`
305
306	77	mihad	`pci_out_reg ad_iob0`
307	21	mihad	`(`
308	2	mihad	`.reset_in ( reset_in ),`
309			`.clk_in ( clk_in) ,`
310			`.dat_en_in ( ad_load_ctrl_low ),`
311			`.en_en_in ( 1'b1 ),`
312			`.dat_in ( temp_ad[0] ) ,`
313			`.en_in ( ad_en_ctrl_low ) ,`
314			`.en_out ( ad_en_out[0] ),`
315			`.dat_out ( ad_out[0] )`
316			`);`
317
318	77	mihad	`pci_out_reg ad_iob1`
319	21	mihad	`(`
320	2	mihad	`.reset_in ( reset_in ),`
321			`.clk_in ( clk_in) ,`
322			`.dat_en_in ( ad_load_ctrl_low ),`
323			`.en_en_in ( 1'b1 ),`
324			`.dat_in ( temp_ad[1] ) ,`
325			`.en_in ( ad_en_ctrl_low ) ,`
326			`.en_out ( ad_en_out[1] ),`
327			`.dat_out ( ad_out[1] )`
328			`);`
329
330	77	mihad	`pci_out_reg ad_iob2`
331	21	mihad	`(`
332	2	mihad	`.reset_in ( reset_in ),`
333			`.clk_in ( clk_in) ,`
334			`.dat_en_in ( ad_load_ctrl_low ),`
335			`.en_en_in ( 1'b1 ),`
336			`.dat_in ( temp_ad[2] ) ,`
337			`.en_in ( ad_en_ctrl_low ) ,`
338			`.en_out ( ad_en_out[2] ),`
339			`.dat_out ( ad_out[2] )`
340			`);`
341
342	77	mihad	`pci_out_reg ad_iob3`
343	21	mihad	`(`
344	2	mihad	`.reset_in ( reset_in ),`
345			`.clk_in ( clk_in) ,`
346			`.dat_en_in ( ad_load_ctrl_low ),`
347			`.en_en_in ( 1'b1 ),`
348			`.dat_in ( temp_ad[3] ) ,`
349			`.en_in ( ad_en_ctrl_low ) ,`
350			`.en_out ( ad_en_out[3] ),`
351			`.dat_out ( ad_out[3] )`
352			`);`
353
354	77	mihad	`pci_out_reg ad_iob4`
355	21	mihad	`(`
356	2	mihad	`.reset_in ( reset_in ),`
357			`.clk_in ( clk_in) ,`
358			`.dat_en_in ( ad_load_ctrl_low ),`
359			`.en_en_in ( 1'b1 ),`
360			`.dat_in ( temp_ad[4] ) ,`
361			`.en_in ( ad_en_ctrl_low ) ,`
362			`.en_out ( ad_en_out[4] ),`
363			`.dat_out ( ad_out[4] )`
364			`);`
365
366	77	mihad	`pci_out_reg ad_iob5`
367	21	mihad	`(`
368	2	mihad	`.reset_in ( reset_in ),`
369			`.clk_in ( clk_in) ,`
370			`.dat_en_in ( ad_load_ctrl_low ),`
371			`.en_en_in ( 1'b1 ),`
372			`.dat_in ( temp_ad[5] ) ,`
373			`.en_in ( ad_en_ctrl_low ) ,`
374			`.en_out ( ad_en_out[5] ),`
375			`.dat_out ( ad_out[5] )`
376			`);`
377
378	77	mihad	`pci_out_reg ad_iob6`
379	21	mihad	`(`
380	2	mihad	`.reset_in ( reset_in ),`
381			`.clk_in ( clk_in) ,`
382			`.dat_en_in ( ad_load_ctrl_low ),`
383			`.en_en_in ( 1'b1 ),`
384			`.dat_in ( temp_ad[6] ) ,`
385			`.en_in ( ad_en_ctrl_low ) ,`
386			`.en_out ( ad_en_out[6] ),`
387			`.dat_out ( ad_out[6] )`
388			`);`
389
390	77	mihad	`pci_out_reg ad_iob7`
391	21	mihad	`(`
392	2	mihad	`.reset_in ( reset_in ),`
393			`.clk_in ( clk_in) ,`
394			`.dat_en_in ( ad_load_ctrl_low ),`
395			`.en_en_in ( 1'b1 ),`
396			`.dat_in ( temp_ad[7] ) ,`
397			`.en_in ( ad_en_ctrl_low ) ,`
398			`.en_out ( ad_en_out[7] ),`
399			`.dat_out ( ad_out[7] )`
400			`);`
401
402	77	mihad	`pci_out_reg ad_iob8`
403	21	mihad	`(`
404	2	mihad	`.reset_in ( reset_in ),`
405			`.clk_in ( clk_in) ,`
406			`.dat_en_in ( ad_load_ctrl_mlow ),`
407			`.en_en_in ( 1'b1 ),`
408			`.dat_in ( temp_ad[8] ) ,`
409			`.en_in ( ad_en_ctrl_mlow ) ,`
410			`.en_out ( ad_en_out[8] ),`
411			`.dat_out ( ad_out[8] )`
412			`);`
413
414	77	mihad	`pci_out_reg ad_iob9`
415	21	mihad	`(`
416	2	mihad	`.reset_in ( reset_in ),`
417			`.clk_in ( clk_in) ,`
418			`.dat_en_in ( ad_load_ctrl_mlow ),`
419			`.en_en_in ( 1'b1 ),`
420			`.dat_in ( temp_ad[9] ) ,`
421			`.en_in ( ad_en_ctrl_mlow ) ,`
422			`.en_out ( ad_en_out[9] ),`
423			`.dat_out ( ad_out[9] )`
424			`);`
425
426	77	mihad	`pci_out_reg ad_iob10`
427	21	mihad	`(`
428	2	mihad	`.reset_in ( reset_in ),`
429			`.clk_in ( clk_in) ,`
430			`.dat_en_in ( ad_load_ctrl_mlow ),`
431			`.en_en_in ( 1'b1 ),`
432			`.dat_in ( temp_ad[10] ) ,`
433			`.en_in ( ad_en_ctrl_mlow ) ,`
434			`.en_out ( ad_en_out[10] ),`
435			`.dat_out ( ad_out[10] )`
436			`);`
437
438	77	mihad	`pci_out_reg ad_iob11`
439	21	mihad	`(`
440	2	mihad	`.reset_in ( reset_in ),`
441			`.clk_in ( clk_in) ,`
442			`.dat_en_in ( ad_load_ctrl_mlow ),`
443			`.en_en_in ( 1'b1 ),`
444			`.dat_in ( temp_ad[11] ) ,`
445			`.en_in ( ad_en_ctrl_mlow ) ,`
446			`.en_out ( ad_en_out[11] ),`
447			`.dat_out ( ad_out[11] )`
448			`);`
449
450	77	mihad	`pci_out_reg ad_iob12`
451	21	mihad	`(`
452	2	mihad	`.reset_in ( reset_in ),`
453			`.clk_in ( clk_in) ,`
454			`.dat_en_in ( ad_load_ctrl_mlow ),`
455			`.en_en_in ( 1'b1 ),`
456			`.dat_in ( temp_ad[12] ) ,`
457			`.en_in ( ad_en_ctrl_mlow ) ,`
458			`.en_out ( ad_en_out[12] ),`
459			`.dat_out ( ad_out[12] )`
460			`);`
461
462	77	mihad	`pci_out_reg ad_iob13`
463	21	mihad	`(`
464	2	mihad	`.reset_in ( reset_in ),`
465			`.clk_in ( clk_in) ,`
466			`.dat_en_in ( ad_load_ctrl_mlow ),`
467			`.en_en_in ( 1'b1 ),`
468			`.dat_in ( temp_ad[13] ) ,`
469			`.en_in ( ad_en_ctrl_mlow ) ,`
470			`.en_out ( ad_en_out[13] ),`
471			`.dat_out ( ad_out[13] )`
472			`);`
473
474	77	mihad	`pci_out_reg ad_iob14`
475	21	mihad	`(`
476	2	mihad	`.reset_in ( reset_in ),`
477			`.clk_in ( clk_in) ,`
478			`.dat_en_in ( ad_load_ctrl_mlow ),`
479			`.en_en_in ( 1'b1 ),`
480			`.dat_in ( temp_ad[14] ) ,`
481			`.en_in ( ad_en_ctrl_mlow ) ,`
482			`.en_out ( ad_en_out[14] ),`
483			`.dat_out ( ad_out[14] )`
484			`);`
485
486	77	mihad	`pci_out_reg ad_iob15`
487	21	mihad	`(`
488	2	mihad	`.reset_in ( reset_in ),`
489			`.clk_in ( clk_in) ,`
490			`.dat_en_in ( ad_load_ctrl_mlow ),`
491			`.en_en_in ( 1'b1 ),`
492			`.dat_in ( temp_ad[15] ) ,`
493			`.en_in ( ad_en_ctrl_mlow ) ,`
494			`.en_out ( ad_en_out[15] ),`
495			`.dat_out ( ad_out[15] )`
496			`);`
497
498	77	mihad	`pci_out_reg ad_iob16`
499	21	mihad	`(`
500	2	mihad	`.reset_in ( reset_in ),`

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[/] [pci/] [tags/] [asyst_3/] [rtl/] [verilog/] [pci_io_mux.v] - Blame information for rev 154