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[/] [pci/] [tags/] [rel_00/] [bench/] [verilog/] [pci_behavioral_iack_target.v] - Blame information for rev 154

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name "pci_behavioral_iack_target"                      ////
////                                                              ////
////  This file is part of the "PCI bridge" project               ////
////  http://www.opencores.org/cores/pci/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Miha Dolenc (mihad@opencores.org)                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2002/02/01 15:07:51  mihad
// *** empty log message ***
//
 
`include "pci_constants.v"
`include "timescale.v"
`include "bus_commands.v"
 
// module is provided just as target for responding to interrupt acknowledge commands, because
// other models don't support this command
module PCI_BEHAVIORAL_IACK_TARGET
(
    CLK,
    AD,
    CBE,
    RST,
    FRAME,
    IRDY,
    DEVSEL,
    TRDY,
    STOP,
    PAR,
    respond,
    interrupt_vector
);
 
input CLK ;
output [31:0] AD ;
reg    [31:0] AD ;
input  [3:0] CBE ;
input  RST ;
input  FRAME ;
input  IRDY ;
output DEVSEL ;
reg    DEVSEL ;
output TRDY ;
reg    TRDY ;
output STOP ;
reg    STOP ;
output PAR ;
reg    PAR ;
input  respond ;
input [31:0] interrupt_vector ;
 
reg frame_prev ;
reg [3:0] cbe_prev ;
 
always@(posedge CLK or negedge RST)
begin
    if ( !RST )
    begin
        frame_prev <= #`FF_DELAY 1'b1 ;
        cbe_prev   <= #`FF_DELAY 4'hF ;
        AD         <= #`FF_DELAY 32'hzzzz_zzzz ;
        DEVSEL     <= #`FF_DELAY 1'bz ;
        TRDY       <= #`FF_DELAY 1'bz ;
        STOP       <= #`FF_DELAY 1'bz ;
        PAR        <= #`FF_DELAY 1'bz ;
    end
    else
    begin
        frame_prev <= #`FF_DELAY FRAME ;
        cbe_prev   <= #`FF_DELAY CBE ;
    end
end
 
always@(posedge CLK)
begin
    if ( RST )
    begin
        if ( (frame_prev === 1) && (FRAME === 0) && (CBE === `BC_IACK) && (respond === 1) )
            do_reference ;
    end
end
 
task do_reference ;
begin
    // do medium decode
    @(posedge CLK) ;
    DEVSEL <= #`FF_DELAY 1'b0 ;
    TRDY   <= #`FF_DELAY 1'b0 ;
    STOP   <= #`FF_DELAY 1'b0 ;
 
    if ( CBE[3] === 0 )
        AD[31:24] <= #`FF_DELAY interrupt_vector[31:24] ;
    else
        AD[31:24] <= #`FF_DELAY 0 ;
 
    if ( CBE[2] === 0 )
        AD[23:16] <= #`FF_DELAY interrupt_vector[23:16] ;
    else
        AD[23:16] <= #`FF_DELAY 0 ;
 
    if ( CBE[1] === 0 )
        AD[15:8] <= #`FF_DELAY interrupt_vector[15:8] ;
    else
        AD[15:8] <= #`FF_DELAY 0 ;
 
    if ( CBE[0] === 0 )
        AD[7:0] <= #`FF_DELAY interrupt_vector[7:0] ;
    else
        AD[7:0] <= #`FF_DELAY 0 ;
 
    @(posedge CLK) ;
    PAR <= #`FF_DELAY ^( {AD, CBE} ) ;
 
    if ( FRAME !== 1 )
    begin
        while ( FRAME !== 1 )
        begin
            @(posedge CLK) ;
            PAR <= #`FF_DELAY ^( {AD, CBE} ) ;
        end
    end
 
    AD         <= #`FF_DELAY 32'hzzzz_zzzz ;
    DEVSEL     <= #`FF_DELAY 1'b1 ;
    TRDY       <= #`FF_DELAY 1'b1 ;
    STOP       <= #`FF_DELAY 1'b1 ;
 
    @(posedge CLK) ;
    DEVSEL     <= #`FF_DELAY 1'bz ;
    TRDY       <= #`FF_DELAY 1'bz ;
    STOP       <= #`FF_DELAY 1'bz ;
    PAR        <= #`FF_DELAY 1'bz ;
end
endtask // do reference
 
endmodule

Line No.	Rev	Author	Line
1	19	mihad	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// File name "pci_behavioral_iack_target" ////`
4			`//// ////`
5			`//// This file is part of the "PCI bridge" project ////`
6			`//// http://www.opencores.org/cores/pci/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Miha Dolenc (mihad@opencores.org) ////`
10			`//// ////`
11			`//// ////`
12			`//////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org ////`
15			`//// ////`
16			`//// This source file may be used and distributed without ////`
17			`//// restriction provided that this copyright statement is not ////`
18			`//// removed from the file and that any derivative work contains ////`
19			`//// the original copyright notice and the associated disclaimer. ////`
20			`//// ////`
21			`//// This source file is free software; you can redistribute it ////`
22			`//// and/or modify it under the terms of the GNU Lesser General ////`
23			`//// Public License as published by the Free Software Foundation; ////`
24			`//// either version 2.1 of the License, or (at your option) any ////`
25			`//// later version. ////`
26			`//// ////`
27			`//// This source is distributed in the hope that it will be ////`
28			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
29			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
30			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
31			`//// details. ////`
32			`//// ////`
33			`//// You should have received a copy of the GNU Lesser General ////`
34			`//// Public License along with this source; if not, download it ////`
35			`//// from http://www.opencores.org/lgpl.shtml ////`
36			`//// ////`
37			`//////////////////////////////////////////////////////////////////////`
38			`//`
39			`// CVS Revision History`
40			`//`
41			`// $Log: not supported by cvs2svn $`
42	34	mihad	`// Revision 1.1 2002/02/01 15:07:51 mihad`
43			`// * empty log message *`
44			`//`
45	19	mihad
46			`include "pci_constants.v"
47			`include "timescale.v"
48	34	mihad	`include "bus_commands.v"
49	19	mihad
50			`// module is provided just as target for responding to interrupt acknowledge commands, because`
51			`// other models don't support this command`
52			`module PCI_BEHAVIORAL_IACK_TARGET`
53			`(`
54			`CLK,`
55			`AD,`
56			`CBE,`
57			`RST,`
58			`FRAME,`
59			`IRDY,`
60			`DEVSEL,`
61			`TRDY,`
62			`STOP,`
63			`PAR,`
64			`respond,`
65			`interrupt_vector`
66			`);`
67
68			`input CLK ;`
69			`output [31:0] AD ;`
70			`reg [31:0] AD ;`
71			`input [3:0] CBE ;`
72			`input RST ;`
73			`input FRAME ;`
74			`input IRDY ;`
75			`output DEVSEL ;`
76			`reg DEVSEL ;`
77			`output TRDY ;`
78			`reg TRDY ;`
79			`output STOP ;`
80			`reg STOP ;`
81			`output PAR ;`
82			`reg PAR ;`
83			`input respond ;`
84			`input [31:0] interrupt_vector ;`
85
86			`reg frame_prev ;`
87			`reg [3:0] cbe_prev ;`
88
89			`always@(posedge CLK or negedge RST)`
90			`begin`
91			`if ( !RST )`
92			`begin`
93			frame_prev <= #`FF_DELAY 1'b1 ;
94			cbe_prev <= #`FF_DELAY 4'hF ;
95			AD <= #`FF_DELAY 32'hzzzz_zzzz ;
96			DEVSEL <= #`FF_DELAY 1'bz ;
97			TRDY <= #`FF_DELAY 1'bz ;
98			STOP <= #`FF_DELAY 1'bz ;
99			PAR <= #`FF_DELAY 1'bz ;
100			`end`
101			`else`
102			`begin`
103			frame_prev <= #`FF_DELAY FRAME ;
104			cbe_prev <= #`FF_DELAY CBE ;
105			`end`
106			`end`
107
108			`always@(posedge CLK)`
109			`begin`
110			`if ( RST )`
111			`begin`
112			if ( (frame_prev === 1) && (FRAME === 0) && (CBE === `BC_IACK) && (respond === 1) )
113			`do_reference ;`
114			`end`
115			`end`
116
117			`task do_reference ;`
118			`begin`
119			`// do medium decode`
120			`@(posedge CLK) ;`
121			DEVSEL <= #`FF_DELAY 1'b0 ;
122			TRDY <= #`FF_DELAY 1'b0 ;
123			STOP <= #`FF_DELAY 1'b0 ;
124
125			`if ( CBE[3] === 0 )`
126			AD[31:24] <= #`FF_DELAY interrupt_vector[31:24] ;
127			`else`
128			AD[31:24] <= #`FF_DELAY 0 ;
129
130			`if ( CBE[2] === 0 )`
131			AD[23:16] <= #`FF_DELAY interrupt_vector[23:16] ;
132			`else`
133			AD[23:16] <= #`FF_DELAY 0 ;
134
135			`if ( CBE[1] === 0 )`
136			AD[15:8] <= #`FF_DELAY interrupt_vector[15:8] ;
137			`else`
138			AD[15:8] <= #`FF_DELAY 0 ;
139
140			`if ( CBE[0] === 0 )`
141			AD[7:0] <= #`FF_DELAY interrupt_vector[7:0] ;
142			`else`
143			AD[7:0] <= #`FF_DELAY 0 ;
144
145			`@(posedge CLK) ;`
146			PAR <= #`FF_DELAY ^( {AD, CBE} ) ;
147
148			`if ( FRAME !== 1 )`
149			`begin`
150			`while ( FRAME !== 1 )`
151			`begin`
152			`@(posedge CLK) ;`
153			PAR <= #`FF_DELAY ^( {AD, CBE} ) ;
154			`end`
155			`end`
156
157			AD <= #`FF_DELAY 32'hzzzz_zzzz ;
158			DEVSEL <= #`FF_DELAY 1'b1 ;
159			TRDY <= #`FF_DELAY 1'b1 ;
160			STOP <= #`FF_DELAY 1'b1 ;
161
162			`@(posedge CLK) ;`
163			DEVSEL <= #`FF_DELAY 1'bz ;
164			TRDY <= #`FF_DELAY 1'bz ;
165			STOP <= #`FF_DELAY 1'bz ;
166			PAR <= #`FF_DELAY 1'bz ;
167			`end`
168			`endtask // do reference`
169
170			`endmodule`

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[/] [pci/] [tags/] [rel_00/] [bench/] [verilog/] [pci_behavioral_iack_target.v] - Blame information for rev 154