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[/] [pci/] [tags/] [rel_00/] [bench/] [verilog/] [wb_bus_mon.v] - Blame information for rev 41

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name "wb_bus_mon.v"                                    ////
////                                                              ////
////  This file is part of the "PCI bridge" project               ////
////  http://www.opencores.org/cores/pci/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - mihad@opencores.org                                   ////
////      - Miha Dolenc                                           ////
////                                                              ////
////  All additional information is avaliable in the README.pdf   ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2001/08/06 18:12:58  mihad
// Pocasi delamo kompletno zadevo
//
//
 
`include "pci_testbench_defines.v"
// WISHBONE bus monitor module - it connects to WISHBONE master signals and
// monitors for any illegal combinations appearing on the bus.
module WB_BUS_MON(
                    CLK_I,
                    RST_I,
                            ACK_I,
                    ADDR_O,
                    CYC_O,
                    DAT_I,
                    DAT_O,
                    ERR_I,
                    RTY_I,
                    SEL_O,
                    STB_O,
                    WE_O,
                    TAG_I,
                    TAG_O,
                    CAB_O,
                    log_file_desc
                  ) ;
 
input                           CLK_I  ;
input                           RST_I  ;
input                           ACK_I  ;
input   [(`WB_ADDR_WIDTH-1):0]  ADDR_O ;
input                           CYC_O  ;
input   [(`WB_DATA_WIDTH-1):0]  DAT_I  ;
input   [(`WB_DATA_WIDTH-1):0]  DAT_O  ;
input                           ERR_I  ;
input                           RTY_I  ;
input   [(`WB_SEL_WIDTH-1):0]   SEL_O  ;
input                           STB_O  ;
input                           WE_O   ;
input   [(`WB_TAG_WIDTH-1):0] TAG_I  ;
input   [(`WB_TAG_WIDTH-1):0] TAG_O  ;
input                           CAB_O  ;
input [31:0] log_file_desc ;
 
always@(posedge CLK_I or posedge RST_I)
begin
    if (RST_I)
    begin
        // when reset is applied, all control signals must be low
        if (CYC_O)
        begin
            $display("CYC_O active under reset") ;
            $fdisplay(log_file_desc, "CYC_O active under reset") ;
        end
        if (STB_O)
        begin
            $display("STB_O active under reset") ;
            $fdisplay(log_file_desc, "STB_O active under reset") ;
        end
        /*if (ACK_I)
            $display("ACK_I active under reset") ;*/
        if (ERR_I)
        begin
            $display("ERR_I active under reset") ;
            $fdisplay(log_file_desc, "ERR_I active under reset") ;
        end
        if (RTY_I)
        begin
            $display("RTY_I active under reset") ;
            $fdisplay(log_file_desc, "RTY_I active under reset") ;
        end
        if (CAB_O)
        begin
            $display("CAB_O active under reset") ;
            $fdisplay(log_file_desc, "CAB_O active under reset") ;
        end
    end // reset
    else
    if (~CYC_O)
    begin
        // when cycle indicator is low, all control signals must be low
        if (STB_O)
        begin
            $display("STB_O active without CYC_O being active") ;
            $fdisplay(log_file_desc, "STB_O active without CYC_O being active") ;
        end
        if (ACK_I)
        begin
            $display("ACK_I active without CYC_O being active") ;
            $fdisplay(log_file_desc, "ACK_I active without CYC_O being active") ;
        end
        if (ERR_I)
        begin
            $display("ERR_I active without CYC_O being active") ;
            $fdisplay(log_file_desc, "ERR_I active without CYC_O being active") ;
        end
        if (RTY_I)
        begin
            $display("RTY_I active without CYC_O being active") ;
            $fdisplay(log_file_desc, "RTY_I active without CYC_O being active") ;
        end
        if (CAB_O)
        begin
            $display("CAB_O active without CYC_O being active") ;
            $fdisplay(log_file_desc, "CAB_O active without CYC_O being active") ;
        end
    end // ~CYC_O
end
 
reg [`WB_DATA_WIDTH-1:0] previous_data ;
reg [`WB_ADDR_WIDTH-1:0] previous_address ;
reg [`WB_SEL_WIDTH-1:0] previous_sel ;
reg can_change ;
 
// cycle monitor
always@(posedge CLK_I or posedge RST_I)
begin
    if (CYC_O && ~RST_I) // cycle in progress
    begin
        if (STB_O)
        begin
            // check for two control signals active at same edge
            if ( ACK_I && RTY_I )
            begin
                $display("ACK_I and RTY_I asserted at the same time during cycle") ;
                $fdisplay(log_file_desc, "ACK_I and RTY_I asserted at the same time during cycle") ;
            end
            if ( ACK_I && ERR_I )
            begin
                $display("ACK_I and ERR_I asserted at the same time during cycle") ;
                $fdisplay(log_file_desc, "ACK_I and ERR_I asserted at the same time during cycle") ;
            end
            if ( RTY_I && ERR_I )
            begin
                $display("RTY_I and ERR_I asserted at the same time during cycle") ;
                $fdisplay(log_file_desc, "RTY_I and ERR_I asserted at the same time during cycle") ;
            end
 
            if ( can_change !== 1 )
            begin
                if ( ADDR_O !== previous_address )
                begin
                    $display("WB bus monitor detected address change in the middle of the cycle!") ;
                    $fdisplay(log_file_desc, "WB bus monitor detected address change in the middle of the cycle!") ;
                end
 
                if ( SEL_O !== previous_sel )
                begin
                    $display("WB bus monitor detected select lines changed in the middle of the cycle!") ;
                    $fdisplay(log_file_desc, "WB bus monitor detected select lines changed in the middle of the cycle!") ;
                end
 
                if ( (WE_O !== 0) && ( DAT_O !== previous_data ) )
                begin
                    $display("WB bus monitor detected data lines changed in the middle of the cycle!") ;
                    $fdisplay(log_file_desc, "WB bus monitor detected data lines changed in the middle of the cycle!") ;
                end
            end
 
            if ( ACK_I || RTY_I || ERR_I )
                can_change       = 1 ;
            else
            begin
                previous_data    = DAT_O ;
                previous_address = ADDR_O ;
                previous_sel     = SEL_O ;
                can_change = 0 ;
            end
 
        end // STB_O
        else
        begin //~STB_O
            // while STB_O is inactive, only ACK_I is allowed to be active
            if ( ERR_I )
            begin
                $display("ERR_I asserted during cycle without STB_O") ;
                $fdisplay(log_file_desc, "ERR_I asserted during cycle without STB_O") ;
            end
            if ( RTY_I )
            begin
                $display("RTY_I asserted during cycle without STB_O") ;
                $fdisplay(log_file_desc, "RTY_I asserted during cycle without STB_O") ;
            end
 
            can_change = 1 ;
        end   // ~STB_O
    end // cycle in progress
end // cycle monitor
 
// CAB_O monitor - CAB_O musn't change during one cycle
reg [1:0] first_cab_val ;
always@(posedge CLK_I or RST_I)
begin
    if ((CYC_O === 0) || RST_I)
        first_cab_val <= 2'b00 ;
    else
    begin
        // cycle in progress - is this first clock edge in a cycle ?
        if (first_cab_val[1] === 1'b0)
            first_cab_val <= {1'b1, CAB_O} ;
        else if ( first_cab_val[0] !== CAB_O )
        begin
            $display("CAB_O value changed during cycle") ;
            $fdisplay(log_file_desc, "CAB_O value changed during cycle") ;
        end
    end
end // CAB_O monitor
 
// WE_O monitor for consecutive address bursts
reg [1:0] first_we_val ;
always@(posedge CLK_I or posedge RST_I)
begin
    if (~CYC_O || ~CAB_O || RST_I)
        first_we_val <= 2'b00 ;
    else
    if (STB_O)
    begin
        // cycle in progress - is this first clock edge in a cycle ?
        if (first_we_val[1] == 1'b0)
            first_we_val <= {1'b1, WE_O} ;
        else if ( first_we_val[0] != WE_O )
        begin
            $display("WE_O value changed during CAB cycle") ;
            $fdisplay(log_file_desc, "WE_O value changed during CAB cycle") ;
        end
    end
end // CAB_O monitor
 
// address monitor for consecutive address bursts
reg [`WB_ADDR_WIDTH:0] address ;
always@(posedge CLK_I or posedge RST_I)
begin
    if (~CYC_O || ~CAB_O || RST_I)
        address <= {(`WB_ADDR_WIDTH + 1){1'b0}} ;
    else
    begin
        if (STB_O && ACK_I)
        begin
            if (address[`WB_ADDR_WIDTH] == 1'b0)
                address <= {1'b1, (ADDR_O + `WB_SEL_WIDTH)} ;
            else
            begin
                if ( address[(`WB_ADDR_WIDTH-1):0] != ADDR_O)
                begin
                    $display("Consecutive address burst address incrementing incorrect") ;
                    $fdisplay(log_file_desc, "Consecutive address burst address incrementing incorrect") ;
                end
                else
                    address <= {1'b1, (ADDR_O + `WB_SEL_WIDTH)} ;
            end
        end
    end
end // address monitor
 
// data monitor
always@(posedge CLK_I or posedge RST_I)
begin
    if (CYC_O && STB_O && ~RST_I)
    begin
        if ( ((^ADDR_O) !== 1'b1) && ((^ADDR_O) !== 1'b0) )
        begin
            $display("Master provided invalid address and qualified it with STB_O") ;
            $fdisplay(log_file_desc, "Master provided invalid address and qualified it with STB_O") ;
        end
        if ( WE_O )
        begin
            if (
                (SEL_O[0] && (((^DAT_O[7:0])   !== 1'b0) && ((^DAT_O[7:0])   !== 1'b1))) ||
                (SEL_O[1] && (((^DAT_O[15:8])  !== 1'b0) && ((^DAT_O[15:8])  !== 1'b1))) ||
                (SEL_O[2] && (((^DAT_O[23:16]) !== 1'b0) && ((^DAT_O[23:16]) !== 1'b1))) ||
                (SEL_O[3] && (((^DAT_O[31:24]) !== 1'b0) && ((^DAT_O[31:24]) !== 1'b1)))
               )
            begin
                $display("Master provided invalid data during write and qualified it with STB_O") ;
                $fdisplay(log_file_desc, "Master provided invalid data during write and qualified it with STB_O") ;
                $display("Byte select value: SEL_O = %b, Data bus value: DAT_O =  %h ", SEL_O, DAT_O) ;
                $fdisplay(log_file_desc, "Byte select value: SEL_O = %b, Data bus value: DAT_O =  %h ", SEL_O, DAT_O) ;
            end
 
        end
        else
        if (~WE_O && ACK_I)
        begin
            if (
                (SEL_O[0] && (((^DAT_I[7:0])   !== 1'b0) && ((^DAT_I[7:0])   !== 1'b1))) ||
                (SEL_O[1] && (((^DAT_I[15:8])  !== 1'b0) && ((^DAT_I[15:8])  !== 1'b1))) ||
                (SEL_O[2] && (((^DAT_I[23:16]) !== 1'b0) && ((^DAT_I[23:16]) !== 1'b1))) ||
                (SEL_O[3] && (((^DAT_I[31:24]) !== 1'b0) && ((^DAT_I[31:24]) !== 1'b1)))
               )
            begin
                $display("Slave provided invalid data during read and qualified it with ACK_I") ;
                $fdisplay(log_file_desc, "Slave provided invalid data during read and qualified it with ACK_I") ;
                $display("Byte select value: SEL_O = %b, Data bus value: DAT_I =  %h ", SEL_O, DAT_I) ;
                $fdisplay(log_file_desc, "Byte select value: SEL_O = %b, Data bus value: DAT_I =  %h ", SEL_O, DAT_I) ;
            end
        end
    end
end
 
initial
begin
    previous_data = 0 ;
    previous_address = 0 ;
    can_change = 1 ;
end
endmodule // BUS_MON

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[/] [pci/] [tags/] [rel_00/] [bench/] [verilog/] [wb_bus_mon.v] - Blame information for rev 41

Line No.	Rev	Author	Line
1	15	mihad	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// File name "wb_bus_mon.v" ////`
4			`//// ////`
5			`//// This file is part of the "PCI bridge" project ////`
6			`//// http://www.opencores.org/cores/pci/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - mihad@opencores.org ////`
10			`//// - Miha Dolenc ////`
11			`//// ////`
12			`//// All additional information is avaliable in the README.pdf ////`
13			`//// file. ////`
14			`//// ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46			`// Revision 1.1 2001/08/06 18:12:58 mihad`
47			`// Pocasi delamo kompletno zadevo`
48			`//`
49			`//`
50
51			`include "pci_testbench_defines.v"
52			`// WISHBONE bus monitor module - it connects to WISHBONE master signals and`
53			`// monitors for any illegal combinations appearing on the bus.`
54			`module WB_BUS_MON(`
55			`CLK_I,`
56			`RST_I,`
57			`ACK_I,`
58			`ADDR_O,`
59			`CYC_O,`
60			`DAT_I,`
61			`DAT_O,`
62			`ERR_I,`
63			`RTY_I,`
64			`SEL_O,`
65			`STB_O,`
66			`WE_O,`
67			`TAG_I,`
68			`TAG_O,`
69			`CAB_O,`
70			`log_file_desc`
71			`) ;`
72
73			`input CLK_I ;`
74			`input RST_I ;`
75			`input ACK_I ;`
76			input [(`WB_ADDR_WIDTH-1):0] ADDR_O ;
77			`input CYC_O ;`
78			input [(`WB_DATA_WIDTH-1):0] DAT_I ;
79			input [(`WB_DATA_WIDTH-1):0] DAT_O ;
80			`input ERR_I ;`
81			`input RTY_I ;`
82			input [(`WB_SEL_WIDTH-1):0] SEL_O ;
83			`input STB_O ;`
84			`input WE_O ;`
85			input [(`WB_TAG_WIDTH-1):0] TAG_I ;
86			input [(`WB_TAG_WIDTH-1):0] TAG_O ;
87			`input CAB_O ;`
88			`input [31:0] log_file_desc ;`
89
90			`always@(posedge CLK_I or posedge RST_I)`
91			`begin`
92			`if (RST_I)`
93			`begin`
94			`// when reset is applied, all control signals must be low`
95			`if (CYC_O)`
96			`begin`
97			`$display("CYC_O active under reset") ;`
98			`$fdisplay(log_file_desc, "CYC_O active under reset") ;`
99			`end`
100			`if (STB_O)`
101			`begin`
102			`$display("STB_O active under reset") ;`
103			`$fdisplay(log_file_desc, "STB_O active under reset") ;`
104			`end`
105			`/*if (ACK_I)`
106			`$display("ACK_I active under reset") ;*/`
107			`if (ERR_I)`
108			`begin`
109			`$display("ERR_I active under reset") ;`
110			`$fdisplay(log_file_desc, "ERR_I active under reset") ;`
111			`end`
112			`if (RTY_I)`
113			`begin`
114			`$display("RTY_I active under reset") ;`
115			`$fdisplay(log_file_desc, "RTY_I active under reset") ;`
116			`end`
117			`if (CAB_O)`
118			`begin`
119			`$display("CAB_O active under reset") ;`
120			`$fdisplay(log_file_desc, "CAB_O active under reset") ;`
121			`end`
122			`end // reset`
123			`else`
124			`if (~CYC_O)`
125			`begin`
126			`// when cycle indicator is low, all control signals must be low`
127			`if (STB_O)`
128			`begin`
129			`$display("STB_O active without CYC_O being active") ;`
130			`$fdisplay(log_file_desc, "STB_O active without CYC_O being active") ;`
131			`end`
132			`if (ACK_I)`
133			`begin`
134			`$display("ACK_I active without CYC_O being active") ;`
135			`$fdisplay(log_file_desc, "ACK_I active without CYC_O being active") ;`
136			`end`
137			`if (ERR_I)`
138			`begin`
139			`$display("ERR_I active without CYC_O being active") ;`
140			`$fdisplay(log_file_desc, "ERR_I active without CYC_O being active") ;`
141			`end`
142			`if (RTY_I)`
143			`begin`
144			`$display("RTY_I active without CYC_O being active") ;`
145			`$fdisplay(log_file_desc, "RTY_I active without CYC_O being active") ;`
146			`end`
147			`if (CAB_O)`
148			`begin`
149			`$display("CAB_O active without CYC_O being active") ;`
150			`$fdisplay(log_file_desc, "CAB_O active without CYC_O being active") ;`
151			`end`
152			`end // ~CYC_O`
153			`end`
154
155			reg [`WB_DATA_WIDTH-1:0] previous_data ;
156			reg [`WB_ADDR_WIDTH-1:0] previous_address ;
157			reg [`WB_SEL_WIDTH-1:0] previous_sel ;
158			`reg can_change ;`
159
160			`// cycle monitor`
161			`always@(posedge CLK_I or posedge RST_I)`
162			`begin`
163			`if (CYC_O && ~RST_I) // cycle in progress`
164			`begin`
165			`if (STB_O)`
166			`begin`
167			`// check for two control signals active at same edge`
168			`if ( ACK_I && RTY_I )`
169			`begin`
170			`$display("ACK_I and RTY_I asserted at the same time during cycle") ;`
171			`$fdisplay(log_file_desc, "ACK_I and RTY_I asserted at the same time during cycle") ;`
172			`end`
173			`if ( ACK_I && ERR_I )`
174			`begin`
175			`$display("ACK_I and ERR_I asserted at the same time during cycle") ;`
176			`$fdisplay(log_file_desc, "ACK_I and ERR_I asserted at the same time during cycle") ;`
177			`end`
178			`if ( RTY_I && ERR_I )`
179			`begin`
180			`$display("RTY_I and ERR_I asserted at the same time during cycle") ;`
181			`$fdisplay(log_file_desc, "RTY_I and ERR_I asserted at the same time during cycle") ;`
182			`end`
183
184			`if ( can_change !== 1 )`
185			`begin`
186			`if ( ADDR_O !== previous_address )`
187			`begin`
188			`$display("WB bus monitor detected address change in the middle of the cycle!") ;`
189			`$fdisplay(log_file_desc, "WB bus monitor detected address change in the middle of the cycle!") ;`
190			`end`
191
192			`if ( SEL_O !== previous_sel )`
193			`begin`
194			`$display("WB bus monitor detected select lines changed in the middle of the cycle!") ;`
195			`$fdisplay(log_file_desc, "WB bus monitor detected select lines changed in the middle of the cycle!") ;`
196			`end`
197
198			`if ( (WE_O !== 0) && ( DAT_O !== previous_data ) )`
199			`begin`
200			`$display("WB bus monitor detected data lines changed in the middle of the cycle!") ;`
201			`$fdisplay(log_file_desc, "WB bus monitor detected data lines changed in the middle of the cycle!") ;`
202			`end`
203			`end`
204
205			`if ( ACK_I \|\| RTY_I \|\| ERR_I )`
206			`can_change = 1 ;`
207			`else`
208			`begin`
209			`previous_data = DAT_O ;`
210			`previous_address = ADDR_O ;`
211			`previous_sel = SEL_O ;`
212			`can_change = 0 ;`
213			`end`
214
215			`end // STB_O`
216			`else`
217			`begin //~STB_O`
218			`// while STB_O is inactive, only ACK_I is allowed to be active`
219			`if ( ERR_I )`
220			`begin`
221			`$display("ERR_I asserted during cycle without STB_O") ;`
222			`$fdisplay(log_file_desc, "ERR_I asserted during cycle without STB_O") ;`
223			`end`
224			`if ( RTY_I )`
225			`begin`
226			`$display("RTY_I asserted during cycle without STB_O") ;`
227			`$fdisplay(log_file_desc, "RTY_I asserted during cycle without STB_O") ;`
228			`end`
229
230			`can_change = 1 ;`
231			`end // ~STB_O`
232			`end // cycle in progress`
233			`end // cycle monitor`
234
235			`// CAB_O monitor - CAB_O musn't change during one cycle`
236			`reg [1:0] first_cab_val ;`
237			`always@(posedge CLK_I or RST_I)`
238			`begin`
239			`if ((CYC_O === 0) \|\| RST_I)`
240			`first_cab_val <= 2'b00 ;`
241			`else`
242			`begin`
243			`// cycle in progress - is this first clock edge in a cycle ?`
244			`if (first_cab_val[1] === 1'b0)`
245			`first_cab_val <= {1'b1, CAB_O} ;`
246			`else if ( first_cab_val[0] !== CAB_O )`
247			`begin`
248			`$display("CAB_O value changed during cycle") ;`
249			`$fdisplay(log_file_desc, "CAB_O value changed during cycle") ;`
250			`end`
251			`end`
252			`end // CAB_O monitor`
253
254			`// WE_O monitor for consecutive address bursts`
255			`reg [1:0] first_we_val ;`
256			`always@(posedge CLK_I or posedge RST_I)`
257			`begin`
258			`if (~CYC_O \|\| ~CAB_O \|\| RST_I)`
259			`first_we_val <= 2'b00 ;`
260			`else`
261			`if (STB_O)`
262			`begin`
263			`// cycle in progress - is this first clock edge in a cycle ?`
264			`if (first_we_val[1] == 1'b0)`
265			`first_we_val <= {1'b1, WE_O} ;`
266			`else if ( first_we_val[0] != WE_O )`
267			`begin`
268			`$display("WE_O value changed during CAB cycle") ;`
269			`$fdisplay(log_file_desc, "WE_O value changed during CAB cycle") ;`
270			`end`
271			`end`
272			`end // CAB_O monitor`
273
274			`// address monitor for consecutive address bursts`
275			reg [`WB_ADDR_WIDTH:0] address ;
276			`always@(posedge CLK_I or posedge RST_I)`
277			`begin`
278			`if (~CYC_O \|\| ~CAB_O \|\| RST_I)`
279			address <= {(`WB_ADDR_WIDTH + 1){1'b0}} ;
280			`else`
281			`begin`
282			`if (STB_O && ACK_I)`
283			`begin`
284			if (address[`WB_ADDR_WIDTH] == 1'b0)
285			address <= {1'b1, (ADDR_O + `WB_SEL_WIDTH)} ;
286			`else`
287			`begin`
288			if ( address[(`WB_ADDR_WIDTH-1):0] != ADDR_O)
289			`begin`
290			`$display("Consecutive address burst address incrementing incorrect") ;`
291			`$fdisplay(log_file_desc, "Consecutive address burst address incrementing incorrect") ;`
292			`end`
293			`else`
294			address <= {1'b1, (ADDR_O + `WB_SEL_WIDTH)} ;
295			`end`
296			`end`
297			`end`
298			`end // address monitor`
299
300			`// data monitor`
301			`always@(posedge CLK_I or posedge RST_I)`
302			`begin`
303			`if (CYC_O && STB_O && ~RST_I)`
304			`begin`
305			`if ( ((^ADDR_O) !== 1'b1) && ((^ADDR_O) !== 1'b0) )`
306			`begin`
307			`$display("Master provided invalid address and qualified it with STB_O") ;`
308			`$fdisplay(log_file_desc, "Master provided invalid address and qualified it with STB_O") ;`
309			`end`
310			`if ( WE_O )`
311			`begin`
312			`if (`
313			`(SEL_O[0] && (((^DAT_O[7:0]) !== 1'b0) && ((^DAT_O[7:0]) !== 1'b1))) \|\|`
314			`(SEL_O[1] && (((^DAT_O[15:8]) !== 1'b0) && ((^DAT_O[15:8]) !== 1'b1))) \|\|`
315			`(SEL_O[2] && (((^DAT_O[23:16]) !== 1'b0) && ((^DAT_O[23:16]) !== 1'b1))) \|\|`
316			`(SEL_O[3] && (((^DAT_O[31:24]) !== 1'b0) && ((^DAT_O[31:24]) !== 1'b1)))`
317			`)`
318			`begin`
319			`$display("Master provided invalid data during write and qualified it with STB_O") ;`
320			`$fdisplay(log_file_desc, "Master provided invalid data during write and qualified it with STB_O") ;`
321			`$display("Byte select value: SEL_O = %b, Data bus value: DAT_O = %h ", SEL_O, DAT_O) ;`
322			`$fdisplay(log_file_desc, "Byte select value: SEL_O = %b, Data bus value: DAT_O = %h ", SEL_O, DAT_O) ;`
323			`end`
324
325			`end`
326			`else`
327			`if (~WE_O && ACK_I)`
328			`begin`
329			`if (`
330			`(SEL_O[0] && (((^DAT_I[7:0]) !== 1'b0) && ((^DAT_I[7:0]) !== 1'b1))) \|\|`
331			`(SEL_O[1] && (((^DAT_I[15:8]) !== 1'b0) && ((^DAT_I[15:8]) !== 1'b1))) \|\|`
332			`(SEL_O[2] && (((^DAT_I[23:16]) !== 1'b0) && ((^DAT_I[23:16]) !== 1'b1))) \|\|`
333			`(SEL_O[3] && (((^DAT_I[31:24]) !== 1'b0) && ((^DAT_I[31:24]) !== 1'b1)))`
334			`)`
335			`begin`
336			`$display("Slave provided invalid data during read and qualified it with ACK_I") ;`
337			`$fdisplay(log_file_desc, "Slave provided invalid data during read and qualified it with ACK_I") ;`
338			`$display("Byte select value: SEL_O = %b, Data bus value: DAT_I = %h ", SEL_O, DAT_I) ;`
339			`$fdisplay(log_file_desc, "Byte select value: SEL_O = %b, Data bus value: DAT_I = %h ", SEL_O, DAT_I) ;`
340			`end`
341			`end`
342			`end`
343			`end`
344
345			`initial`
346			`begin`
347			`previous_data = 0 ;`
348			`previous_address = 0 ;`
349			`can_change = 1 ;`
350			`end`
351			`endmodule // BUS_MON`