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[/] [pci/] [tags/] [rel_00/] [rtl/] [verilog/] [async_reset_flop.v] - Blame information for rev 154

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//===========================================================================
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// $Id: async_reset_flop.v,v 1.2 2002-02-25 15:15:43 mihad Exp $
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//
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// async_reset_flop                                             ////
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////                                                              ////
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//// This file is part of the general opencores effort.           ////
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//// <http://www.opencores.org/cores/misc/>                       ////
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////                                                              ////
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//// Module Description:                                          ////
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////                                                              ////
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//// Make a rising-edge triggered flop with async reset with a    ////
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////   distinguished name so that it's output can be easily       ////
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////   traced, because it is used for asynchronous reset of some  ////
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////   flip-flops.                                                ////
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////                                                              ////
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//// This flop should be used instead of a regular flop for ALL   ////
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////   asynchronous-reset generator flops.                        ////
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////                                                              ////
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//// To Do:                                                       ////
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//// Nothing                                                      ////
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////                                                              ////
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//// Author(s):                                                   ////
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////      - Tadej Markovic, tadej@opencores.org                   ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE. See the GNU Lesser General Public License for more  ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from <http://www.opencores.org/lgpl.shtml>                   ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.1  2002/02/01 14:43:31  mihad
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// *** empty log message ***
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//
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// 
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//
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// synopsys translate_off
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`include "timescale.v"
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`include "pci_constants.v"
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// synopsys translate_on
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module async_reset_flop (
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  data_in, clk_in, async_reset_data_out, reset_in
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);
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input      data_in;
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input      clk_in;
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output     async_reset_data_out;
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input      reset_in;
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reg        async_reset_data_out;
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always @(posedge clk_in or posedge reset_in)
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begin
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  if (reset_in)
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  begin
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    async_reset_data_out <= #`FF_DELAY 1'b0;
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  end
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  else
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  begin
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    async_reset_data_out <= #`FF_DELAY data_in;
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  end
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end
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endmodule
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