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//////////////////////////////////////////////////////////////////////

////                                                              ////

////  File name: conf_space.v                                     ////

////                                                              ////

////  This file is part of the "PCI bridge" project               ////

////  http://www.opencores.org/cores/pci/                         ////

////                                                              ////

////  Author(s):                                                  ////

////      - tadej@opencores.org                                   ////

////      - Tadej Markovic                                        ////

////                                                              ////

////  All additional information is avaliable in the README.txt   ////

////  file.                                                       ////

////                                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org       ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//

// CVS Revision History

//

// $Log: not supported by cvs2svn $

// Revision 1.2  2001/10/05 08:14:28  mihad

// Updated all files with inclusion of timescale file for simulation purposes.

//

// Revision 1.1.1.1  2001/10/02 15:33:46  mihad

// New project directory structure

//

//

`include "pci_constants.v"

// synopsys translate_off

`include "timescale.v"

// synopsys translate_on

/*-----------------------------------------------------------------------------------------------------------

        w_ prefix is a sign for Write (and read) side of Dual-Port registers

        r_ prefix is a sign for Read only side of Dual-Port registers

In the first line there are DATA and ADDRESS ports, in the second line there are write enable and read

enable signals with chip-select (conf_hit) for config. space.

In the third line there are output signlas from Command register of the PCI configuration header !!!

In the fourth line there are input signals to Status register of the PCI configuration header !!!

In the fifth line there is output from Latency Timer & r_Interrupt pin registers of the PCI conf. header !!!

Following are IMAGE specific registers, from which PCI_BASE_ADDR registers are the same as base address

registers from the PCI conf. header !!!

-----------------------------------------------------------------------------------------------------------*/

                                        // normal R/W address, data and control

module CONF_SPACE (     w_conf_address_in, w_conf_data_in, w_conf_data_out, r_conf_address_in, r_conf_data_out,

                                        w_we, w_re, r_re, w_byte_en, w_clock, reset, pci_clk, wb_clk,

                                        // outputs from command register of the PCI header

                                        serr_enable, perr_response, pci_master_enable, memory_space_enable, io_space_enable,

                                        // inputs to status register of the PCI header

                                        perr_in, serr_in, master_abort_recv, target_abort_recv, target_abort_set, master_data_par_err,

                                        // output from cache_line_size, latency timer and r_interrupt_pin register of the PCI header

                                        cache_line_size_to_pci, cache_line_size_to_wb, cache_lsize_not_zero_to_wb,

                                        latency_tim,

                                        // output from all pci IMAGE registers

                                        pci_base_addr0, pci_base_addr1, pci_base_addr2, pci_base_addr3, pci_base_addr4, pci_base_addr5,

                                        pci_memory_io0, pci_memory_io1, pci_memory_io2, pci_memory_io3, pci_memory_io4, pci_memory_io5,

                                        pci_addr_mask0, pci_addr_mask1, pci_addr_mask2, pci_addr_mask3, pci_addr_mask4, pci_addr_mask5,

                                        pci_tran_addr0, pci_tran_addr1, pci_tran_addr2, pci_tran_addr3, pci_tran_addr4, pci_tran_addr5,

                                        pci_img_ctrl0,  pci_img_ctrl1,  pci_img_ctrl2,  pci_img_ctrl3,  pci_img_ctrl4,  pci_img_ctrl5,

                                        // input to pci error control and status register, error address and error data registers

                                        pci_error_be, pci_error_bc, pci_error_rty_exp, pci_error_es, pci_error_sig, pci_error_addr,

                                        pci_error_data,

                                        // output from all wishbone IMAGE registers

                                        wb_base_addr0, wb_base_addr1, wb_base_addr2, wb_base_addr3, wb_base_addr4, wb_base_addr5,

                                        wb_memory_io0, wb_memory_io1, wb_memory_io2, wb_memory_io3, wb_memory_io4, wb_memory_io5,

                                        wb_addr_mask0, wb_addr_mask1, wb_addr_mask2, wb_addr_mask3, wb_addr_mask4, wb_addr_mask5,

                                        wb_tran_addr0, wb_tran_addr1, wb_tran_addr2, wb_tran_addr3, wb_tran_addr4, wb_tran_addr5,

                                        wb_img_ctrl0,  wb_img_ctrl1,  wb_img_ctrl2,  wb_img_ctrl3,  wb_img_ctrl4,  wb_img_ctrl5,

                                        // input to wb error control and status register, error address and error data registers

                                        wb_error_be, wb_error_bc, wb_error_rty_exp, wb_error_es, wb_error_sig, wb_error_addr, wb_error_data,

                                        // output from conf. cycle generation register (sddress), int. control register & interrupt output

                                        config_addr, icr_soft_res, int_out,

                                        // input to interrupt status register

                                        isr_sys_err_int, isr_par_err_int, isr_int_prop ) ;

/*###########################################################################################################

/////////////////////////////////////////////////////////////////////////////////////////////////////////////

        Input and output ports

        ======================

/////////////////////////////////////////////////////////////////////////////////////////////////////////////

###########################################################################################################*/

// output data

output  [31 : 0]                         w_conf_data_out ;

output  [31 : 0]                         r_conf_data_out ;

reg             [31 : 0]                         w_conf_data_out ;

`ifdef  NO_CNF_IMAGE

`else

reg             [31 : 0]                         r_conf_data_out ;

`endif

// input data

input   [31 : 0]                         w_conf_data_in ;

wire    [31 : 0]                         w_conf_pdata_reduced ; // reduced data written into PCI image registers

wire    [31 : 0]                         w_conf_wdata_reduced ; // reduced data written into WB  image registers

// input address

input   [11 : 0]                         w_conf_address_in ;

input   [11 : 0]                         r_conf_address_in ;

// input control signals

input                                                   w_we ;

input                                                   w_re ;

input                                                   r_re ;

input   [3 : 0]                                  w_byte_en ;

input                                                   w_clock ;

input                                                   reset ;

input                                                   pci_clk ;

input                                                   wb_clk ;

// PCI header outputs from command register

output                                                  serr_enable ;

output                                                  perr_response ;

output                                                  pci_master_enable ;

output                                                  memory_space_enable ;

output                                                  io_space_enable ;

// PCI header inputs to status register

input                                                   perr_in ;

input                                                   serr_in ;

input                                                   master_abort_recv ;

input                                                   target_abort_recv ;

input                                                   target_abort_set ;

input                                                   master_data_par_err ;

// PCI header output from cache_line_size, latency timer and interrupt pin

output  [7 : 0]                                  cache_line_size_to_pci ; // sinchronized to PCI clock

output  [7 : 0]                                  cache_line_size_to_wb ;  // sinchronized to WB clock

output                                                  cache_lsize_not_zero_to_wb ; // used in WBU and PCIU

output  [7 : 0]                                  latency_tim ;

//output        [2 : 0]                                 int_pin ; // only 3 LSbits are important!

// PCI output from image registers

output  [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_base_addr0 ;

output  [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_base_addr1 ;

output  [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_base_addr2 ;

output  [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_base_addr3 ;

output  [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_base_addr4 ;

output  [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_base_addr5 ;

output                                                  pci_memory_io0 ;

output                                                  pci_memory_io1 ;

output                                                  pci_memory_io2 ;

output                                                  pci_memory_io3 ;

output                                                  pci_memory_io4 ;

output                                                  pci_memory_io5 ;

output  [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_addr_mask0 ;

output  [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_addr_mask1 ;

output  [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_addr_mask2 ;

output  [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_addr_mask3 ;

output  [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_addr_mask4 ;

output  [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_addr_mask5 ;

output  [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_tran_addr0 ;

output  [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_tran_addr1 ;

output  [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_tran_addr2 ;

output  [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_tran_addr3 ;

output  [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_tran_addr4 ;

output  [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_tran_addr5 ;

output  [2 : 1]                 pci_img_ctrl0 ;

output  [2 : 1]                 pci_img_ctrl1 ;

output  [2 : 1]                 pci_img_ctrl2 ;

output  [2 : 1]                 pci_img_ctrl3 ;

output  [2 : 1]                 pci_img_ctrl4 ;

output  [2 : 1]                 pci_img_ctrl5 ;

// PCI input to pci error control and status register, error address and error data registers

input   [3 : 0]                                  pci_error_be ;

input   [3 : 0]                 pci_error_bc ;

input                           pci_error_rty_exp ;

input                                                   pci_error_es ;

input                           pci_error_sig ;

input   [31 : 0]                pci_error_addr ;

input   [31 : 0]                pci_error_data ;

// WISHBONE output from image registers

output  [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_base_addr0 ;

output  [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_base_addr1 ;

output  [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_base_addr2 ;

output  [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_base_addr3 ;

output  [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_base_addr4 ;

output  [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_base_addr5 ;

output                                                  wb_memory_io0 ;

output                                                  wb_memory_io1 ;

output                                                  wb_memory_io2 ;

output                                                  wb_memory_io3 ;

output                                                  wb_memory_io4 ;

output                                                  wb_memory_io5 ;

output  [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_addr_mask0 ;

output  [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_addr_mask1 ;

output  [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_addr_mask2 ;

output  [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_addr_mask3 ;

output  [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_addr_mask4 ;

output  [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_addr_mask5 ;

output  [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_tran_addr0 ;

output  [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_tran_addr1 ;

output  [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_tran_addr2 ;

output  [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_tran_addr3 ;

output  [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_tran_addr4 ;

output  [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_tran_addr5 ;

output  [2 : 0]                 wb_img_ctrl0 ;

output  [2 : 0]                 wb_img_ctrl1 ;

output  [2 : 0]                 wb_img_ctrl2 ;

output  [2 : 0]                 wb_img_ctrl3 ;

output  [2 : 0]                 wb_img_ctrl4 ;

output  [2 : 0]                 wb_img_ctrl5 ;

// WISHBONE input to wb error control and status register, error address and error data registers

input   [3 : 0]                          wb_error_be ;

input   [3 : 0]                  wb_error_bc ;

input                                   wb_error_rty_exp ;

input                           wb_error_es ;

input                           wb_error_sig ;

input   [31 : 0]                wb_error_addr ;

input   [31 : 0]                wb_error_data ;

// GENERAL output from conf. cycle generation register & int. control register

output  [23 : 0]                         config_addr ;

output                          icr_soft_res ;

output                                                  int_out ;

// GENERAL input to interrupt status register

input                           isr_sys_err_int ;

input                           isr_par_err_int ;

input                                                   isr_int_prop ;

/*###########################################################################################################

/////////////////////////////////////////////////////////////////////////////////////////////////////////////

        REGISTERS definition

        ====================

/////////////////////////////////////////////////////////////////////////////////////////////////////////////

###########################################################################################################*/

// Decoded Register Select signals for writting (only one address decoder)

reg             [55 : 0]                         w_reg_select_dec ;

/*###########################################################################################################

-------------------------------------------------------------------------------------------------------------

PCI CONFIGURATION SPACE HEADER (type 00h) registers

        BIST and some other registers are not implemented and therefor written in correct

        place with comment line. There are also some registers with NOT all bits implemented and therefor uses

        _bitX or _bitX2_X1 to sign which bit or range of bits are implemented.

        Some special cases and examples are described below!

-------------------------------------------------------------------------------------------------------------

###########################################################################################################*/

/*-----------------------------------------------------------------------------------------------------------

[000h-00Ch] First 4 DWORDs (32-bit) of PCI configuration header - the same regardless of the HEADER type !

                        r_ prefix is a sign for read only registers

        Vendor_ID is an ID for a specific vendor defined by PCI_SIG - 2321h does not belong to anyone (e.g.

        Xilinx's Vendor_ID is 10EEh and Altera's Vendor_ID is 1172h). Device_ID and Revision_ID should be used

        together by application. Class_Code has 3 bytes to define BASE class (06h for PCI Bridge), SUB class

        (00h for HOST type, 80h for Other Bridge type) and Interface type (00h for normal).

-----------------------------------------------------------------------------------------------------------*/

                        parameter                       r_vendor_id = `HEADER_VENDOR_ID ;       // 16'h2321 = 16'd8993 !!!

                        parameter                       r_device_id = `HEADER_DEVICE_ID ;

                        reg                                     command_bit8 ;

                        reg                                     command_bit6 ;

                        reg             [2 : 0]          command_bit2_0 ;

                        reg             [15 : 11]       status_bit15_11 ;

                        parameter                       r_status_bit10_9 = 2'b01 ;      // 2'b01 means MEDIUM devsel timing !!!

                        reg                                     status_bit8 ;

                        parameter                       r_status_bit7 = 1'b1 ; // fast back-to-back capable response !!!

                        parameter                       r_status_bit5 = `HEADER_66MHz ;         // 1'b0 indicates 33 MHz capable !!!

                        parameter                       r_revision_id = `HEADER_REVISION_ID ;

`ifdef          HOST

                        parameter                       r_class_code = 24'h06_00_00 ;

`else

                        parameter                       r_class_code = 24'h06_80_00 ;

`endif

                        reg             [7 : 0]          cache_line_size_reg     ;

                        reg             [7 : 0]          latency_timer ;

                        parameter                       r_header_type = 8'h00 ;

                        // REG                          bist                                                    NOT implemented !!!

/*-----------------------------------------------------------------------------------------------------------

[010h-03Ch] all other DWORDs (32-bit) of PCI configuration header - only for HEADER type 00h !

                        r_ prefix is a sign for read only registers

        BASE_ADDRESS_REGISTERS are the same as ones in the PCI Target configuration registers section. They

        are duplicated and therefor defined just ones and used with the same name as written below. If

        IMAGEx is NOT defined there is only parameter image_X assigned to '0' and this parameter is used

        elsewhere in the code. This parameter is defined in the INTERNAL SIGNALS part !!!

        Interrupt_Pin value 8'h01 is used for INT_A pin used.

        MIN_GNT and MAX_LAT are used for device's desired values for Latency Timer value. The value in boath

        registers specifies a period of time in units of 1/4 microsecond. ZERO indicates that there are no

        major requirements for the settings of Latency Timer.

        MIN_GNT specifieshow how long a burst period the device needs at 33MHz. MAX_LAT specifies how often

        the device needs to gain access to the PCI bus. Values are choosen assuming that the target does not

        insert any wait states. Follow the expamle of settings for simple display card.

        If we use 64 (32-bit) FIFO locations for one burst then we need 8 x 1/4 microsecond periods at 33MHz

        clock rate => MIN_GNT = 08h ! Resolution is 1024 x 768 (= 786432 pixels for one frame) with 16-bit

        color mode. We can transfere 2 16-bit pixels in one FIFO location. From that we calculate, that for

        one frame we need 6144 burst transferes in 1/25 second. So we need one burst every 6,51 microsecond

        and that is 26 x 1/4 microsecond or 1Ah x 1/4 microsecond => MAX_LAT = 1Ah !

-----------------------------------------------------------------------------------------------------------*/

                        // REG x 6              base_address_register_X                 IMPLEMENTED as          pci_ba_X !!!

                        // REG                  r_cardbus_cis_pointer                   NOT implemented !!!

                        // REG                  r_subsystem_vendor_id                   NOT implemented !!!

                        // REG                  r_subsystem_id                                  NOT implemented !!!

                        // REG                  r_expansion_rom_base_address    NOT implemented !!!

                        // REG                  r_cap_list_pointer                              NOT implemented !!!

                        reg             [7 : 0]  interrupt_line ;

                        parameter               r_interrupt_pin = 8'h01 ;

                        parameter               r_min_gnt = 8'h08 ;

                        parameter               r_max_lat = 8'h1a ;

/*###########################################################################################################

-------------------------------------------------------------------------------------------------------------

PCI Bridge default image SIZE parameters

        This parameters are not part of any register group, but are needed for default image size configuration

        used in PCI Target and WISHBONE Slave configuration registers!

-------------------------------------------------------------------------------------------------------------

###########################################################################################################*/

/*-----------------------------------------------------------------------------------------------------------

        PCI Target default image size parameters are defined with masked bits for address mask registers of

        each image space. By default there are 1MByte of address space defined for def_pci_imageX_addr_map

        parameters!

-----------------------------------------------------------------------------------------------------------*/

                wire    [19:0]   def_pci_image0_addr_map = `PCI_AM0 ;

                wire    [19:0]   def_pci_image1_addr_map = `PCI_AM1 ;

                wire    [19:0]   def_pci_image2_addr_map = `PCI_AM2 ;

                wire    [19:0]   def_pci_image3_addr_map = `PCI_AM3 ;

                wire    [19:0]   def_pci_image4_addr_map = `PCI_AM4 ;

                wire    [19:0]   def_pci_image5_addr_map = `PCI_AM5 ;

/*-----------------------------------------------------------------------------------------------------------

        WISHBONE Slave default image size parameters are defined with masked bits for address mask registers

        of each image space. By default there are 1MByte of address space defined for def_wb_imageX_addr_map

        parameters except for def_wb_image0_addr_map which is used for configuration space!

-----------------------------------------------------------------------------------------------------------*/

                        // PARAMETER    def_wb_image0_addr_map  IMPLEMENTED as r_wb_am0 parameter for CONF. space !!!

                wire    [19:0]   def_wb_image1_addr_map = 20'h0000_0 ;

                wire    [19:0]   def_wb_image2_addr_map = 20'h0000_0 ;

                wire    [19:0]   def_wb_image3_addr_map = 20'h0000_0 ;

                wire    [19:0]   def_wb_image4_addr_map = 20'h0000_0 ;

                wire    [19:0]   def_wb_image5_addr_map = 20'h0000_0 ;

/*###########################################################################################################

-------------------------------------------------------------------------------------------------------------

PCI Target configuration registers

        There are also some registers with NOT all bits implemented and therefor uses _bitX or _bitX2_X1 to

        sign which bit or range of bits are implemented. Some special cases and examples are described below!

-------------------------------------------------------------------------------------------------------------

###########################################################################################################*/

/*-----------------------------------------------------------------------------------------------------------

[100h-168h]

        Depending on defines (PCI_IMAGE1 or .. or PCI_IMAGE5 or (PCI_IMAGE0 and HOST)) in constants.v file,

        there are registers corresponding to each IMAGE defined to REG and parameter pci_image_X assigned to '1'.

        The maximum number of images is "6". By default there are first two images used and the first (PCI_IMAGE0)

        is assigned to Configuration space! With a 'define' PCI_IMAGEx you choose the number of used PCI IMAGES

        in a bridge without PCI_IMAGE0 (e.g. PCI_IMAGE3 tells, that PCI_IMAGE1, PCI_IMAGE2 and PCI_IMAGE3 are

        used for mapping the space from WB to PCI. Offcourse, PCI_IMAGE0 is assigned to Configuration space).

        That leave us PCI_IMAGE5 as the maximum number of images.

        There is one exeption, when the core is implemented as HOST. If so, then the PCI specification allowes

        the Configuration space NOT to be visible on the PCI bus. With `define PCI_IMAGE0 (and `define HOST), we

        assign PCI_IMAGE0 to normal WB to PCI image and not to configuration space!

        When error occurs, PCI ERR_ADDR and ERR_DATA registers stores address and data on the bus that

        caused error. While ERR_CS register stores Byte Enables and Bus Command in the MSByte. In bits 10

        and 8 it reports Retry Counter Expired (for posted writes), Error Source (Master Abort) and Error

        Report Signal (signals that error has occured) respectively. With bit 0 we enable Error Reporting

        mechanism.

-----------------------------------------------------------------------------------------------------------*/

`ifdef          HOST

        `ifdef  NO_CNF_IMAGE

                `ifdef  PCI_IMAGE0      // if PCI bridge is HOST and IMAGE0 is assigned as general image space

                        reg             [31 : 12]       pci_ba0_bit31_12 ;

                        reg             [2 : 1]         pci_img_ctrl0_bit2_1 ;

                        reg                                     pci_ba0_bit0 ;

                        reg             [31 : 12]       pci_am0 ;

                        reg             [31 : 12]       pci_ta0 ;

                `else // if PCI bridge is HOST and IMAGE0 is not used

                        wire    [31 : 12]       pci_ba0_bit31_12 = 20'h0000_0 ; // NO base address needed

                        wire    [2 : 1]         pci_img_ctrl0_bit2_1 = 2'b00 ; // NO addr.transl. and pre-fetch

                        wire                            pci_ba0_bit0 = 0 ; // config. space is MEMORY space

                        wire    [31 : 12]       pci_am0 = 20'h0000_0 ; // NO address mask needed

                        wire    [31 : 12]       pci_ta0 = 20'h0000_0 ; // NO address translation needed

                `endif

        `else // if PCI bridge is HOST and IMAGE0 is assigned to PCI configuration space

                        reg             [31 : 12]       pci_ba0_bit31_12 ;

                        wire    [2 : 1]         pci_img_ctrl0_bit2_1 = 2'b00 ; // NO pre-fetch and read line support

                        wire                            pci_ba0_bit0 = 0 ; // config. space is MEMORY space

                        wire    [31 : 12]       pci_am0 = def_pci_image0_addr_map ; // 20'hffff_f ; // 4KBytes of configuration space

                        wire    [31 : 12]       pci_ta0 = 20'h0000_0 ; // NO address translation needed

        `endif

`else // if PCI bridge is GUEST, then IMAGE0 is assigned to PCI configuration space

                        reg             [31 : 12]       pci_ba0_bit31_12 ;

                        wire    [2 : 1]         pci_img_ctrl0_bit2_1 = 2'b00 ; // NO addr.transl. and pre-fetch

                        wire                            pci_ba0_bit0 = 0 ; // config. space is MEMORY space

                        wire    [31 : 12]       pci_am0 = def_pci_image0_addr_map ; // 20'hffff_f ; // 4KBytes of configuration space

                        wire    [31 : 12]       pci_ta0 = 20'h0000_0 ; // NO address translation needed

`endif

// IMAGE1 is included by default, meanwhile other IMAGEs are optional !!!

                        reg             [2 : 1]         pci_img_ctrl1_bit2_1 ;

                        reg             [31 : 12]       pci_ba1_bit31_12 ;

        `ifdef  HOST

                        reg                                     pci_ba1_bit0 ;

        `else

                        wire                            pci_ba1_bit0 = `PCI_BA1_MEM_IO ;

        `endif

                        reg             [31 : 12]       pci_am1 ;

                        reg             [31 : 12]       pci_ta1 ;

`ifdef          PCI_IMAGE2

                        reg             [2 : 1]         pci_img_ctrl2_bit2_1 ;

                        reg             [31 : 12]       pci_ba2_bit31_12 ;

        `ifdef  HOST

                        reg                                     pci_ba2_bit0 ;

        `else

                        wire                            pci_ba2_bit0 = `PCI_BA2_MEM_IO ;

        `endif

                        reg             [31 : 12]       pci_am2 ;

                        reg             [31 : 12]       pci_ta2 ;

`else

            wire        [2 : 1]         pci_img_ctrl2_bit2_1 = 2'b00 ;

                        wire    [31 : 12]       pci_ba2_bit31_12 = 20'h0000_0 ;

            wire                                pci_ba2_bit0 = 1'b0 ;

            wire        [31 : 12]       pci_am2 = 20'h0000_0 ;

            wire        [31 : 12]       pci_ta2 = 20'h0000_0 ;

`endif

`ifdef          PCI_IMAGE3

                        reg             [2 : 1]         pci_img_ctrl3_bit2_1 ;

                        reg             [31 : 12]       pci_ba3_bit31_12 ;

        `ifdef  HOST

                        reg                                     pci_ba3_bit0 ;

        `else

                        wire                            pci_ba3_bit0 = `PCI_BA3_MEM_IO ;

        `endif

                        reg             [31 : 12]       pci_am3 ;

                        reg             [31 : 12]       pci_ta3 ;

`else

            wire        [2 : 1]         pci_img_ctrl3_bit2_1 = 2'b00 ;

                        wire    [31 : 12]       pci_ba3_bit31_12 = 20'h0000_0 ;

            wire                                pci_ba3_bit0 = 1'b0 ;

            wire        [31 : 12]       pci_am3 = 20'h0000_0 ;

            wire        [31 : 12]       pci_ta3 = 20'h0000_0 ;

`endif

`ifdef          PCI_IMAGE4

                        reg             [2 : 1]         pci_img_ctrl4_bit2_1 ;

                        reg             [31 : 12]       pci_ba4_bit31_12 ;

        `ifdef  HOST

                        reg                                     pci_ba4_bit0 ;

        `else

                        wire                            pci_ba4_bit0 = `PCI_BA4_MEM_IO ;

        `endif

                        reg             [31 : 12]       pci_am4 ;

                        reg             [31 : 12]       pci_ta4 ;

`else

            wire        [2 : 1]         pci_img_ctrl4_bit2_1 = 2'b00 ;

                        wire    [31 : 12]       pci_ba4_bit31_12 = 20'h0000_0 ;

            wire                                pci_ba4_bit0 = 1'b0 ;

            wire        [31 : 12]       pci_am4 = 20'h0000_0 ;

            wire        [31 : 12]       pci_ta4 = 20'h0000_0 ;

`endif

`ifdef          PCI_IMAGE5

                        reg             [2 : 1]         pci_img_ctrl5_bit2_1 ;

                        reg             [31 : 12]       pci_ba5_bit31_12 ;

        `ifdef  HOST

                        reg                                     pci_ba5_bit0 ;

        `else

                        wire                            pci_ba5_bit0 = `PCI_BA5_MEM_IO ;

        `endif

                        reg             [31 : 12]       pci_am5 ;

                        reg             [31 : 12]       pci_ta5 ;

`else

            wire        [2 : 1]         pci_img_ctrl5_bit2_1 = 2'b00 ;

                        wire    [31 : 12]       pci_ba5_bit31_12 = 20'h0000_0 ;

            wire                                pci_ba5_bit0 = 1'b0 ;

            wire        [31 : 12]       pci_am5 = 20'h0000_0 ;

            wire        [31 : 12]       pci_ta5 = 20'h0000_0 ;

`endif

                        reg             [31 : 24]       pci_err_cs_bit31_24 ;

                        reg                                     pci_err_cs_bit10 ;

                        reg                                     pci_err_cs_bit9 ;

                        reg                                     pci_err_cs_bit8 ;

                        reg                                     pci_err_cs_bit0 ;

                        reg             [31 : 0] pci_err_addr ;

                        reg             [31 : 0] pci_err_data ;

/*###########################################################################################################

-------------------------------------------------------------------------------------------------------------

WISHBONE Slave configuration registers

        There are also some registers with NOT all bits implemented and therefor uses _bitX or _bitX2_X1 to

        sign which bit or range of bits are implemented. Some special cases and examples are described below!

-------------------------------------------------------------------------------------------------------------

###########################################################################################################*/

/*-----------------------------------------------------------------------------------------------------------

[800h-85Ch]

        Depending on defines (WB_IMAGE1 or .. or WB_IMAGE4 or WB_IMAGE5) in constants.v file, there are

        registers corresponding to each IMAGE defined to REG and parameter wb_image_X assigned to '1'.

        The maximum number of images is "6". By default there are first two images used and the first (WB_IMAGE0)

        is assigned to Configuration space! With a 'define' WB_IMAGEx you choose the number of used WB IMAGES in

        a bridge without WB_IMAGE0 (e.g. WB_IMAGE3 tells, that WB_IMAGE1, WB_IMAGE2 and WB_IMAGE3 are used for

        mapping the space from PCI to WB. Offcourse, WB_IMAGE0 is assigned to Configuration space). That leave

        us WB_IMAGE5 as the maximum number of images.

        When error occurs, WISHBONE ERR_ADDR and ERR_DATA registers stores address and data on the bus that

        caused error. While ERR_CS register stores Byte Enables and Bus Command in the MSByte. In bits 10, 9

        and 8 it reports Retry Counter Expired (for posted writes), Error Source (Master Abort) and Error

        Report Signal (signals that error has occured) respectively. With bit 0 we enable Error Reporting

        mechanism.

-----------------------------------------------------------------------------------------------------------*/

// WB_IMAGE0 is always assigned to config. space or is not used

                        wire    [2 : 0]          wb_img_ctrl0_bit2_0 = 3'b000 ; // NO addr.transl., pre-fetch and read-line

                        wire    [31 : 12]       wb_ba0_bit31_12 = `WB_CONFIGURATION_BASE ;

                        wire                            wb_ba0_bit0 = 0 ; // config. space is MEMORY space

                        wire    [31 : 12]       wb_am0 = `WB_AM0 ; // 4KBytes of configuration space is minimum

                        wire    [31 : 12]       wb_ta0 = 20'h0000_0 ; // NO address translation needed

// WB_IMAGE1 is included by default meanwhile others are optional !

                        reg             [2 : 0]          wb_img_ctrl1_bit2_0 ;

                        reg             [31 : 12]       wb_ba1_bit31_12 ;

                        reg                                     wb_ba1_bit0 ;

                        reg             [31 : 12]       wb_am1 ;

                        reg             [31 : 12]       wb_ta1 ;

`ifdef          WB_IMAGE2

                        reg             [2 : 0]          wb_img_ctrl2_bit2_0 ;

                        reg             [31 : 12]       wb_ba2_bit31_12 ;

                        reg                                     wb_ba2_bit0 ;

                        reg             [31 : 12]       wb_am2 ;

                        reg             [31 : 12]       wb_ta2 ;

`else

            wire        [2 : 0]          wb_img_ctrl2_bit2_0 = 3'b000 ;

                        wire    [31 : 12]       wb_ba2_bit31_12 = 20'h0000_0 ;

            wire                                wb_ba2_bit0 = 1'b0 ;

            wire        [31 : 12]       wb_am2 = 20'h0000_0 ;

            wire        [31 : 12]       wb_ta2 = 20'h0000_0 ;

`endif

`ifdef          WB_IMAGE3

                        reg             [2 : 0]          wb_img_ctrl3_bit2_0 ;

                        reg             [31 : 12]       wb_ba3_bit31_12 ;

                        reg                                     wb_ba3_bit0 ;

                        reg             [31 : 12]       wb_am3 ;

                        reg             [31 : 12]       wb_ta3 ;

`else

            wire        [2 : 0]          wb_img_ctrl3_bit2_0 = 3'b000 ;

                        wire    [31 : 12]       wb_ba3_bit31_12 = 20'h0000_0 ;

            wire                                wb_ba3_bit0 = 1'b0 ;

            wire        [31 : 12]       wb_am3 = 20'h0000_0 ;

            wire        [31 : 12]       wb_ta3 = 20'h0000_0 ;

`endif

`ifdef          WB_IMAGE4

                        reg             [2 : 0]          wb_img_ctrl4_bit2_0 ;

                        reg             [31 : 12]       wb_ba4_bit31_12 ;

                        reg                                     wb_ba4_bit0 ;

                        reg             [31 : 12]       wb_am4 ;

                        reg             [31 : 12]       wb_ta4 ;

`else

            wire        [2 : 0]          wb_img_ctrl4_bit2_0 = 3'b000 ;

                        wire    [31 : 12]       wb_ba4_bit31_12 = 20'h0000_0 ;

            wire                                wb_ba4_bit0 = 1'b0 ;

            wire        [31 : 12]       wb_am4 = 20'h0000_0 ;

            wire        [31 : 12]       wb_ta4 = 20'h0000_0 ;

`endif

`ifdef          WB_IMAGE5

                        reg             [2 : 0]          wb_img_ctrl5_bit2_0 ;

                        reg             [31 : 12]       wb_ba5_bit31_12 ;

                        reg                                     wb_ba5_bit0 ;

                        reg             [31 : 12]       wb_am5 ;

                        reg             [31 : 12]       wb_ta5 ;

`else

            wire        [2 : 0]          wb_img_ctrl5_bit2_0 = 3'b000 ;

                        wire    [31 : 12]       wb_ba5_bit31_12 = 20'h0000_0 ;

            wire                                wb_ba5_bit0 = 1'b0 ;

            wire        [31 : 12]       wb_am5 = 20'h0000_0 ;

            wire        [31 : 12]       wb_ta5 = 20'h0000_0 ;

`endif

                        reg             [31 : 24]       wb_err_cs_bit31_24 ;

/*                      reg                                     wb_err_cs_bit10 ;*/

                        reg                                     wb_err_cs_bit9 ;

                        reg                                     wb_err_cs_bit8 ;

                        reg                                     wb_err_cs_bit0 ;

                        reg             [31 : 0] wb_err_addr ;

                        reg             [31 : 0] wb_err_data ;

/*###########################################################################################################

-------------------------------------------------------------------------------------------------------------

Configuration Cycle address register

        There are also some registers with NOT all bits implemented and therefor uses _bitX or _bitX2_X1 to

        sign which bit or range of bits are implemented.

-------------------------------------------------------------------------------------------------------------

###########################################################################################################*/

/*-----------------------------------------------------------------------------------------------------------

[860h-868h]