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//////////////////////////////////////////////////////////////////////
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//// ////
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//// File name "wbw_wbr_fifos.v" ////
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//// ////
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//// This file is part of the "PCI bridge" project ////
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//// http://www.opencores.org/cores/pci/ ////
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//// ////
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//// Author(s): ////
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//// - Miha Dolenc (mihad@opencores.org) ////
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//// ////
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//// All additional information is avaliable in the README ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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mihad |
// Revision 1.2 2001/10/05 08:20:12 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// New project directory structure
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//
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//
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`include "pci_constants.v"
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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mihad |
module WBW_WBR_FIFOS(
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wb_clock_in,
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pci_clock_in,
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reset_in,
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wbw_wenable_in,
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wbw_addr_data_in,
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wbw_cbe_in,
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wbw_control_in,
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wbw_renable_in,
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wbw_addr_data_out,
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wbw_cbe_out,
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wbw_control_out,
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wbw_flush_in,
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wbw_almost_full_out,
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wbw_full_out,
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wbw_empty_out,
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wbw_transaction_ready_out,
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wbr_wenable_in,
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wbr_data_in,
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wbr_be_in,
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wbr_control_in,
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wbr_renable_in,
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wbr_data_out,
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wbr_be_out,
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wbr_control_out,
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wbr_flush_in,
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wbr_empty_out
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) ;
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/*-----------------------------------------------------------------------------------------------------------
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System inputs:
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wb_clock_in - WISHBONE bus clock
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pci_clock_in - PCI bus clock
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reset_in - reset from control logic
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-------------------------------------------------------------------------------------------------------------*/
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input wb_clock_in, pci_clock_in, reset_in ;
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/*-----------------------------------------------------------------------------------------------------------
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WISHBONE WRITE FIFO interface signals prefixed with wbw_ - FIFO is used for posted writes initiated by
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WISHBONE master, traveling through FIFO and are completed on PCI by PCI master interface
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write enable signal:
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wbw_wenable_in = write enable input for WBW_FIFO - driven by WISHBONE slave interface
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data input signals:
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wbw_addr_data_in = data input - data from WISHBONE bus - first entry of transaction is address others are data entries
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wbw_cbe_in = bus command/byte enable(~SEL[3:0]) input - first entry of transaction is bus command, other are byte enables
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wbw_control_in = control input - encoded control bus input
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read enable signal:
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wbw_renable_in = read enable input driven by PCI master interface
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data output signals:
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wbw_addr_data_out = data output - data from WISHBONE bus - first entry of transaction is address, others are data entries
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wbw_cbe_out = bus command/byte enable output - first entry of transaction is bus command, others are byte enables
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wbw_control_out = control input - encoded control bus input
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status signals - monitored by various resources in the core
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wbw_flush_in = flush signal input for WBW_FIFO - when asserted, fifo is flushed(emptied)
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wbw_almost_full_out = almost full output from WBW_FIFO
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wbw_full_out = full output from WBW_FIFO
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wbw_empty_out = empty output from WBW_FIFO
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wbw_transaction_ready_out = output indicating that one complete transaction is waiting in WBW_FIFO
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-----------------------------------------------------------------------------------------------------------*/
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// input control and data
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input wbw_wenable_in ;
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input [31:0] wbw_addr_data_in ;
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input [3:0] wbw_cbe_in ;
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input [3:0] wbw_control_in ;
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// output control and data
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input wbw_renable_in ;
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output [31:0] wbw_addr_data_out ;
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output [3:0] wbw_cbe_out ;
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output [3:0] wbw_control_out ;
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// flush input
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input wbw_flush_in ;
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mihad |
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// status outputs
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output wbw_almost_full_out ;
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output wbw_full_out ;
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output wbw_empty_out ;
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output wbw_transaction_ready_out ;
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/*-----------------------------------------------------------------------------------------------------------
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mihad |
WISHBONE READ FIFO interface signals prefixed with wbr_ - FIFO is used for holding delayed read completions
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initiated by master on WISHBONE bus and completed on PCI bus,
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mihad |
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write enable signal:
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wbr_wenable_in = write enable input for WBR_FIFO - driven by PCI master interface
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data input signals:
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wbr_data_in = data input - data from PCI bus - there is no address entry here, since address is stored in separate register
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wbr_be_in = byte enable(~BE#[3:0]) input - byte enables - same through one transaction
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wbr_control_in = control input - encoded control bus input
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read enable signal:
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wbr_renable_in = read enable input driven by WISHBONE slave interface
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data output signals:
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wbr_data_out = data output - data from PCI bus
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wbr_be_out = byte enable output(~#BE)
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wbr_control_out = control output - encoded control bus output
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status signals - monitored by various resources in the core
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wbr_flush_in = flush signal input for WBR_FIFO - when asserted, fifo is flushed(emptied)
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wbr full_out = full output from WBR_FIFO
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wbr_empty_out = empty output from WBR_FIFO
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-----------------------------------------------------------------------------------------------------------*/
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// input control and data
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input wbr_wenable_in ;
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input [31:0] wbr_data_in ;
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input [3:0] wbr_be_in ;
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mihad |
input [3:0] wbr_control_in ;
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2 |
mihad |
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// output control and data
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input wbr_renable_in ;
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output [31:0] wbr_data_out ;
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output [3:0] wbr_be_out ;
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mihad |
output [3:0] wbr_control_out ;
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2 |
mihad |
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// flush input
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mihad |
input wbr_flush_in ;
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mihad |
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output wbr_empty_out ;
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/*-----------------------------------------------------------------------------------------------------------
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FIFO depth parameters:
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WBW_DEPTH = defines WBW_FIFO depth
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WBR_DEPTH = defines WBR_FIFO depth
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WBW_ADDR_LENGTH = defines WBW_FIFO's location address length = log2(WBW_DEPTH)
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WBR_ADDR_LENGTH = defines WBR_FIFO's location address length = log2(WBR_DEPTH)
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-----------------------------------------------------------------------------------------------------------*/
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parameter WBW_DEPTH = `WBW_DEPTH ;
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parameter WBW_ADDR_LENGTH = `WBW_ADDR_LENGTH ;
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parameter WBR_DEPTH = `WBR_DEPTH ;
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parameter WBR_ADDR_LENGTH = `WBR_ADDR_LENGTH ;
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// obvious
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wire vcc = 1'b1 ;
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wire gnd = 1'b0 ;
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/*-----------------------------------------------------------------------------------------------------------
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wbw_wallow = WBW_FIFO write allow wire - writes to FIFO are allowed when FIFO isn't full and write enable is 1
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wbw_rallow = WBW_FIFO read allow wire - reads from FIFO are allowed when FIFO isn't empty and read enable is 1
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-----------------------------------------------------------------------------------------------------------*/
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wire wbw_wallow ;
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wire wbw_rallow ;
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/*-----------------------------------------------------------------------------------------------------------
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wbr_wallow = WBR_FIFO write allow wire - writes to FIFO are allowed when FIFO isn't full and write enable is 1
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wbr_rallow = WBR_FIFO read allow wire - reads from FIFO are allowed when FIFO isn't empty and read enable is 1
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-----------------------------------------------------------------------------------------------------------*/
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wire wbr_wallow ;
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wire wbr_rallow ;
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/*-----------------------------------------------------------------------------------------------------------
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wires for address port conections from WBW_FIFO control logic to RAM blocks used for WBW_FIFO
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-----------------------------------------------------------------------------------------------------------*/
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wire [(WBW_ADDR_LENGTH - 1):0] wbw_raddr ;
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wire [(WBW_ADDR_LENGTH - 1):0] wbw_waddr ;
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/*-----------------------------------------------------------------------------------------------------------
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wires for address port conections from WBR_FIFO control logic to RAM blocks used for WBR_FIFO
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-----------------------------------------------------------------------------------------------------------*/
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wire [(WBR_ADDR_LENGTH - 1):0] wbr_raddr ;
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wire [(WBR_ADDR_LENGTH - 1):0] wbr_waddr ;
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/*-----------------------------------------------------------------------------------------------------------
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WBW_FIFO transaction counters: used to count incoming transactions and outgoing transactions. When number of
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input transactions is equal to number of output transactions, it means that there isn't any complete transaction
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currently present in the FIFO.
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-----------------------------------------------------------------------------------------------------------*/
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reg [(WBW_ADDR_LENGTH - 2):0] wbw_inTransactionCount ;
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reg [(WBW_ADDR_LENGTH - 2):0] wbw_outTransactionCount ;
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/*-----------------------------------------------------------------------------------------------------------
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wires monitoring control bus. When control bus on a write transaction has a value of `LAST, it means that
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complete transaction is in the FIFO. When control bus on a read transaction has a value of `LAST,
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it means that there was one complete transaction taken out of FIFO.
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-----------------------------------------------------------------------------------------------------------*/
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wire wbw_last_in = wbw_control_in[`LAST_CTRL_BIT] ;
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wire wbw_last_out = wbw_control_out[`LAST_CTRL_BIT] ;
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wire wbw_empty ;
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wire wbr_empty ;
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assign wbw_empty_out = wbw_empty ;
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assign wbr_empty_out = wbr_empty ;
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// clear wires for fifos
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wire wbw_clear = reset_in || wbw_flush_in ; // WBW_FIFO clear
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wire wbr_clear = reset_in || wbr_flush_in ; // WBR_FIFO clear
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/*-----------------------------------------------------------------------------------------------------------
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21 |
mihad |
Definitions of wires for connecting RAM instances
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2 |
mihad |
-----------------------------------------------------------------------------------------------------------*/
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21 |
mihad |
wire [39:0] dpram_portA_output ;
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wire [39:0] dpram_portB_output ;
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2 |
mihad |
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21 |
mihad |
wire [39:0] dpram_portA_input = {wbw_control_in, wbw_cbe_in, wbw_addr_data_in} ;
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wire [39:0] dpram_portB_input = {wbr_control_in, wbr_be_in, wbr_data_in} ;
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2 |
mihad |
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21 |
mihad |
/*-----------------------------------------------------------------------------------------------------------
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264 |
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Fifo output assignments - each ram port provides data for different fifo
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265 |
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-----------------------------------------------------------------------------------------------------------*/
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266 |
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assign wbw_control_out = dpram_portB_output[39:36] ;
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267 |
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assign wbr_control_out = dpram_portA_output[39:36] ;
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2 |
mihad |
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269 |
21 |
mihad |
assign wbw_cbe_out = dpram_portB_output[35:32] ;
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270 |
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assign wbr_be_out = dpram_portA_output[35:32] ;
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271 |
2 |
mihad |
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272 |
21 |
mihad |
assign wbw_addr_data_out = dpram_portB_output[31:0] ;
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273 |
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assign wbr_data_out = dpram_portA_output[31:0] ;
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274 |
2 |
mihad |
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275 |
21 |
mihad |
`ifdef WB_RAM_DONT_SHARE
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276 |
2 |
mihad |
|
277 |
21 |
mihad |
/*-----------------------------------------------------------------------------------------------------------
|
278 |
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Piece of code in this ifdef section is used in applications which can provide enough RAM instances to
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279 |
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accomodate four fifos - each occupying its own instance of ram. Ports are connected in such a way,
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280 |
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that instances of RAMs can be changed from two port to dual port ( async read/write port ). In that case,
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281 |
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write port is always port a and read port is port b.
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282 |
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-----------------------------------------------------------------------------------------------------------*/
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283 |
2 |
mihad |
|
284 |
21 |
mihad |
/*-----------------------------------------------------------------------------------------------------------
|
285 |
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Pad redundant address lines with zeros. This may seem stupid, but it comes in perfect for FPGA impl.
|
286 |
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-----------------------------------------------------------------------------------------------------------*/
|
287 |
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/*
|
288 |
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wire [(`WBW_FIFO_RAM_ADDR_LENGTH - WBW_ADDR_LENGTH - 1):0] wbw_addr_prefix = {( `WBW_FIFO_RAM_ADDR_LENGTH - WBW_ADDR_LENGTH){1'b0}} ;
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289 |
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wire [(`WBR_FIFO_RAM_ADDR_LENGTH - WBR_ADDR_LENGTH - 1):0] wbr_addr_prefix = {( `WBR_FIFO_RAM_ADDR_LENGTH - WBR_ADDR_LENGTH){1'b0}} ;
|
290 |
|
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*/
|
291 |
2 |
mihad |
|
292 |
21 |
mihad |
// compose complete port addresses
|
293 |
|
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wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] wbw_whole_waddr = wbw_waddr ;
|
294 |
|
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wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] wbw_whole_raddr = wbw_raddr ;
|
295 |
2 |
mihad |
|
296 |
21 |
mihad |
wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] wbr_whole_waddr = wbr_waddr ;
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297 |
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wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] wbr_whole_raddr = wbr_raddr ;
|
298 |
2 |
mihad |
|
299 |
21 |
mihad |
wire wbw_read_enable = 1'b1 ;
|
300 |
|
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wire wbr_read_enable = 1'b1 ;
|
301 |
2 |
mihad |
|
302 |
21 |
mihad |
// instantiate and connect two generic rams - one for wishbone write fifo and one for wishbone read fifo
|
303 |
|
|
WB_TPRAM #(`WB_FIFO_RAM_ADDR_LENGTH, 40) wbw_fifo_storage
|
304 |
|
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(
|
305 |
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// Generic synchronous two-port RAM interface
|
306 |
|
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.clk_a(wb_clock_in),
|
307 |
|
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.rst_a(reset_in),
|
308 |
|
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.ce_a(1'b1),
|
309 |
|
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.we_a(wbw_wallow),
|
310 |
|
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.oe_a(1'b1),
|
311 |
|
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.addr_a(wbw_whole_waddr),
|
312 |
|
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.di_a(dpram_portA_input),
|
313 |
|
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.do_a(),
|
314 |
2 |
mihad |
|
315 |
21 |
mihad |
.clk_b(pci_clock_in),
|
316 |
|
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.rst_b(reset_in),
|
317 |
|
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.ce_b(wbw_read_enable),
|
318 |
|
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.we_b(1'b0),
|
319 |
|
|
.oe_b(1'b1),
|
320 |
|
|
.addr_b(wbw_whole_raddr),
|
321 |
|
|
.di_b(40'h00_0000_0000),
|
322 |
|
|
.do_b(dpram_portB_output)
|
323 |
|
|
);
|
324 |
2 |
mihad |
|
325 |
21 |
mihad |
WB_TPRAM #(`WB_FIFO_RAM_ADDR_LENGTH, 40) wbr_fifo_storage
|
326 |
|
|
(
|
327 |
|
|
// Generic synchronous two-port RAM interface
|
328 |
|
|
.clk_a(pci_clock_in),
|
329 |
|
|
.rst_a(reset_in),
|
330 |
|
|
.ce_a(1'b1),
|
331 |
|
|
.we_a(wbr_wallow),
|
332 |
|
|
.oe_a(1'b1),
|
333 |
|
|
.addr_a(wbr_whole_waddr),
|
334 |
|
|
.di_a(dpram_portB_input),
|
335 |
|
|
.do_a(),
|
336 |
2 |
mihad |
|
337 |
21 |
mihad |
.clk_b(wb_clock_in),
|
338 |
|
|
.rst_b(reset_in),
|
339 |
|
|
.ce_b(wbr_read_enable),
|
340 |
|
|
.we_b(1'b0),
|
341 |
|
|
.oe_b(1'b1),
|
342 |
|
|
.addr_b(wbr_whole_raddr),
|
343 |
|
|
.di_b(40'h00_0000_0000),
|
344 |
|
|
.do_b(dpram_portA_output)
|
345 |
|
|
);
|
346 |
2 |
mihad |
|
347 |
21 |
mihad |
`else // RAM blocks sharing between two fifos
|
348 |
2 |
mihad |
|
349 |
21 |
mihad |
/*-----------------------------------------------------------------------------------------------------------
|
350 |
|
|
Code section under this ifdef is used for implementation where RAM instances are too expensive. In this
|
351 |
|
|
case one RAM instance is used for both - WISHBONE read and WISHBONE write fifo.
|
352 |
|
|
-----------------------------------------------------------------------------------------------------------*/
|
353 |
|
|
/*-----------------------------------------------------------------------------------------------------------
|
354 |
|
|
Address prefix definition - since both FIFOs reside in same RAM instance, storage is separated by MSB
|
355 |
|
|
addresses. WISHBONE write fifo addresses are padded with zeros on the MSB side ( at least one address line
|
356 |
|
|
must be used for this ), WISHBONE read fifo addresses are padded with ones on the right ( at least one ).
|
357 |
|
|
-----------------------------------------------------------------------------------------------------------*/
|
358 |
|
|
wire [(`WB_FIFO_RAM_ADDR_LENGTH - WBW_ADDR_LENGTH - 1):0] wbw_addr_prefix = {( `WB_FIFO_RAM_ADDR_LENGTH - WBW_ADDR_LENGTH){1'b0}} ;
|
359 |
|
|
wire [(`WB_FIFO_RAM_ADDR_LENGTH - WBR_ADDR_LENGTH - 1):0] wbr_addr_prefix = {( `WB_FIFO_RAM_ADDR_LENGTH - WBR_ADDR_LENGTH){1'b1}} ;
|
360 |
2 |
mihad |
|
361 |
|
|
/*-----------------------------------------------------------------------------------------------------------
|
362 |
21 |
mihad |
Port A address generation for RAM instance. RAM instance must be full two port RAM - read and write capability
|
363 |
|
|
on both sides.
|
364 |
|
|
Port A is clocked by WISHBONE clock, DIA is input for wbw_fifo, DOA is output for wbr_fifo.
|
365 |
|
|
Address is multiplexed so operation can be switched between fifos. Default is a read on port.
|
366 |
2 |
mihad |
-----------------------------------------------------------------------------------------------------------*/
|
367 |
21 |
mihad |
wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] portA_addr = wbw_wallow ? {wbw_addr_prefix, wbw_waddr} : {wbr_addr_prefix, wbr_raddr} ;
|
368 |
|
|
|
369 |
|
|
/*-----------------------------------------------------------------------------------------------------------
|
370 |
|
|
Port B is clocked by PCI clock, DIB is input for wbr_fifo, DOB is output for wbw_fifo.
|
371 |
|
|
Address is multiplexed so operation can be switched between fifos. Default is a read on port.
|
372 |
|
|
-----------------------------------------------------------------------------------------------------------*/
|
373 |
|
|
wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] portB_addr = wbr_wallow ? {wbr_addr_prefix, wbr_waddr} : {wbw_addr_prefix, wbw_raddr} ;
|
374 |
|
|
|
375 |
|
|
wire portA_enable = 1'b1 ;
|
376 |
|
|
|
377 |
|
|
wire portB_enable = 1'b1 ;
|
378 |
|
|
|
379 |
|
|
// instantiate RAM for these two fifos
|
380 |
|
|
WB_TPRAM #(`WB_FIFO_RAM_ADDR_LENGTH, 40) wbu_fifo_storage
|
381 |
|
|
(
|
382 |
|
|
// Generic synchronous two-port RAM interface
|
383 |
|
|
.clk_a(wb_clock_in),
|
384 |
|
|
.rst_a(reset_in),
|
385 |
|
|
.ce_a(portA_enable),
|
386 |
|
|
.we_a(wbw_wallow),
|
387 |
|
|
.oe_a(1'b1),
|
388 |
|
|
.addr_a(portA_addr),
|
389 |
|
|
.di_a(dpram_portA_input),
|
390 |
|
|
.do_a(dpram_portA_output),
|
391 |
|
|
.clk_b(pci_clock_in),
|
392 |
|
|
.rst_b(reset_in),
|
393 |
|
|
.ce_b(portB_enable),
|
394 |
|
|
.we_b(wbr_wallow),
|
395 |
|
|
.oe_b(1'b1),
|
396 |
|
|
.addr_b(portB_addr),
|
397 |
|
|
.di_b(dpram_portB_input),
|
398 |
|
|
.do_b(dpram_portB_output)
|
399 |
|
|
);
|
400 |
|
|
|
401 |
2 |
mihad |
`endif
|
402 |
|
|
|
403 |
|
|
/*-----------------------------------------------------------------------------------------------------------
|
404 |
|
|
Instantiation of two control logic modules - one for WBW_FIFO and one for WBR_FIFO
|
405 |
|
|
-----------------------------------------------------------------------------------------------------------*/
|
406 |
|
|
WBW_FIFO_CONTROL #(WBW_ADDR_LENGTH) wbw_fifo_ctrl
|
407 |
21 |
mihad |
(
|
408 |
|
|
.rclock_in(pci_clock_in),
|
409 |
|
|
.wclock_in(wb_clock_in),
|
410 |
|
|
.renable_in(wbw_renable_in),
|
411 |
|
|
.wenable_in(wbw_wenable_in),
|
412 |
|
|
.reset_in(reset_in),
|
413 |
|
|
.flush_in(wbw_flush_in),
|
414 |
|
|
.almost_full_out(wbw_almost_full_out),
|
415 |
|
|
.full_out(wbw_full_out),
|
416 |
|
|
.empty_out(wbw_empty),
|
417 |
|
|
.waddr_out(wbw_waddr),
|
418 |
|
|
.raddr_out(wbw_raddr),
|
419 |
|
|
.rallow_out(wbw_rallow),
|
420 |
|
|
.wallow_out(wbw_wallow)
|
421 |
|
|
);
|
422 |
2 |
mihad |
|
423 |
|
|
WBR_FIFO_CONTROL #(WBR_ADDR_LENGTH) wbr_fifo_ctrl
|
424 |
21 |
mihad |
( .rclock_in(wb_clock_in),
|
425 |
|
|
.wclock_in(pci_clock_in),
|
426 |
|
|
.renable_in(wbr_renable_in),
|
427 |
|
|
.wenable_in(wbr_wenable_in),
|
428 |
|
|
.reset_in(reset_in),
|
429 |
|
|
.flush_in(wbr_flush_in),
|
430 |
|
|
.empty_out(wbr_empty),
|
431 |
|
|
.waddr_out(wbr_waddr),
|
432 |
|
|
.raddr_out(wbr_raddr),
|
433 |
|
|
.rallow_out(wbr_rallow),
|
434 |
|
|
.wallow_out(wbr_wallow)
|
435 |
|
|
);
|
436 |
2 |
mihad |
|
437 |
|
|
|
438 |
|
|
// in and out transaction counters and grey codes
|
439 |
|
|
reg [(WBW_ADDR_LENGTH-2):0] inGreyCount ;
|
440 |
|
|
reg [(WBW_ADDR_LENGTH-2):0] outGreyCount ;
|
441 |
|
|
wire [(WBW_ADDR_LENGTH-2):0] inNextGreyCount = {wbw_inTransactionCount[(WBW_ADDR_LENGTH-2)], wbw_inTransactionCount[(WBW_ADDR_LENGTH-2):1] ^ wbw_inTransactionCount[(WBW_ADDR_LENGTH-3):0]} ;
|
442 |
|
|
wire [(WBW_ADDR_LENGTH-2):0] outNextGreyCount = {wbw_outTransactionCount[(WBW_ADDR_LENGTH-2)], wbw_outTransactionCount[(WBW_ADDR_LENGTH-2):1] ^ wbw_outTransactionCount[(WBW_ADDR_LENGTH-3):0]} ;
|
443 |
|
|
|
444 |
21 |
mihad |
// input transaction counter increment - when last data of transaction is written to fifo
|
445 |
2 |
mihad |
wire in_count_en = wbw_wallow && wbw_last_in ;
|
446 |
21 |
mihad |
|
447 |
|
|
// output transaction counter increment - when last data is on top of fifo and read from it
|
448 |
2 |
mihad |
wire out_count_en = wbw_renable_in && wbw_last_out ;
|
449 |
|
|
|
450 |
21 |
mihad |
// register holding grey coded count of incoming transactions
|
451 |
2 |
mihad |
always@(posedge wb_clock_in or posedge wbw_clear)
|
452 |
|
|
begin
|
453 |
|
|
if (wbw_clear)
|
454 |
|
|
begin
|
455 |
|
|
inGreyCount[(WBW_ADDR_LENGTH-2)] <= #`FF_DELAY 1'b1 ;
|
456 |
|
|
inGreyCount[(WBW_ADDR_LENGTH-3):0] <= #`FF_DELAY {(WBW_ADDR_LENGTH-2),1'b0} ;
|
457 |
|
|
end
|
458 |
|
|
else
|
459 |
|
|
if (in_count_en)
|
460 |
|
|
inGreyCount <= #`FF_DELAY inNextGreyCount ;
|
461 |
|
|
end
|
462 |
|
|
|
463 |
21 |
mihad |
// register holding grey coded count of outgoing transactions
|
464 |
2 |
mihad |
always@(posedge pci_clock_in or posedge wbw_clear)
|
465 |
|
|
begin
|
466 |
|
|
if (wbw_clear)
|
467 |
|
|
begin
|
468 |
|
|
outGreyCount[(WBW_ADDR_LENGTH-2)] <= #`FF_DELAY 1'b1 ;
|
469 |
|
|
outGreyCount[(WBW_ADDR_LENGTH-3):0] <= #`FF_DELAY {(WBW_ADDR_LENGTH-2),1'b0} ;
|
470 |
|
|
end
|
471 |
|
|
else
|
472 |
|
|
if (out_count_en)
|
473 |
|
|
outGreyCount <= #`FF_DELAY outNextGreyCount ;
|
474 |
|
|
end
|
475 |
|
|
|
476 |
21 |
mihad |
// incoming transactions counter
|
477 |
2 |
mihad |
always@(posedge wb_clock_in or posedge wbw_clear)
|
478 |
|
|
begin
|
479 |
|
|
if (wbw_clear)
|
480 |
|
|
wbw_inTransactionCount <= #`FF_DELAY {(WBW_ADDR_LENGTH-1){1'b0}} ;
|
481 |
|
|
else
|
482 |
|
|
if (in_count_en)
|
483 |
|
|
wbw_inTransactionCount <= #`FF_DELAY wbw_inTransactionCount + 1'b1 ;
|
484 |
|
|
end
|
485 |
|
|
|
486 |
21 |
mihad |
// outgoing transactions counter
|
487 |
2 |
mihad |
always@(posedge pci_clock_in or posedge wbw_clear)
|
488 |
|
|
begin
|
489 |
|
|
if (wbw_clear)
|
490 |
|
|
wbw_outTransactionCount <= #`FF_DELAY {(WBW_ADDR_LENGTH-1){1'b0}} ;
|
491 |
|
|
else
|
492 |
|
|
if (out_count_en)
|
493 |
|
|
wbw_outTransactionCount <= #`FF_DELAY wbw_outTransactionCount + 1'b1 ;
|
494 |
|
|
end
|
495 |
|
|
|
496 |
|
|
// synchronize transaction ready output to reading clock
|
497 |
21 |
mihad |
// transaction ready is set when incoming transaction count is not equal to outgoing transaction count (what goes in must come out logic)
|
498 |
|
|
// transaction ready is cleared when whole transaction is pulled out of fifo (otherwise it could stay set for additional cycle and result in wrong op.)
|
499 |
2 |
mihad |
reg wbw_transaction_ready_out ;
|
500 |
|
|
always@(posedge pci_clock_in or posedge wbw_clear)
|
501 |
|
|
begin
|
502 |
|
|
if (wbw_clear)
|
503 |
|
|
wbw_transaction_ready_out <= #`FF_DELAY 1'b0 ;
|
504 |
|
|
else
|
505 |
|
|
if ( out_count_en )
|
506 |
|
|
wbw_transaction_ready_out <= #`FF_DELAY 1'b0 ;
|
507 |
|
|
else
|
508 |
|
|
wbw_transaction_ready_out <= #`FF_DELAY inGreyCount != outGreyCount ;
|
509 |
|
|
end
|
510 |
|
|
|
511 |
|
|
endmodule
|
512 |
|
|
|