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mihad |
//===========================================================================
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mihad |
// $Id: pci_behaviorial_device.v,v 1.2 2002-03-21 07:35:50 mihad Exp $
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mihad |
//
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// Copyright 2001 Blue Beaver. All Rights Reserved.
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//
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// Summary: A top-level PCI Behaviorial interface. This module instantiates
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// a number of behaviorial IO pads and a behaviorial PCI Master
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// and behaviorial PCI Target. Not much going on here.
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//
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// This library is free software; you can distribute it and/or modify it
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// under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful, but
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// WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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// See the GNU Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with this library. If not, write to
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// Free Software Foundation, Inc.
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// 59 Temple Place, Suite 330
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// Boston, MA 02111-1307 USA
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//
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// Author's note about this license: The intention of the Author and of
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// the Gnu Lesser General Public License is that users should be able to
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// use this code for any purpose, including combining it with other source
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// code, combining it with other logic, translated it into a gate-level
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// representation, or projected it into gates in a programmable or
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// hardwired chip, as long as the users of the resulting source, compiled
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// source, or chip are given the means to get a copy of this source code
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// with no new restrictions on redistribution of this source.
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//
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// If you make changes, even substantial changes, to this code, or use
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// substantial parts of this code as an inseparable part of another work
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// of authorship, the users of the resulting IP must be given the means
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// to get a copy of the modified or combined source code, with no new
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// restrictions on redistribution of the resulting source.
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//
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// Separate parts of the combined source code, compiled code, or chip,
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// which are NOT derived from this source code do NOT need to be offered
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// to the final user of the chip merely because they are used in
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// combination with this code. Other code is not forced to fall under
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// the GNU Lesser General Public License when it is linked to this code.
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// The license terms of other source code linked to this code might require
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// that it NOT be made available to users. The GNU Lesser General Public
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// License does not prevent this code from being used in such a situation,
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// as long as the user of the resulting IP is given the means to get a
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// copy of this component of the IP with no new restrictions on
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// redistribution of this source.
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//
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// This code was developed using VeriLogger Pro, by Synapticad.
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// Their support is greatly appreciated.
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//
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// NOTE: This Test Chip instantiates one PCI interface and connects it
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// to its IO pads and to logic representing a real application.
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//
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// NOTE: Needs to be improved to allow back-to-back transfers from
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// the same Master. I think the request is being held off
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// too long! But it might also be fast-back-to-back.
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//
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//===========================================================================
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mihad |
// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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mihad |
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module pci_behaviorial_device (
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pci_ext_ad, pci_ext_cbe_l, pci_ext_par,
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pci_ext_frame_l, pci_ext_irdy_l,
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pci_ext_devsel_l, pci_ext_trdy_l, pci_ext_stop_l,
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pci_ext_perr_l, pci_ext_serr_l,
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pci_ext_idsel,
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pci_ext_inta_l,
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pci_ext_req_l, pci_ext_gnt_l,
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pci_ext_reset_l, pci_ext_clk,
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// Signals used by the test bench instead of using "." notation
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test_observe_oe_sigs,
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test_master_number, test_address, test_command,
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test_data, test_byte_enables_l, test_size,
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test_make_addr_par_error, test_make_data_par_error,
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test_master_initial_wait_states, test_master_subsequent_wait_states,
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test_target_initial_wait_states, test_target_subsequent_wait_states,
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test_target_devsel_speed, test_fast_back_to_back,
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test_target_termination,
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test_expect_master_abort,
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test_start, test_accepted_l, test_error_event,
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test_device_id,
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test_target_response,
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master_received_data,
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master_received_data_valid,
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master_check_received_data
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);
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`include "pci_blue_options.vh"
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`include "pci_blue_constants.vh"
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inout [PCI_BUS_DATA_RANGE:0] pci_ext_ad;
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inout [PCI_BUS_CBE_RANGE:0] pci_ext_cbe_l;
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inout pci_ext_par;
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inout pci_ext_frame_l, pci_ext_irdy_l;
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inout pci_ext_devsel_l, pci_ext_trdy_l, pci_ext_stop_l;
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inout pci_ext_perr_l, pci_ext_serr_l;
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input pci_ext_idsel;
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inout pci_ext_inta_l;
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output pci_ext_req_l;
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input pci_ext_gnt_l;
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input pci_ext_reset_l, pci_ext_clk;
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// Test wires to make it easier to understand who is driving the bus
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output [5:0] test_observe_oe_sigs;
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input [2:0] test_master_number;
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input [PCI_BUS_DATA_RANGE:0] test_address;
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input [PCI_BUS_CBE_RANGE:0] test_command;
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input [PCI_BUS_DATA_RANGE:0] test_data;
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input [PCI_BUS_CBE_RANGE:0] test_byte_enables_l;
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input [9:0] test_size;
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input test_make_addr_par_error, test_make_data_par_error;
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input [3:0] test_master_initial_wait_states;
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input [3:0] test_master_subsequent_wait_states;
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input [3:0] test_target_initial_wait_states;
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input [3:0] test_target_subsequent_wait_states;
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input [1:0] test_target_devsel_speed;
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input test_fast_back_to_back;
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input [2:0] test_target_termination;
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input test_expect_master_abort;
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input test_start;
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output test_accepted_l;
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output test_error_event;
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input [2:0] test_device_id;
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input [25:0] test_target_response ;
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output [PCI_BUS_DATA_RANGE:0] master_received_data ;
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output master_received_data_valid ;
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input master_check_received_data ;
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// Make temporary Bip every time an error is detected
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reg test_error_event;
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initial test_error_event <= 1'bZ;
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wire master_error_event, target_error_event;
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reg error_detected;
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initial error_detected <= 1'b0;
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always @(error_detected or master_error_event or target_error_event)
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begin
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test_error_event <= 1'b0;
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#2;
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test_error_event <= 1'bZ;
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end
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// Assign local variables to board-level signals
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// NOTE: all of these output pads are combinational, not clocked, on output
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wire pci_reset_comb = ~pci_ext_reset_l;
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wire master_req;
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wire master_req_dly1, master_req_dly2;
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assign #`PAD_MIN_DATA_DLY master_req_dly1 = master_req;
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assign #`PAD_MAX_DATA_DLY master_req_dly2 = master_req;
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assign pci_ext_req_l = (master_req_dly1 !== master_req_dly2)
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? 1'bX : ~master_req_dly2;
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wire master_gnt_now = ~pci_ext_gnt_l;
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wire [PCI_BUS_DATA_RANGE:0] pci_ad_out;
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wire [PCI_BUS_DATA_RANGE:0] pci_ad_out_dly1, pci_ad_out_dly2;
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assign #`PAD_MIN_DATA_DLY pci_ad_out_dly1[PCI_BUS_DATA_RANGE:0] = pci_ad_out[PCI_BUS_DATA_RANGE:0];
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assign #`PAD_MAX_DATA_DLY pci_ad_out_dly2[PCI_BUS_DATA_RANGE:0] = pci_ad_out[PCI_BUS_DATA_RANGE:0];
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wire pci_ad_oe;
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wire pci_ad_oe_dly1, pci_ad_oe_dly2;
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assign #`PAD_MIN_OE_DLY pci_ad_oe_dly1 = pci_ad_oe;
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assign #`PAD_MAX_OE_DLY pci_ad_oe_dly2 = pci_ad_oe;
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wire force_ad_x = (pci_ad_oe_dly1 !== pci_ad_oe_dly2)
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| (pci_ad_oe & (pci_ad_out_dly1 !== pci_ad_out_dly2));
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assign pci_ext_ad[PCI_BUS_DATA_RANGE:0] = force_ad_x ? `PCI_BUS_DATA_X
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: (pci_ad_oe_dly2
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? pci_ad_out_dly2[PCI_BUS_DATA_RANGE:0]
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: `PCI_BUS_DATA_Z);
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// NOTE ad_now must have a bypass from internal data in the synthesized design
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wire [PCI_BUS_DATA_RANGE:0] ad_now = pci_ext_ad[PCI_BUS_DATA_RANGE:0];
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reg [PCI_BUS_DATA_RANGE:0] ad_prev;
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wire [PCI_BUS_CBE_RANGE:0] master_cbe_l_out;
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wire [PCI_BUS_CBE_RANGE:0] master_cbe_l_dly1, master_cbe_l_dly2;
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assign #`PAD_MIN_DATA_DLY master_cbe_l_dly1[PCI_BUS_CBE_RANGE:0] = master_cbe_l_out[PCI_BUS_CBE_RANGE:0];
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assign #`PAD_MAX_DATA_DLY master_cbe_l_dly2[PCI_BUS_CBE_RANGE:0] = master_cbe_l_out[PCI_BUS_CBE_RANGE:0];
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wire master_cbe_oe;
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wire master_cbe_oe_dly1, master_cbe_oe_dly2;
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assign #`PAD_MIN_OE_DLY master_cbe_oe_dly1 = master_cbe_oe;
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assign #`PAD_MAX_OE_DLY master_cbe_oe_dly2 = master_cbe_oe;
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wire force_cbe_x = (master_cbe_oe_dly1 !== master_cbe_oe_dly2)
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| (master_cbe_oe & (master_cbe_l_dly1 !== master_cbe_l_dly2));
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assign pci_ext_cbe_l[PCI_BUS_CBE_RANGE:0] = force_cbe_x ? `PCI_BUS_CBE_X
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: (master_cbe_oe_dly2
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? master_cbe_l_dly2[PCI_BUS_CBE_RANGE:0]
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: `PCI_BUS_CBE_Z);
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// NOTE cbe_l_now must have a bypass from internal data in the synthesized design
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wire [PCI_BUS_CBE_RANGE:0] cbe_l_now = pci_ext_cbe_l[PCI_BUS_CBE_RANGE:0];
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reg [PCI_BUS_CBE_RANGE:0] cbe_l_prev;
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always @(posedge pci_ext_clk)
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begin
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ad_prev[PCI_BUS_DATA_RANGE:0] <= pci_ext_ad[PCI_BUS_DATA_RANGE:0];
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cbe_l_prev[PCI_BUS_CBE_RANGE:0] <= pci_ext_cbe_l[PCI_BUS_CBE_RANGE:0];
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end
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wire idsel_now, idsel_prev, idsel_now_l, idsel_prev_l;
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delayed_test_pad test_pad_idsel (
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.external_sig (pci_ext_idsel), .data_in_comb (idsel_now_l),
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.data_in_prev (idsel_prev_l), .data_out_comb (1'b0),
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.data_oe_comb (1'b0), .pci_ext_clk (pci_ext_clk)
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);
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assign idsel_now = ~idsel_now_l;
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assign idsel_prev = ~idsel_prev_l;
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reg pci_par_out, pci_par_oe;
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wire par_now, par_prev, par_now_l, par_prev_l;
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delayed_test_pad test_pad_par (
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.external_sig (pci_ext_par), .data_in_comb (par_now_l),
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.data_in_prev (par_prev_l), .data_out_comb (pci_par_out),
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.data_oe_comb (pci_par_oe), .pci_ext_clk (pci_ext_clk)
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);
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assign par_now = ~par_now_l; // oups, want NON-inverted version of this
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assign par_prev = ~par_prev_l;
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wire master_frame_out, master_frame_oe;
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wire frame_now, frame_prev;
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delayed_test_pad test_pad_frame (
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.external_sig (pci_ext_frame_l), .data_in_comb (frame_now),
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.data_in_prev (frame_prev), .data_out_comb (~master_frame_out),
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.data_oe_comb (master_frame_oe), .pci_ext_clk (pci_ext_clk)
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);
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wire master_irdy_out, master_irdy_oe;
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wire irdy_now, irdy_prev;
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delayed_test_pad test_pad_irdy (
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.external_sig (pci_ext_irdy_l), .data_in_comb (irdy_now),
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.data_in_prev (irdy_prev), .data_out_comb (~master_irdy_out),
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.data_oe_comb (master_irdy_oe), .pci_ext_clk (pci_ext_clk)
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);
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wire target_devsel_out, target_d_t_s_oe;
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wire devsel_now, devsel_prev;
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delayed_test_pad test_pad_devsel (
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.external_sig (pci_ext_devsel_l), .data_in_comb (devsel_now),
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.data_in_prev (devsel_prev), .data_out_comb (~target_devsel_out),
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.data_oe_comb (target_d_t_s_oe), .pci_ext_clk (pci_ext_clk)
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);
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wire target_trdy_out; // shares target_d_t_s_oe
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wire trdy_prev, trdy_now;
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delayed_test_pad test_pad_trdy (
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.external_sig (pci_ext_trdy_l), .data_in_comb (trdy_now),
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.data_in_prev (trdy_prev), .data_out_comb (~target_trdy_out),
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.data_oe_comb (target_d_t_s_oe), .pci_ext_clk (pci_ext_clk)
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);
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wire target_stop_out; // shares target_d_t_s_oe
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wire stop_now, stop_prev;
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delayed_test_pad test_pad_stop (
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.external_sig (pci_ext_stop_l), .data_in_comb (stop_now),
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.data_in_prev (stop_prev), .data_out_comb (~target_stop_out),
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.data_oe_comb (target_d_t_s_oe), .pci_ext_clk (pci_ext_clk)
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);
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263 |
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wire pci_perr_out, pci_perr_oe;
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wire perr_now, perr_prev;
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delayed_test_pad test_pad_perr (
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.external_sig (pci_ext_perr_l), .data_in_comb (perr_now),
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.data_in_prev (perr_prev), .data_out_comb (~pci_perr_out),
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.data_oe_comb (pci_perr_oe), .pci_ext_clk (pci_ext_clk)
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);
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270 |
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271 |
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wire pci_serr_oe;
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wire serr_now, serr_prev;
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delayed_test_pad test_pad_serr (
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274 |
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.external_sig (pci_ext_serr_l), .data_in_comb (serr_now),
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.data_in_prev (serr_prev), .data_out_comb (1'b0),
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.data_oe_comb (pci_serr_oe), .pci_ext_clk (pci_ext_clk)
|
277 |
|
|
);
|
278 |
|
|
|
279 |
|
|
// Make visible the internal OE signals. This makes it MUCH easier to
|
280 |
|
|
// see who is using the bus during simulation.
|
281 |
|
|
// OE Observation signals are
|
282 |
|
|
// {frame_oe, irdy_oe, devsel_t_s_oe, ad_oe, cbe_oe, perr_oe}
|
283 |
|
|
assign test_observe_oe_sigs[5:0] = {master_frame_oe, master_irdy_oe,
|
284 |
|
|
target_d_t_s_oe, pci_ad_oe, master_cbe_oe, pci_perr_oe};
|
285 |
|
|
|
286 |
|
|
// Variables to give access to shared IO pins
|
287 |
|
|
wire [PCI_BUS_DATA_RANGE:0] master_ad_out;
|
288 |
|
|
wire master_par_out_next;
|
289 |
|
|
wire master_perr_out;
|
290 |
|
|
wire master_ad_oe, master_perr_oe, master_serr_oe;
|
291 |
|
|
wire master_debug_force_bad_par;
|
292 |
|
|
wire [PCI_BUS_DATA_RANGE:0] target_ad_out;
|
293 |
|
|
wire target_par_out_next;
|
294 |
|
|
wire target_perr_out;
|
295 |
|
|
wire target_ad_oe, target_perr_oe, target_serr_oe;
|
296 |
|
|
wire target_debug_force_bad_par;
|
297 |
|
|
|
298 |
|
|
// Shared Bus Wires which can be driven by the Master or the Target
|
299 |
|
|
assign pci_ad_out[PCI_BUS_DATA_RANGE:0] = master_ad_oe
|
300 |
|
|
? master_ad_out[PCI_BUS_DATA_RANGE:0]
|
301 |
|
|
: (target_ad_oe
|
302 |
|
|
? target_ad_out[PCI_BUS_DATA_RANGE:0]
|
303 |
|
|
: `PCI_BUS_DATA_X);
|
304 |
|
|
assign pci_ad_oe = master_ad_oe | target_ad_oe;
|
305 |
|
|
always @(posedge pci_ext_clk or posedge pci_reset_comb)
|
306 |
|
|
begin
|
307 |
|
|
if (pci_reset_comb)
|
308 |
|
|
begin
|
309 |
|
|
pci_par_oe <= 1'b0;
|
310 |
|
|
end
|
311 |
|
|
else
|
312 |
|
|
begin
|
313 |
|
|
pci_par_oe <= master_ad_oe | target_ad_oe;
|
314 |
|
|
end
|
315 |
|
|
end
|
316 |
|
|
assign master_par_out_next = (^master_ad_out[PCI_BUS_DATA_RANGE:0])
|
317 |
|
|
^ (^master_cbe_l_out[PCI_BUS_CBE_RANGE:0])
|
318 |
|
|
^ master_debug_force_bad_par;
|
319 |
|
|
assign target_par_out_next = (^target_ad_out[PCI_BUS_DATA_RANGE:0])
|
320 |
|
|
^ (^cbe_l_now[PCI_BUS_CBE_RANGE:0])
|
321 |
|
|
^ target_debug_force_bad_par;
|
322 |
|
|
always @(posedge pci_ext_clk)
|
323 |
|
|
begin
|
324 |
|
|
pci_par_out <= master_ad_oe ? master_par_out_next
|
325 |
|
|
: (target_ad_oe ? target_par_out_next : 1'bX);
|
326 |
|
|
end
|
327 |
|
|
assign pci_perr_out = master_perr_oe ? master_perr_out
|
328 |
|
|
: (target_perr_oe ? target_perr_out : 1'bX);
|
329 |
|
|
assign pci_perr_oe = master_perr_oe | target_perr_oe;
|
330 |
|
|
assign pci_serr_oe = master_serr_oe | target_serr_oe;
|
331 |
|
|
|
332 |
|
|
// synopsys translate_off
|
333 |
|
|
// Test for obvious errors in this test device
|
334 |
|
|
always @(posedge pci_ext_clk)
|
335 |
|
|
begin
|
336 |
|
|
if (master_ad_oe & target_ad_oe)
|
337 |
|
|
begin
|
338 |
|
|
$display ("*** test %h - Master and Target drive AD bus at the same time, at %t",
|
339 |
|
|
test_device_id[2:0], $time);
|
340 |
|
|
error_detected <= ~error_detected;
|
341 |
|
|
end
|
342 |
|
|
`NO_ELSE;
|
343 |
|
|
if (master_perr_oe & target_perr_oe)
|
344 |
|
|
begin
|
345 |
|
|
$display ("*** test %h - Master and Target drive PERR at the same time, at %t",
|
346 |
|
|
test_device_id[2:0], $time);
|
347 |
|
|
error_detected <= ~error_detected;
|
348 |
|
|
end
|
349 |
|
|
`NO_ELSE;
|
350 |
|
|
if (master_serr_oe & target_serr_oe)
|
351 |
|
|
begin
|
352 |
|
|
$display ("*** test %h - Master and Target drive SERR at the same time, at %t",
|
353 |
|
|
test_device_id[2:0], $time);
|
354 |
|
|
error_detected <= ~error_detected;
|
355 |
|
|
end
|
356 |
|
|
`NO_ELSE;
|
357 |
|
|
end
|
358 |
|
|
// synopsys translate_on
|
359 |
|
|
|
360 |
|
|
// Share a parity generator on inputs (Is this legal? Can't receive CBE in Master)
|
361 |
|
|
wire calc_input_parity_prev = (^ad_prev[PCI_BUS_DATA_RANGE:0])
|
362 |
|
|
^ (^cbe_l_prev[PCI_BUS_CBE_RANGE:0]) ;
|
363 |
|
|
// added by miha d for bad PERR generation
|
364 |
|
|
//^ target_debug_force_bad_par ;
|
365 |
|
|
|
366 |
|
|
// Master needs to report conditions to Target, which contains the Config Register
|
367 |
|
|
// If the system is a target only, these bits should all be wired to 0
|
368 |
|
|
wire master_got_parity_error, master_asserted_serr, master_got_master_abort;
|
369 |
|
|
wire master_got_target_abort, master_caused_parity_error;
|
370 |
|
|
wire master_enable, master_fast_b2b_en, master_perr_enable, master_serr_enable;
|
371 |
|
|
wire [7:0] master_latency_value;
|
372 |
|
|
|
373 |
|
|
pci_behaviorial_master pci_behaviorial_master (
|
374 |
|
|
.ad_now (ad_now[PCI_BUS_DATA_RANGE:0]),
|
375 |
|
|
.ad_prev (ad_prev[PCI_BUS_DATA_RANGE:0]),
|
376 |
|
|
.calc_input_parity_prev (calc_input_parity_prev),
|
377 |
|
|
.master_ad_out (master_ad_out[PCI_BUS_DATA_RANGE:0]),
|
378 |
|
|
.master_ad_oe (master_ad_oe),
|
379 |
|
|
.master_cbe_l_out (master_cbe_l_out[PCI_BUS_CBE_RANGE:0]),
|
380 |
|
|
.master_cbe_oe (master_cbe_oe),
|
381 |
|
|
.par_now (par_now),
|
382 |
|
|
.par_prev (par_prev),
|
383 |
|
|
.frame_now (frame_now),
|
384 |
|
|
.frame_prev (frame_prev),
|
385 |
|
|
.master_frame_out (master_frame_out),
|
386 |
|
|
.master_frame_oe (master_frame_oe),
|
387 |
|
|
.irdy_now (irdy_now),
|
388 |
|
|
.irdy_prev (irdy_prev),
|
389 |
|
|
.master_irdy_out (master_irdy_out),
|
390 |
|
|
.master_irdy_oe (master_irdy_oe),
|
391 |
|
|
.devsel_now (devsel_now),
|
392 |
|
|
.devsel_prev (devsel_prev),
|
393 |
|
|
.trdy_now (trdy_now),
|
394 |
|
|
.trdy_prev (trdy_prev),
|
395 |
|
|
.stop_now (stop_now),
|
396 |
|
|
.stop_prev (stop_prev),
|
397 |
|
|
.perr_now (perr_now),
|
398 |
|
|
.perr_prev (perr_prev),
|
399 |
|
|
.master_perr_out (master_perr_out),
|
400 |
|
|
.master_perr_oe (master_perr_oe),
|
401 |
|
|
.master_serr_oe (master_serr_oe),
|
402 |
|
|
.master_req_out (master_req),
|
403 |
|
|
.master_gnt_now (master_gnt_now),
|
404 |
|
|
.pci_reset_comb (pci_reset_comb),
|
405 |
|
|
.pci_ext_clk (pci_ext_clk),
|
406 |
|
|
// Signals from the master to the target to set bits in the Status Register
|
407 |
|
|
.master_got_parity_error (master_got_parity_error),
|
408 |
|
|
.master_asserted_serr (master_asserted_serr),
|
409 |
|
|
.master_got_master_abort (master_got_master_abort),
|
410 |
|
|
.master_got_target_abort (master_got_target_abort),
|
411 |
|
|
.master_caused_parity_error (master_caused_parity_error),
|
412 |
|
|
.master_enable (master_enable),
|
413 |
|
|
.master_fast_b2b_en (master_fast_b2b_en),
|
414 |
|
|
.master_perr_enable (master_perr_enable),
|
415 |
|
|
.master_serr_enable (master_serr_enable),
|
416 |
|
|
.master_latency_value (master_latency_value[7:0]),
|
417 |
|
|
// Signals used by the test bench instead of using "." notation
|
418 |
|
|
.master_debug_force_bad_par (master_debug_force_bad_par),
|
419 |
|
|
.test_master_number (test_master_number[2:0]),
|
420 |
|
|
.test_address (test_address[PCI_BUS_DATA_RANGE:0]),
|
421 |
|
|
.test_command (test_command[PCI_BUS_CBE_RANGE:0]),
|
422 |
|
|
.test_data (test_data[PCI_BUS_DATA_RANGE:0]),
|
423 |
|
|
.test_byte_enables_l (test_byte_enables_l[PCI_BUS_CBE_RANGE:0]),
|
424 |
|
|
.test_size (test_size),
|
425 |
|
|
.test_make_addr_par_error (test_make_addr_par_error),
|
426 |
|
|
.test_make_data_par_error (test_make_data_par_error),
|
427 |
|
|
.test_master_initial_wait_states (test_master_initial_wait_states[3:0]),
|
428 |
|
|
.test_master_subsequent_wait_states (test_master_subsequent_wait_states[3:0]),
|
429 |
|
|
.test_target_initial_wait_states (test_target_initial_wait_states[3:0]),
|
430 |
|
|
.test_target_subsequent_wait_states (test_target_subsequent_wait_states[3:0]),
|
431 |
|
|
.test_target_devsel_speed (test_target_devsel_speed[1:0]),
|
432 |
|
|
.test_fast_back_to_back (test_fast_back_to_back),
|
433 |
|
|
.test_target_termination (test_target_termination[2:0]),
|
434 |
|
|
.test_expect_master_abort (test_expect_master_abort),
|
435 |
|
|
.test_start (test_start),
|
436 |
|
|
.test_accepted_l (test_accepted_l),
|
437 |
|
|
.test_error_event (master_error_event),
|
438 |
|
|
.test_device_id (test_device_id[2:0]),
|
439 |
|
|
// target read data and data valid signals for testbench
|
440 |
|
|
.master_received_data (master_received_data),
|
441 |
|
|
.master_received_data_valid (master_received_data_valid),
|
442 |
|
|
.master_check_received_data (master_check_received_data)
|
443 |
|
|
);
|
444 |
|
|
|
445 |
|
|
pci_behaviorial_target pci_behaviorial_target (
|
446 |
|
|
.ad_now (ad_now[PCI_BUS_DATA_RANGE:0]),
|
447 |
|
|
.ad_prev (ad_prev[PCI_BUS_DATA_RANGE:0]),
|
448 |
|
|
.calc_input_parity_prev (calc_input_parity_prev),
|
449 |
|
|
.target_ad_out (target_ad_out[PCI_BUS_DATA_RANGE:0]),
|
450 |
|
|
.target_ad_oe (target_ad_oe),
|
451 |
|
|
.cbe_l_now (cbe_l_now[PCI_BUS_CBE_RANGE:0]),
|
452 |
|
|
.cbe_l_prev (cbe_l_prev[PCI_BUS_CBE_RANGE:0]),
|
453 |
|
|
.par_now (par_now),
|
454 |
|
|
.par_prev (par_prev),
|
455 |
|
|
.frame_now (frame_now),
|
456 |
|
|
.frame_prev (frame_prev),
|
457 |
|
|
.irdy_now (irdy_now),
|
458 |
|
|
.irdy_prev (irdy_prev),
|
459 |
|
|
.target_devsel_out (target_devsel_out),
|
460 |
|
|
.target_d_t_s_oe (target_d_t_s_oe),
|
461 |
|
|
.target_trdy_out (target_trdy_out),
|
462 |
|
|
.target_stop_out (target_stop_out),
|
463 |
|
|
.target_perr_out (target_perr_out),
|
464 |
|
|
.target_perr_oe (target_perr_oe),
|
465 |
|
|
.target_serr_oe (target_serr_oe),
|
466 |
|
|
.idsel_now (idsel_now),
|
467 |
|
|
.idsel_prev (idsel_prev),
|
468 |
|
|
.pci_reset_comb (pci_reset_comb),
|
469 |
|
|
.pci_ext_clk (pci_ext_clk),
|
470 |
|
|
// Signals from the master to the target to set bits in the Status Register
|
471 |
|
|
.master_got_parity_error (master_got_parity_error),
|
472 |
|
|
.master_asserted_serr (master_asserted_serr),
|
473 |
|
|
.master_got_master_abort (master_got_master_abort),
|
474 |
|
|
.master_got_target_abort (master_got_target_abort),
|
475 |
|
|
.master_caused_parity_error (master_caused_parity_error),
|
476 |
|
|
.master_enable (master_enable),
|
477 |
|
|
.master_fast_b2b_en (master_fast_b2b_en),
|
478 |
|
|
.master_perr_enable (master_perr_enable),
|
479 |
|
|
.master_serr_enable (master_serr_enable),
|
480 |
|
|
.master_latency_value (master_latency_value[7:0]),
|
481 |
|
|
// Signals used by the test bench instead of using "." notation
|
482 |
|
|
.target_debug_force_bad_par (target_debug_force_bad_par),
|
483 |
|
|
.test_error_event (target_error_event),
|
484 |
|
|
.test_device_id (test_device_id[2:0]),
|
485 |
|
|
.test_response (test_target_response)
|
486 |
|
|
);
|
487 |
|
|
endmodule
|
488 |
|
|
|
489 |
|
|
module delayed_test_pad (
|
490 |
|
|
external_sig, data_out_comb, data_oe_comb, data_in_comb, data_in_prev,
|
491 |
|
|
pci_ext_clk
|
492 |
|
|
);
|
493 |
|
|
inout external_sig;
|
494 |
|
|
input data_out_comb, data_oe_comb;
|
495 |
|
|
output data_in_comb, data_in_prev;
|
496 |
|
|
input pci_ext_clk;
|
497 |
|
|
|
498 |
|
|
wire data_out_dly1, data_out_dly2;
|
499 |
|
|
assign #`PAD_MIN_DATA_DLY data_out_dly1 = data_out_comb;
|
500 |
|
|
assign #`PAD_MAX_DATA_DLY data_out_dly2 = data_out_comb;
|
501 |
|
|
|
502 |
|
|
wire data_oe_dly1, data_oe_dly2;
|
503 |
|
|
assign #`PAD_MIN_OE_DLY data_oe_dly1 = data_oe_comb;
|
504 |
|
|
assign #`PAD_MAX_OE_DLY data_oe_dly2 = data_oe_comb;
|
505 |
|
|
|
506 |
|
|
wire force_data_x = (data_oe_dly1 !== data_oe_dly2)
|
507 |
|
|
| (data_oe_comb & (data_out_dly1 !== data_out_dly2));
|
508 |
|
|
assign external_sig = force_data_x ? 1'bX
|
509 |
|
|
: (data_oe_dly2 ? data_out_dly2 : 1'bZ);
|
510 |
|
|
assign data_in_comb = ~external_sig;
|
511 |
|
|
|
512 |
|
|
reg pci_ad_out_oe_hold, pci_ad_out_hold, pci_ad_in_hold, data_in_prev;
|
513 |
|
|
always @(posedge pci_ext_clk)
|
514 |
|
|
begin
|
515 |
|
|
data_in_prev <= ~external_sig;
|
516 |
|
|
pci_ad_out_oe_hold <= data_oe_comb;
|
517 |
|
|
pci_ad_out_hold <= data_out_comb;
|
518 |
|
|
pci_ad_in_hold <= external_sig;
|
519 |
|
|
if (pci_ad_out_oe_hold & (pci_ad_out_hold !== pci_ad_in_hold))
|
520 |
|
|
begin
|
521 |
|
|
$display ("*** Test Device Pad drives one value while receiving another %h, %h, %h, at %t",
|
522 |
|
|
pci_ad_out_oe_hold, pci_ad_out_hold, pci_ad_in_hold, $time);
|
523 |
|
|
end
|
524 |
|
|
`NO_ELSE;
|
525 |
|
|
end
|
526 |
|
|
endmodule
|
527 |
|
|
|