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[/] [pci/] [tags/] [rel_1/] [bench/] [verilog/] [pci_unsupported_commands_master.v] - Blame information for rev 154

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`include "bus_commands.v"
module pci_unsupported_commands_master
(
    CLK,
    AD,
    CBE,
    RST,
    REQ,
    GNT,
    FRAME,
    IRDY,
    DEVSEL,
    TRDY,
    STOP,
    PAR
);
 
input CLK ;
output [31:0] AD ;
output [3:0]  CBE ;
input  RST ;
output REQ ;
input  GNT ;
output FRAME ;
output IRDY ;
input  DEVSEL ;
input  TRDY ;
input  STOP ;
output PAR ;
 
reg [31:0]  AD ;
reg [3:0]   CBE ;
reg         REQ ;
reg         FRAME ;
reg         IRDY ;
reg         PAR ;
 
initial
begin
    REQ   = 1'b1 ;
    AD    = 32'hzzzz_zzzz ;
    CBE   = 4'bzzzz ;
    FRAME = 1'bz ;
    IRDY  = 1'bz ;
    PAR   = 1'bz ;
end
 
task master_reference ;
    input [31:0] addr1 ;
    input [31:0] addr2 ;
    input [3:0]  bc1 ;
    input [3:0]  bc2 ;
    input [3:0]  be ;
    input [31:0] data ;
    input        make_addr_perr1 ;
    input        make_addr_perr2 ;
    output       ok ;
    integer      i ;
    reg          dual_address ;
begin
    ok = 1 ;
    dual_address = (bc1 == `BC_DUAL_ADDR_CYC) ;
    @(posedge CLK) ;
    while( GNT == 1 )
    begin
        REQ <= #1 1'b0 ;
        @(posedge CLK) ;
    end
 
    REQ   <= #1 1'b1 ;
    FRAME <= #1 1'b0 ;
    AD    <= #1 addr1 ;
    CBE   <= #1 bc1 ;
 
    // end of first address cycle
    @(posedge CLK) ;
    PAR <= #1 ^{AD, CBE, make_addr_perr1} ;
    if ( dual_address )
    begin
        IRDY <= #1 1'b1 ;
        AD   <= #1 addr2 ;
        CBE  <= #1 bc2 ;
    end
    else
    begin
        IRDY  <= #1 1'b0 ;
        FRAME <= #1 1'b1 ;
        CBE   <= #1 be ;
        if ( bc1[0] )
            AD <= #1 data ;
        else
            AD <= #1 32'hzzzz_zzzz ;
    end
 
    @(posedge CLK) ;
    CBE <= #1 be ;
    if ( dual_address )
    begin
        PAR   <= #1 ^{AD, CBE, make_addr_perr2} ;
        IRDY  <= #1 1'b0 ;
        FRAME <= #1 1'b1 ;
        if ( bc2[0] )
            AD <= #1 data ;
        else
            AD <= #1 32'hzzzz_zzzz ;
    end
    else
    begin
        if ( bc1[0] )
            PAR <= #1 ^{AD, CBE} ;
        else
            PAR <= #1 1'bz ;
    end
 
    @(posedge CLK) ;
    if ( AD[31] !== 1'bz )
        PAR <= #1 ^{AD, CBE} ;
    else
        PAR <= #1 1'bz ;
 
    i = 0 ; // Checking for Master Abort
    while ( (DEVSEL === 1) && (STOP === 1) && (i < 6) )
    begin
        @(posedge CLK) ;
        i = i + 1 ;
    end
 
    if ( (DEVSEL !== 1) || (STOP !== 1) )
    begin
        ok = 0 ; // If NO Master abort, then NOT OK!
    end
 
    FRAME <= #1 1'bz ;
    IRDY  <= #1 1'b1 ;
    AD    <= #1 32'hzzzz_zzzz ;
    CBE   <= #1 4'hz ;
 
    @(posedge CLK) ;
    IRDY <= #1 1'bz ;
    PAR  <= #1 1'bz ;
end
endtask // master_reference
endmodule
 

Line No.	Rev	Author	Line
1	15	mihad	`include "bus_commands.v"
2			`module pci_unsupported_commands_master`
3			`(`
4			`CLK,`
5			`AD,`
6			`CBE,`
7			`RST,`
8			`REQ,`
9			`GNT,`
10			`FRAME,`
11			`IRDY,`
12			`DEVSEL,`
13			`TRDY,`
14			`STOP,`
15			`PAR`
16			`);`
17
18			`input CLK ;`
19			`output [31:0] AD ;`
20			`output [3:0] CBE ;`
21			`input RST ;`
22			`output REQ ;`
23			`input GNT ;`
24			`output FRAME ;`
25			`output IRDY ;`
26			`input DEVSEL ;`
27			`input TRDY ;`
28			`input STOP ;`
29			`output PAR ;`
30
31			`reg [31:0] AD ;`
32			`reg [3:0] CBE ;`
33			`reg REQ ;`
34			`reg FRAME ;`
35			`reg IRDY ;`
36			`reg PAR ;`
37
38			`initial`
39			`begin`
40			`REQ = 1'b1 ;`
41			`AD = 32'hzzzz_zzzz ;`
42			`CBE = 4'bzzzz ;`
43			`FRAME = 1'bz ;`
44			`IRDY = 1'bz ;`
45			`PAR = 1'bz ;`
46			`end`
47
48			`task master_reference ;`
49			`input [31:0] addr1 ;`
50			`input [31:0] addr2 ;`
51			`input [3:0] bc1 ;`
52			`input [3:0] bc2 ;`
53			`input [3:0] be ;`
54			`input [31:0] data ;`
55			`input make_addr_perr1 ;`
56			`input make_addr_perr2 ;`
57			`output ok ;`
58			`integer i ;`
59			`reg dual_address ;`
60			`begin`
61			`ok = 1 ;`
62			dual_address = (bc1 == `BC_DUAL_ADDR_CYC) ;
63			`@(posedge CLK) ;`
64			`while( GNT == 1 )`
65			`begin`
66			`REQ <= #1 1'b0 ;`
67			`@(posedge CLK) ;`
68			`end`
69
70			`REQ <= #1 1'b1 ;`
71			`FRAME <= #1 1'b0 ;`
72			`AD <= #1 addr1 ;`
73			`CBE <= #1 bc1 ;`
74
75			`// end of first address cycle`
76			`@(posedge CLK) ;`
77			`PAR <= #1 ^{AD, CBE, make_addr_perr1} ;`
78			`if ( dual_address )`
79			`begin`
80			`IRDY <= #1 1'b1 ;`
81			`AD <= #1 addr2 ;`
82			`CBE <= #1 bc2 ;`
83			`end`
84			`else`
85			`begin`
86			`IRDY <= #1 1'b0 ;`
87			`FRAME <= #1 1'b1 ;`
88			`CBE <= #1 be ;`
89			`if ( bc1[0] )`
90			`AD <= #1 data ;`
91			`else`
92			`AD <= #1 32'hzzzz_zzzz ;`
93			`end`
94
95			`@(posedge CLK) ;`
96			`CBE <= #1 be ;`
97			`if ( dual_address )`
98			`begin`
99			`PAR <= #1 ^{AD, CBE, make_addr_perr2} ;`
100			`IRDY <= #1 1'b0 ;`
101			`FRAME <= #1 1'b1 ;`
102			`if ( bc2[0] )`
103			`AD <= #1 data ;`
104			`else`
105			`AD <= #1 32'hzzzz_zzzz ;`
106			`end`
107			`else`
108			`begin`
109			`if ( bc1[0] )`
110			`PAR <= #1 ^{AD, CBE} ;`
111			`else`
112			`PAR <= #1 1'bz ;`
113			`end`
114
115			`@(posedge CLK) ;`
116			`if ( AD[31] !== 1'bz )`
117			`PAR <= #1 ^{AD, CBE} ;`
118			`else`
119			`PAR <= #1 1'bz ;`
120
121			`i = 0 ; // Checking for Master Abort`
122			`while ( (DEVSEL === 1) && (STOP === 1) && (i < 6) )`
123			`begin`
124			`@(posedge CLK) ;`
125			`i = i + 1 ;`
126			`end`
127
128			`if ( (DEVSEL !== 1) \|\| (STOP !== 1) )`
129			`begin`
130			`ok = 0 ; // If NO Master abort, then NOT OK!`
131			`end`
132
133			`FRAME <= #1 1'bz ;`
134			`IRDY <= #1 1'b1 ;`
135			`AD <= #1 32'hzzzz_zzzz ;`
136			`CBE <= #1 4'hz ;`
137
138			`@(posedge CLK) ;`
139			`IRDY <= #1 1'bz ;`
140			`PAR <= #1 1'bz ;`
141			`end`
142			`endtask // master_reference`
143			`endmodule`
144

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[/] [pci/] [tags/] [rel_1/] [bench/] [verilog/] [pci_unsupported_commands_master.v] - Blame information for rev 154