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//////////////////////////////////////////////////////////////////////
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//// ////
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//// File name: conf_space.v ////
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//// ////
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//// This file is part of the "PCI bridge" project ////
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//// http://www.opencores.org/cores/pci/ ////
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//// ////
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//// Author(s): ////
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//// - tadej@opencores.org ////
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//// - Tadej Markovic ////
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//// ////
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//// All additional information is avaliable in the README.txt ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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mihad |
// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
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// New project directory structure
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mihad |
//
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mihad |
//
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mihad |
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`include "constants.v"
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mihad |
`include "timescale.v"
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mihad |
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/*-----------------------------------------------------------------------------------------------------------
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w_ prefix is a sign for Write (and read) side of Dual-Port registers
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r_ prefix is a sign for Read only side of Dual-Port registers
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In the first line there are DATA and ADDRESS ports, in the second line there are write enable and read
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enable signals with chip-select (conf_hit) for config. space.
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In the third line there are output signlas from Command register of the PCI configuration header !!!
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In the fourth line there are input signals to Status register of the PCI configuration header !!!
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In the fifth line there is output from Latency Timer & r_Interrupt pin registers of the PCI conf. header !!!
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Following are IMAGE specific registers, from which PCI_BASE_ADDR registers are the same as base address
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registers from the PCI conf. header !!!
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-----------------------------------------------------------------------------------------------------------*/
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// normal R/W address, data and control
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module CONF_SPACE ( w_conf_address_in, w_conf_data_in, w_conf_data_out, r_conf_address_in, r_conf_data_out,
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w_we, w_re, r_re, w_byte_en, w_clock, reset, pci_clk, wb_clk,
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// outputs from command register of the PCI header
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serr_enable, perr_response, pci_master_enable, memory_space_enable, io_space_enable,
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// inputs to status register of the PCI header
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perr_in, serr_in, master_abort_recv, target_abort_recv, target_abort_set, master_data_par_err,
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// output from cache_line_size, latency timer and r_interrupt_pin register of the PCI header
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cache_line_size, latency_tim, int_pin,
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// output from all pci IMAGE registers
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pci_base_addr0, pci_base_addr1, pci_base_addr2, pci_base_addr3, pci_base_addr4, pci_base_addr5,
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pci_memory_io0, pci_memory_io1, pci_memory_io2, pci_memory_io3, pci_memory_io4, pci_memory_io5,
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pci_addr_mask0, pci_addr_mask1, pci_addr_mask2, pci_addr_mask3, pci_addr_mask4, pci_addr_mask5,
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pci_tran_addr0, pci_tran_addr1, pci_tran_addr2, pci_tran_addr3, pci_tran_addr4, pci_tran_addr5,
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pci_img_ctrl0, pci_img_ctrl1, pci_img_ctrl2, pci_img_ctrl3, pci_img_ctrl4, pci_img_ctrl5,
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// input to pci error control and status register, error address and error data registers
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pci_error_be, pci_error_bc, pci_error_rty_exp, pci_error_sig, pci_error_addr, pci_error_data,
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// output from pci error control and status register
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pci_error_en, pci_error_sig_set, pci_error_rty_exp_set,
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// output from all wishbone IMAGE registers
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wb_base_addr0, wb_base_addr1, wb_base_addr2, wb_base_addr3, wb_base_addr4, wb_base_addr5,
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wb_memory_io0, wb_memory_io1, wb_memory_io2, wb_memory_io3, wb_memory_io4, wb_memory_io5,
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wb_addr_mask0, wb_addr_mask1, wb_addr_mask2, wb_addr_mask3, wb_addr_mask4, wb_addr_mask5,
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wb_tran_addr0, wb_tran_addr1, wb_tran_addr2, wb_tran_addr3, wb_tran_addr4, wb_tran_addr5,
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wb_img_ctrl0, wb_img_ctrl1, wb_img_ctrl2, wb_img_ctrl3, wb_img_ctrl4, wb_img_ctrl5,
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// input to wb error control and status register, error address and error data registers
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wb_error_be, wb_error_bc, wb_error_rty_exp, wb_error_es, wb_error_sig, wb_error_addr, wb_error_data,
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// output from wb error control and status register
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wb_error_en, wb_error_sig_set, wb_error_rty_exp_set,
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// output from conf. cycle generation register (sddress) & int. control register
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config_addr, icr_soft_res, serr_int_en, perr_int_en, error_int_en, int_prop_en,
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// input to interrupt status register
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isr_int_prop, isr_err_int, isr_par_err_int, isr_sys_err_int ) ;
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/*###########################################################################################################
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/////////////////////////////////////////////////////////////////////////////////////////////////////////////
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Input and output ports
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======================
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/////////////////////////////////////////////////////////////////////////////////////////////////////////////
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###########################################################################################################*/
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// output data
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output [31 : 0] w_conf_data_out ;
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output [31 : 0] r_conf_data_out ;
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reg [31 : 0] w_conf_data_out ;
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reg [31 : 0] r_conf_data_out ;
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// input data
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input [31 : 0] w_conf_data_in ;
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// input address
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input [11 : 0] w_conf_address_in ;
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input [11 : 0] r_conf_address_in ;
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// input control signals
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input w_we ;
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input w_re ;
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input r_re ;
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input [3 : 0] w_byte_en ;
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input w_clock ;
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input reset ;
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input pci_clk ;
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input wb_clk ;
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// PCI header outputs from command register
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output serr_enable ;
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output perr_response ;
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output pci_master_enable ;
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output memory_space_enable ;
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output io_space_enable ;
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// PCI header inputs to status register
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input perr_in ;
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input serr_in ;
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input master_abort_recv ;
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input target_abort_recv ;
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input target_abort_set ;
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input master_data_par_err ;
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// PCI header output from cache_line_size, latency timer and interrupt pin
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output [7 : 0] cache_line_size ;
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output [7 : 0] latency_tim ;
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output [2 : 0] int_pin ; // only 3 LSbits are important!
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// PCI output from image registers
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output [31 : 12] pci_base_addr0 ;
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output [31 : 12] pci_base_addr1 ;
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output [31 : 12] pci_base_addr2 ;
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output [31 : 12] pci_base_addr3 ;
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output [31 : 12] pci_base_addr4 ;
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output [31 : 12] pci_base_addr5 ;
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output pci_memory_io0 ;
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output pci_memory_io1 ;
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output pci_memory_io2 ;
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output pci_memory_io3 ;
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output pci_memory_io4 ;
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output pci_memory_io5 ;
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output [31 : 12] pci_addr_mask0 ;
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output [31 : 12] pci_addr_mask1 ;
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output [31 : 12] pci_addr_mask2 ;
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output [31 : 12] pci_addr_mask3 ;
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output [31 : 12] pci_addr_mask4 ;
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output [31 : 12] pci_addr_mask5 ;
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output [31 : 12] pci_tran_addr0 ;
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output [31 : 12] pci_tran_addr1 ;
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output [31 : 12] pci_tran_addr2 ;
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output [31 : 12] pci_tran_addr3 ;
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output [31 : 12] pci_tran_addr4 ;
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output [31 : 12] pci_tran_addr5 ;
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output [2 : 1] pci_img_ctrl0 ;
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output [2 : 1] pci_img_ctrl1 ;
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output [2 : 1] pci_img_ctrl2 ;
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output [2 : 1] pci_img_ctrl3 ;
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output [2 : 1] pci_img_ctrl4 ;
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output [2 : 1] pci_img_ctrl5 ;
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// PCI input to pci error control and status register, error address and error data registers
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input [3 : 0] pci_error_be ;
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input [3 : 0] pci_error_bc ;
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input pci_error_rty_exp ;
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input pci_error_sig ;
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input [31 : 0] pci_error_addr ;
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input [31 : 0] pci_error_data ;
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// PCI output from pci error control and status register
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output pci_error_en ;
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output pci_error_sig_set ;
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output pci_error_rty_exp_set ;
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// WISHBONE output from image registers
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output [31 : 12] wb_base_addr0 ;
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output [31 : 12] wb_base_addr1 ;
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output [31 : 12] wb_base_addr2 ;
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output [31 : 12] wb_base_addr3 ;
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output [31 : 12] wb_base_addr4 ;
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output [31 : 12] wb_base_addr5 ;
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output wb_memory_io0 ;
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output wb_memory_io1 ;
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output wb_memory_io2 ;
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output wb_memory_io3 ;
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output wb_memory_io4 ;
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output wb_memory_io5 ;
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output [31 : 12] wb_addr_mask0 ;
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output [31 : 12] wb_addr_mask1 ;
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output [31 : 12] wb_addr_mask2 ;
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output [31 : 12] wb_addr_mask3 ;
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output [31 : 12] wb_addr_mask4 ;
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output [31 : 12] wb_addr_mask5 ;
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output [31 : 12] wb_tran_addr0 ;
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output [31 : 12] wb_tran_addr1 ;
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output [31 : 12] wb_tran_addr2 ;
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output [31 : 12] wb_tran_addr3 ;
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output [31 : 12] wb_tran_addr4 ;
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output [31 : 12] wb_tran_addr5 ;
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output [2 : 0] wb_img_ctrl0 ;
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output [2 : 0] wb_img_ctrl1 ;
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output [2 : 0] wb_img_ctrl2 ;
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output [2 : 0] wb_img_ctrl3 ;
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output [2 : 0] wb_img_ctrl4 ;
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output [2 : 0] wb_img_ctrl5 ;
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// WISHBONE input to wb error control and status register, error address and error data registers
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input [3 : 0] wb_error_be ;
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input [3 : 0] wb_error_bc ;
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input wb_error_rty_exp ;
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input wb_error_es ;
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input wb_error_sig ;
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input [31 : 0] wb_error_addr ;
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input [31 : 0] wb_error_data ;
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// WISHBONE output from wb error control and status register
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output wb_error_en ;
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output wb_error_sig_set ;
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output wb_error_rty_exp_set ;
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// GENERAL output from conf. cycle generation register & int. control register
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output [23 : 0] config_addr ;
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output icr_soft_res ;
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output serr_int_en ;
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output perr_int_en ;
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output error_int_en ;
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output int_prop_en ;
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// GENERAL input to interrupt status register
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input isr_int_prop ;
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input isr_err_int ;
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input isr_par_err_int ;
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input isr_sys_err_int ;
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/*###########################################################################################################
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/////////////////////////////////////////////////////////////////////////////////////////////////////////////
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REGISTERS definition
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====================
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/////////////////////////////////////////////////////////////////////////////////////////////////////////////
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247 |
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###########################################################################################################*/
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/*###########################################################################################################
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-------------------------------------------------------------------------------------------------------------
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PCI CONFIGURATION SPACE HEADER (type 00h) registers
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BIST and some other registers are not implemented and therefor written in correct
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place with comment line. There are also some registers with NOT all bits implemented and therefor uses
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_bitX or _bitX2_X1 to sign which bit or range of bits are implemented.
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Some special cases and examples are described below!
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258 |
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-------------------------------------------------------------------------------------------------------------
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259 |
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###########################################################################################################*/
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/*-----------------------------------------------------------------------------------------------------------
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[000h-00Ch] First 4 DWORDs (32-bit) of PCI configuration header - the same regardless of the HEADER type !
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r_ prefix is a sign for read only registers
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Vendor_ID is an ID for a specific vendor defined by PCI_SIG - 2321h does not belong to anyone (e.g.
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Xilinx's Vendor_ID is 10EEh and Altera's Vendor_ID is 1172h). Device_ID and Revision_ID should be used
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together by application. Class_Code has 3 bytes to define BASE class (06h for PCI Bridge), SUB class
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(00h for HOST type, 80h for Other Bridge type) and Interface type (00h for normal).
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-----------------------------------------------------------------------------------------------------------*/
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parameter r_vendor_id = `HEADER_VENDOR_ID ; // 16'h2321 = 16'd8993 !!!
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270 |
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parameter r_device_id = `HEADER_DEVICE_ID ;
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271 |
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reg command_bit8 ;
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reg command_bit6 ;
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reg [2 : 0] command_bit2_0 ;
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reg [15 : 11] status_bit15_11 ;
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275 |
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parameter r_status_bit10_9 = 2'b01 ; // 2'b01 means MEDIUM devsel timing !!!
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reg status_bit8 ;
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parameter r_status_bit5 = `HEADER_66MHz ; // 1'b0 indicates 33 MHz capable !!!
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parameter r_revision_id = `HEADER_REVISION_ID ;
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`ifdef HOST
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parameter r_class_code = 24'h06_00_00 ;
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`else
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parameter r_class_code = 24'h06_80_00 ;
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`endif
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284 |
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reg [7 : 0] cache_line_size_reg ;
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reg [7 : 0] latency_timer ;
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parameter r_header_type = 8'h00 ;
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// REG bist NOT implemented !!!
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/*-----------------------------------------------------------------------------------------------------------
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[010h-03Ch] all other DWORDs (32-bit) of PCI configuration header - only for HEADER type 00h !
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r_ prefix is a sign for read only registers
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BASE_ADDRESS_REGISTERS are the same as ones in the PCI Target configuration registers section. They
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are duplicated and therefor defined just ones and used with the same name as written below. If
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IMAGEx is NOT defined there is only parameter image_X assigned to '0' and this parameter is used
|
295 |
|
|
elsewhere in the code. This parameter is defined in the INTERNAL SIGNALS part !!!
|
296 |
|
|
Interrupt_Pin value 8'h01 is used for INT_A pin used.
|
297 |
|
|
MIN_GNT and MAX_LAT are used for device's desired values for Latency Timer value. The value in boath
|
298 |
|
|
registers specifies a period of time in units of 1/4 microsecond. ZERO indicates that there are no
|
299 |
|
|
major requirements for the settings of Latency Timer.
|
300 |
|
|
MIN_GNT specifieshow how long a burst period the device needs at 33MHz. MAX_LAT specifies how often
|
301 |
|
|
the device needs to gain access to the PCI bus. Values are choosen assuming that the target does not
|
302 |
|
|
insert any wait states. Follow the expamle of settings for simple display card.
|
303 |
|
|
If we use 64 (32-bit) FIFO locations for one burst then we need 8 x 1/4 microsecond periods at 33MHz
|
304 |
|
|
clock rate => MIN_GNT = 08h ! Resolution is 1024 x 768 (= 786432 pixels for one frame) with 16-bit
|
305 |
|
|
color mode. We can transfere 2 16-bit pixels in one FIFO location. From that we calculate, that for
|
306 |
|
|
one frame we need 6144 burst transferes in 1/25 second. So we need one burst every 6,51 microsecond
|
307 |
|
|
and that is 26 x 1/4 microsecond or 1Ah x 1/4 microsecond => MAX_LAT = 1Ah !
|
308 |
|
|
-----------------------------------------------------------------------------------------------------------*/
|
309 |
|
|
// REG x 6 base_address_register_X IMPLEMENTED as pci_ba_X !!!
|
310 |
|
|
// REG r_cardbus_cis_pointer NOT implemented !!!
|
311 |
|
|
// REG r_subsystem_vendor_id NOT implemented !!!
|
312 |
|
|
// REG r_subsystem_id NOT implemented !!!
|
313 |
|
|
// REG r_expansion_rom_base_address NOT implemented !!!
|
314 |
|
|
// REG r_cap_list_pointer NOT implemented !!!
|
315 |
|
|
reg [7 : 0] interrupt_line ;
|
316 |
|
|
parameter r_interrupt_pin = 8'h01 ;
|
317 |
|
|
parameter r_min_gnt = 8'h08 ;
|
318 |
|
|
parameter r_max_lat = 8'h1a ;
|
319 |
|
|
|
320 |
|
|
|
321 |
|
|
/*###########################################################################################################
|
322 |
|
|
-------------------------------------------------------------------------------------------------------------
|
323 |
|
|
PCI Bridge default image SIZE parameters
|
324 |
|
|
This parameters are not part of any register group, but are needed for default image size configuration
|
325 |
|
|
used in PCI Target and WISHBONE Slave configuration registers!
|
326 |
|
|
-------------------------------------------------------------------------------------------------------------
|
327 |
|
|
###########################################################################################################*/
|
328 |
|
|
|
329 |
|
|
/*-----------------------------------------------------------------------------------------------------------
|
330 |
|
|
PCI Target default image size parameters are defined with masked bits for address mask registers of
|
331 |
|
|
each image space. By default there are 1MByte of address space defined for def_pci_imageX_addr_map
|
332 |
|
|
parameters!
|
333 |
|
|
-----------------------------------------------------------------------------------------------------------*/
|
334 |
|
|
parameter def_pci_image0_addr_map = `PCI_AM0 ; //20'hfff0_0
|
335 |
|
|
parameter def_pci_image1_addr_map = `PCI_AM1 ; //20'hfff0_0
|
336 |
|
|
parameter def_pci_image2_addr_map = `PCI_AM2 ; //20'h0000_0
|
337 |
|
|
parameter def_pci_image3_addr_map = `PCI_AM3 ; //20'h0000_0
|
338 |
|
|
parameter def_pci_image4_addr_map = `PCI_AM4 ; //20'h0000_0
|
339 |
|
|
parameter def_pci_image5_addr_map = `PCI_AM5 ; //20'h0000_0
|
340 |
|
|
|
341 |
|
|
/*-----------------------------------------------------------------------------------------------------------
|
342 |
|
|
WISHBONE Slave default image size parameters are defined with masked bits for address mask registers
|
343 |
|
|
of each image space. By default there are 1MByte of address space defined for def_wb_imageX_addr_map
|
344 |
|
|
parameters except for def_wb_image0_addr_map which is used for configuration space!
|
345 |
|
|
-----------------------------------------------------------------------------------------------------------*/
|
346 |
|
|
// PARAMETER def_wb_image0_addr_map IMPLEMENTED as r_wb_am0 parameter for CONF. space !!!
|
347 |
|
|
parameter def_wb_image1_addr_map = 20'h0000_0 ;
|
348 |
|
|
parameter def_wb_image2_addr_map = 20'h0000_0 ;
|
349 |
|
|
parameter def_wb_image3_addr_map = 20'h0000_0 ;
|
350 |
|
|
parameter def_wb_image4_addr_map = 20'h0000_0 ;
|
351 |
|
|
parameter def_wb_image5_addr_map = 20'h0000_0 ;
|
352 |
|
|
|
353 |
|
|
|
354 |
|
|
/*###########################################################################################################
|
355 |
|
|
-------------------------------------------------------------------------------------------------------------
|
356 |
|
|
PCI Target configuration registers
|
357 |
|
|
There are also some registers with NOT all bits implemented and therefor uses _bitX or _bitX2_X1 to
|
358 |
|
|
sign which bit or range of bits are implemented. Some special cases and examples are described below!
|
359 |
|
|
-------------------------------------------------------------------------------------------------------------
|
360 |
|
|
###########################################################################################################*/
|
361 |
|
|
|
362 |
|
|
/*-----------------------------------------------------------------------------------------------------------
|
363 |
|
|
[100h-168h]
|
364 |
|
|
Depending on defines (PCI_IMAGE1 or .. or PCI_IMAGE5 or (PCI_IMAGE6 and HOST)) in constants.v file,
|
365 |
|
|
there are registers corresponding to each IMAGE defined to REG and parameter pci_image_X assigned to '1'.
|
366 |
|
|
The maximum number of images is "6". By default there are first two images used and the first (PCI_IMAGE0)
|
367 |
|
|
is assigned to Configuration space! With a 'define' PCI_IMAGEx you choose the number of used PCI IMAGES
|
368 |
|
|
in a bridge without PCI_IMAGE0 (e.g. PCI_IMAGE3 tells, that PCI_IMAGE1, PCI_IMAGE2 and PCI_IMAGE3 are
|
369 |
|
|
used for mapping the space from WB to PCI. Offcourse, PCI_IMAGE0 is assigned to Configuration space).
|
370 |
|
|
That leave us PCI_IMAGE5 as the maximum number of images.
|
371 |
|
|
There is one exeption, when the core is implemented as HOST. If so, then the PCI specification allowes
|
372 |
|
|
the Configuration space NOT to be visible on the PCI bus. With `define PCI_IMAGE6 (and `define HOST), we
|
373 |
|
|
assign PCI_IMAGE0 to normal WB to PCI image and not to configuration space!
|
374 |
|
|
|
375 |
|
|
When error occurs, PCI ERR_ADDR and ERR_DATA registers stores address and data on the bus that
|
376 |
|
|
caused error. While ERR_CS register stores Byte Enables and Bus Command in the MSByte. In bits 10
|
377 |
|
|
and 8 it reports Retry Counter Expired (for posted writes), Error Source (Master Abort) and Error
|
378 |
|
|
Report Signal (signals that error has occured) respectively. With bit 0 we enable Error Reporting
|
379 |
|
|
mechanism.
|
380 |
|
|
-----------------------------------------------------------------------------------------------------------*/
|
381 |
|
|
parameter pci_image0 = 1 ;
|
382 |
|
|
reg [31 : 12] pci_ba0_bit31_12 ;
|
383 |
|
|
`ifdef HOST
|
384 |
|
|
`ifdef PCI_IMAGE6 // if PCI bridge is HOST and IMAGE0 is assigned as general image space
|
385 |
|
|
parameter pci_image0_conf = 1 ;
|
386 |
|
|
reg [2 : 1] pci_img_ctrl0_bit2_1 ;
|
387 |
|
|
reg pci_ba0_bit0 ;
|
388 |
|
|
reg [31 : 12] pci_am0 ;
|
389 |
|
|
reg [31 : 12] pci_ta0 ;
|
390 |
|
|
`else // if PCI bridge is HOST and IMAGE0 is assigned to PCI configuration space
|
391 |
|
|
parameter pci_image0_conf = 0 ;
|
392 |
|
|
wire [2 : 1] pci_img_ctrl0_bit2_1 = 2'b00 ; // NO pre-fetch and read line support
|
393 |
|
|
wire pci_ba0_bit0 = 0 ; // config. space is MEMORY space
|
394 |
6 |
mihad |
wire [31 : 12] pci_am0 = `PCI_AM0 ; // 4KBytes of configuration space is minimum
|
395 |
2 |
mihad |
wire [31 : 12] pci_ta0 = 20'h0000_0 ; // NO address translation needed
|
396 |
|
|
`endif
|
397 |
|
|
`else // if PCI bridge is GUEST, then IMAGE0 is assigned to PCI configuration space
|
398 |
|
|
parameter pci_image0_conf = 0 ;
|
399 |
|
|
wire [2 : 1] pci_img_ctrl0_bit2_1 = 2'b00 ; // NO addr.transl. and pre-fetch
|
400 |
|
|
wire pci_ba0_bit0 = 0 ; // config. space is MEMORY space
|
401 |
6 |
mihad |
wire [31 : 12] pci_am0 = `PCI_AM0 ; // 4KBytes of configuration space is minimum
|
402 |
2 |
mihad |
wire [31 : 12] pci_ta0 = 20'h0000_0 ; // NO address translation needed
|
403 |
|
|
`endif
|
404 |
|
|
parameter pci_image1 = 1 ;
|
405 |
|
|
reg [2 : 1] pci_img_ctrl1_bit2_1 ;
|
406 |
|
|
reg [31 : 12] pci_ba1_bit31_12 ;
|
407 |
|
|
reg pci_ba1_bit0 ;
|
408 |
|
|
reg [31 : 12] pci_am1 ;
|
409 |
|
|
reg [31 : 12] pci_ta1 ;
|
410 |
|
|
|
411 |
|
|
// IMAGE0 and IMAGE1 are included by default, meanwhile other IMAGEs are optional !!!
|
412 |
|
|
`ifdef PCI_IMAGE1
|
413 |
|
|
parameter pci_image2 = 0 ;
|
414 |
|
|
wire [2 : 1] pci_img_ctrl2_bit2_1 = 2'b00 ;
|
415 |
|
|
wire [31 : 12] pci_ba2_bit31_12 = 20'h0000_0 ;
|
416 |
|
|
wire pci_ba2_bit0 = 1'b0 ;
|
417 |
|
|
wire [31 : 12] pci_am2 = 20'h0000_0 ;
|
418 |
|
|
wire [31 : 12] pci_ta2 = 20'h0000_0 ;
|
419 |
|
|
|
420 |
|
|
parameter pci_image3 = 0 ;
|
421 |
|
|
wire [2 : 1] pci_img_ctrl3_bit2_1 = 2'b00 ;
|
422 |
|
|
wire [31 : 12] pci_ba3_bit31_12 = 20'h0000_0 ;
|
423 |
|
|
wire pci_ba3_bit0 = 1'b0 ;
|
424 |
|
|
wire [31 : 12] pci_am3 = 20'h0000_0 ;
|
425 |
|
|
wire [31 : 12] pci_ta3 = 20'h0000_0 ;
|
426 |
|
|
|
427 |
|
|
parameter pci_image4 = 0 ;
|
428 |
|
|
wire [2 : 1] pci_img_ctrl4_bit2_1 = 2'b00 ;
|
429 |
|
|
wire [31 : 12] pci_ba4_bit31_12 = 20'h0000_0 ;
|
430 |
|
|
wire pci_ba4_bit0 = 1'b0 ;
|
431 |
|
|
wire [31 : 12] pci_am4 = 20'h0000_0 ;
|
432 |
|
|
wire [31 : 12] pci_ta4 = 20'h0000_0 ;
|
433 |
|
|
|
434 |
|
|
parameter pci_image5 = 0 ;
|
435 |
|
|
wire [2 : 1] pci_img_ctrl5_bit2_1 = 2'b00 ;
|
436 |
|
|
wire [31 : 12] pci_ba5_bit31_12 = 20'h0000_0 ;
|
437 |
|
|
wire pci_ba5_bit0 = 1'b0 ;
|
438 |
|
|
wire [31 : 12] pci_am5 = 20'h0000_0 ;
|
439 |
|
|
wire [31 : 12] pci_ta5 = 20'h0000_0 ;
|
440 |
|
|
`endif
|
441 |
|
|
`ifdef PCI_IMAGE2
|
442 |
|
|
parameter pci_image2 = 1 ;
|
443 |
|
|
reg [2 : 1] pci_img_ctrl2_bit2_1 ;
|
444 |
|
|
reg [31 : 12] pci_ba2_bit31_12 ;
|
445 |
|
|
reg pci_ba2_bit0 ;
|
446 |
|
|
reg [31 : 12] pci_am2 ;
|
447 |
|
|
reg [31 : 12] pci_ta2 ;
|
448 |
|
|
|
449 |
|
|
parameter pci_image3 = 0 ;
|
450 |
|
|
wire [2 : 1] pci_img_ctrl3_bit2_1 = 2'b00 ;
|
451 |
|
|
wire [31 : 12] pci_ba3_bit31_12 = 20'h0000_0 ;
|
452 |
|
|
wire pci_ba3_bit0 = 1'b0 ;
|
453 |
|
|
wire [31 : 12] pci_am3 = 20'h0000_0 ;
|
454 |
|
|
wire [31 : 12] pci_ta3 = 20'h0000_0 ;
|
455 |
|
|
|
456 |
|
|
parameter pci_image4 = 0 ;
|
457 |
|
|
wire [2 : 1] pci_img_ctrl4_bit2_1 = 2'b00 ;
|
458 |
|
|
wire [31 : 12] pci_ba4_bit31_12 = 20'h0000_0 ;
|
459 |
|
|
wire pci_ba4_bit0 = 1'b0 ;
|
460 |
|
|
wire [31 : 12] pci_am4 = 20'h0000_0 ;
|
461 |
|
|
wire [31 : 12] pci_ta4 = 20'h0000_0 ;
|
462 |
|
|
|
463 |
|
|
parameter pci_image5 = 0 ;
|
464 |
|
|
wire [2 : 1] pci_img_ctrl5_bit2_1 = 2'b00 ;
|
465 |
|
|
wire [31 : 12] pci_ba5_bit31_12 = 20'h0000_0 ;
|
466 |
|
|
wire pci_ba5_bit0 = 1'b0 ;
|
467 |
|
|
wire [31 : 12] pci_am5 = 20'h0000_0 ;
|
468 |
|
|
wire [31 : 12] pci_ta5 = 20'h0000_0 ;
|
469 |
|
|
`endif
|
470 |
|
|
`ifdef PCI_IMAGE3
|
471 |
|
|
parameter pci_image2 = 1 ;
|
472 |
|
|
reg [2 : 1] pci_img_ctrl2_bit2_1 ;
|
473 |
|
|
reg [31 : 12] pci_ba2_bit31_12 ;
|
474 |
|
|
reg pci_ba2_bit0 ;
|
475 |
|
|
reg [31 : 12] pci_am2 ;
|
476 |
|
|
reg [31 : 12] pci_ta2 ;
|
477 |
|
|
|
478 |
|
|
parameter pci_image3 = 1 ;
|
479 |
|
|
reg [2 : 1] pci_img_ctrl3_bit2_1 ;
|
480 |
|
|
reg [31 : 12] pci_ba3_bit31_12 ;
|
481 |
|
|
reg pci_ba3_bit0 ;
|
482 |
|
|
reg [31 : 12] pci_am3 ;
|
483 |
|
|
reg [31 : 12] pci_ta3 ;
|
484 |
|
|
|
485 |
|
|
parameter pci_image4 = 0 ;
|
486 |
|
|
wire [2 : 1] pci_img_ctrl4_bit2_1 = 2'b00 ;
|
487 |
|
|
wire [31 : 12] pci_ba4_bit31_12 = 20'h0000_0 ;
|
488 |
|
|
wire pci_ba4_bit0 = 1'b0 ;
|
489 |
|
|
wire [31 : 12] pci_am4 = 20'h0000_0 ;
|
490 |
|
|
wire [31 : 12] pci_ta4 = 20'h0000_0 ;
|
491 |
|
|
|
492 |
|
|
parameter pci_image5 = 0 ;
|
493 |
|
|
wire [2 : 1] pci_img_ctrl5_bit2_1 = 2'b00 ;
|
494 |
|
|
wire [31 : 12] pci_ba5_bit31_12 = 20'h0000_0 ;
|
495 |
|
|
wire pci_ba5_bit0 = 1'b0 ;
|
496 |
|
|
wire [31 : 12] pci_am5 = 20'h0000_0 ;
|
497 |
|
|
wire [31 : 12] pci_ta5 = 20'h0000_0 ;
|
498 |
|
|
`endif
|
499 |
|
|
`ifdef PCI_IMAGE4
|
500 |
|
|
parameter pci_image2 = 1 ;
|
501 |
|
|
reg [2 : 1] pci_img_ctrl2_bit2_1 ;
|
502 |
|
|
reg [31 : 12] pci_ba2_bit31_12 ;
|
503 |
|
|
reg pci_ba2_bit0 ;
|
504 |
|
|
reg [31 : 12] pci_am2 ;
|
505 |
|
|
reg [31 : 12] pci_ta2 ;
|
506 |
|
|
|
507 |
|
|
parameter pci_image3 = 1 ;
|
508 |
|
|
reg [2 : 1] pci_img_ctrl3_bit2_1 ;
|
509 |
|
|
reg [31 : 12] pci_ba3_bit31_12 ;
|
510 |
|
|
reg pci_ba3_bit0 ;
|
511 |
|
|
reg [31 : 12] pci_am3 ;
|
512 |
|
|
reg [31 : 12] pci_ta3 ;
|
513 |
|
|
|
514 |
|
|
parameter pci_image4 = 1 ;
|
515 |
|
|
reg [2 : 1] pci_img_ctrl4_bit2_1 ;
|
516 |
|
|
reg [31 : 12] pci_ba4_bit31_12 ;
|
517 |
|
|
reg pci_ba4_bit0 ;
|
518 |
|
|
reg [31 : 12] pci_am4 ;
|
519 |
|
|
reg [31 : 12] pci_ta4 ;
|
520 |
|
|
|
521 |
|
|
parameter pci_image5 = 0 ;
|
522 |
|
|
wire [2 : 1] pci_img_ctrl5_bit2_1 = 2'b00 ;
|
523 |
|
|
wire [31 : 12] pci_ba5_bit31_12 = 20'h0000_0 ;
|
524 |
|
|
wire pci_ba5_bit0 = 1'b0 ;
|
525 |
|
|
wire [31 : 12] pci_am5 = 20'h0000_0 ;
|
526 |
|
|
wire [31 : 12] pci_ta5 = 20'h0000_0 ;
|
527 |
|
|
`endif
|
528 |
|
|
`ifdef PCI_IMAGE5
|
529 |
|
|
parameter pci_image2 = 1 ;
|
530 |
|
|
reg [2 : 1] pci_img_ctrl2_bit2_1 ;
|
531 |
|
|
reg [31 : 12] pci_ba2_bit31_12 ;
|
532 |
|
|
reg pci_ba2_bit0 ;
|
533 |
|
|
reg [31 : 12] pci_am2 ;
|
534 |
|
|
reg [31 : 12] pci_ta2 ;
|
535 |
|
|
|
536 |
|
|
parameter pci_image3 = 1 ;
|
537 |
|
|
reg [2 : 1] pci_img_ctrl3_bit2_1 ;
|
538 |
|
|
reg [31 : 12] pci_ba3_bit31_12 ;
|
539 |
|
|
reg pci_ba3_bit0 ;
|
540 |
|
|
reg [31 : 12] pci_am3 ;
|
541 |
|
|
reg [31 : 12] pci_ta3 ;
|
542 |
|
|
|
543 |
|
|
parameter pci_image4 = 1 ;
|
544 |
|
|
reg [2 : 1] pci_img_ctrl4_bit2_1 ;
|
545 |
|
|
reg [31 : 12] pci_ba4_bit31_12 ;
|
546 |
|
|
reg pci_ba4_bit0 ;
|
547 |
|
|
reg [31 : 12] pci_am4 ;
|
548 |
|
|
reg [31 : 12] pci_ta4 ;
|
549 |
|
|
|
550 |
|
|
parameter pci_image5 = 1 ;
|
551 |
|
|
reg [2 : 1] pci_img_ctrl5_bit2_1 ;
|
552 |
|
|
reg [31 : 12] pci_ba5_bit31_12 ;
|
553 |
|
|
reg pci_ba5_bit0 ;
|
554 |
|
|
reg [31 : 12] pci_am5 ;
|
555 |
|
|
reg [31 : 12] pci_ta5 ;
|
556 |
|
|
`endif
|
557 |
|
|
`ifdef PCI_IMAGE6
|
558 |
|
|
parameter pci_image2 = 1 ;
|
559 |
|
|
reg [2 : 1] pci_img_ctrl2_bit2_1 ;
|
560 |
|
|
reg [31 : 12] pci_ba2_bit31_12 ;
|
561 |
|
|
reg pci_ba2_bit0 ;
|
562 |
|
|
reg [31 : 12] pci_am2 ;
|
563 |
|
|
reg [31 : 12] pci_ta2 ;
|
564 |
|
|
|
565 |
|
|
parameter pci_image3 = 1 ;
|
566 |
|
|
reg [2 : 1] pci_img_ctrl3_bit2_1 ;
|
567 |
|
|
reg [31 : 12] pci_ba3_bit31_12 ;
|
568 |
|
|
reg pci_ba3_bit0 ;
|
569 |
|
|
reg [31 : 12] pci_am3 ;
|
570 |
|
|
reg [31 : 12] pci_ta3 ;
|
571 |
|
|
|
572 |
|
|
parameter pci_image4 = 1 ;
|
573 |
|
|
reg [2 : 1] pci_img_ctrl4_bit2_1 ;
|
574 |
|
|
reg [31 : 12] pci_ba4_bit31_12 ;
|
575 |
|
|
reg pci_ba4_bit0 ;
|
576 |
|
|
reg [31 : 12] pci_am4 ;
|
577 |
|
|
reg [31 : 12] pci_ta4 ;
|
578 |
|
|
|
579 |
|
|
parameter pci_image5 = 1 ;
|
580 |
|
|
reg [2 : 1] pci_img_ctrl5_bit2_1 ;
|
581 |
|
|
reg [31 : 12] pci_ba5_bit31_12 ;
|
582 |
|
|
reg pci_ba5_bit0 ;
|
583 |
|
|
reg [31 : 12] pci_am5 ;
|
584 |
|
|
reg [31 : 12] pci_ta5 ;
|
585 |
|
|
`endif
|
586 |
|
|
reg [31 : 24] pci_err_cs_bit31_24 ;
|
587 |
|
|
reg pci_err_cs_bit10 ;
|
588 |
|
|
reg pci_err_cs_bit8 ;
|
589 |
|
|
reg pci_err_cs_bit0 ;
|
590 |
|
|
reg [31 : 0] pci_err_addr ;
|
591 |
|
|
reg [31 : 0] pci_err_data ;
|
592 |
|
|
|
593 |
|
|
|
594 |
|
|
/*###########################################################################################################
|
595 |
|
|
-------------------------------------------------------------------------------------------------------------
|
596 |
|
|
WISHBONE Slave configuration registers
|
597 |
|
|
There are also some registers with NOT all bits implemented and therefor uses _bitX or _bitX2_X1 to
|
598 |
|
|
sign which bit or range of bits are implemented. Some special cases and examples are described below!
|
599 |
|
|
-------------------------------------------------------------------------------------------------------------
|
600 |
|
|
###########################################################################################################*/
|
601 |
|
|
|
602 |
|
|
/*-----------------------------------------------------------------------------------------------------------
|
603 |
|
|
[800h-85Ch]
|
604 |
|
|
Depending on defines (WB_IMAGE1 or .. or WB_IMAGE4 or WB_IMAGE5) in constants.v file, there are
|
605 |
|
|
registers corresponding to each IMAGE defined to REG and parameter wb_image_X assigned to '1'.
|
606 |
|
|
The maximum number of images is "6". By default there are first two images used and the first (WB_IMAGE0)
|
607 |
|
|
is assigned to Configuration space! With a 'define' WB_IMAGEx you choose the number of used WB IMAGES in
|
608 |
|
|
a bridge without WB_IMAGE0 (e.g. WB_IMAGE3 tells, that WB_IMAGE1, WB_IMAGE2 and WB_IMAGE3 are used for
|
609 |
|
|
mapping the space from PCI to WB. Offcourse, WB_IMAGE0 is assigned to Configuration space). That leave
|
610 |
|
|
us WB_IMAGE5 as the maximum number of images.
|
611 |
|
|
|
612 |
|
|
When error occurs, WISHBONE ERR_ADDR and ERR_DATA registers stores address and data on the bus that
|
613 |
|
|
caused error. While ERR_CS register stores Byte Enables and Bus Command in the MSByte. In bits 10, 9
|
614 |
|
|
and 8 it reports Retry Counter Expired (for posted writes), Error Source (Master Abort) and Error
|
615 |
|
|
Report Signal (signals that error has occured) respectively. With bit 0 we enable Error Reporting
|
616 |
|
|
mechanism.
|
617 |
|
|
-----------------------------------------------------------------------------------------------------------*/
|
618 |
|
|
// WB_IMAGE0 is always assigned to config. space
|
619 |
|
|
parameter wb_image0 = 1 ;
|
620 |
|
|
wire [2 : 0] wb_img_ctrl0_bit2_0 = 3'b000 ; // NO addr.transl., pre-fetch and read-line
|
621 |
|
|
wire [31 : 12] wb_ba0_bit31_12 = `WB_CONFIGURATION_BASE ;
|
622 |
|
|
wire wb_ba0_bit0 = 0 ; // config. space is MEMORY space
|
623 |
6 |
mihad |
wire [31 : 12] wb_am0 = `WB_AM0 ; // 4KBytes of configuration space is minimum
|
624 |
2 |
mihad |
wire [31 : 12] wb_ta0 = 20'h0000_0 ; // NO address translation needed
|
625 |
|
|
// WB_IMAGE0 and WB_IMAGE1 are included by default meanwhile others are optional !
|
626 |
|
|
parameter wb_image1 = 1 ;
|
627 |
|
|
reg [2 : 0] wb_img_ctrl1_bit2_0 ;
|
628 |
|
|
reg [31 : 12] wb_ba1_bit31_12 ;
|
629 |
|
|
reg wb_ba1_bit0 ;
|
630 |
|
|
reg [31 : 12] wb_am1 ;
|
631 |
|
|
reg [31 : 12] wb_ta1 ;
|
632 |
|
|
`ifdef WB_IMAGE1
|
633 |
|
|
parameter wb_image2 = 0 ;
|
634 |
|
|
wire [2 : 0] wb_img_ctrl2_bit2_0 = 3'b000 ;
|
635 |
|
|
wire [31 : 12] wb_ba2_bit31_12 = 20'h0000_0 ;
|
636 |
|
|
wire wb_ba2_bit0 = 1'b0 ;
|
637 |
|
|
wire [31 : 12] wb_am2 = 20'h0000_0 ;
|
638 |
|
|
wire [31 : 12] wb_ta2 = 20'h0000_0 ;
|
639 |
|
|
|
640 |
|
|
parameter wb_image3 = 0 ;
|
641 |
|
|
wire [2 : 0] wb_img_ctrl3_bit2_0 = 3'b000 ;
|
642 |
|
|
wire [31 : 12] wb_ba3_bit31_12 = 20'h0000_0 ;
|
643 |
|
|
wire wb_ba3_bit0 = 1'b0 ;
|
644 |
|
|
wire [31 : 12] wb_am3 = 20'h0000_0 ;
|
645 |
|
|
wire [31 : 12] wb_ta3 = 20'h0000_0 ;
|
646 |
|
|
|
647 |
|
|
parameter wb_image4 = 0 ;
|
648 |
|
|
wire [2 : 0] wb_img_ctrl4_bit2_0 = 3'b000 ;
|
649 |
|
|
wire [31 : 12] wb_ba4_bit31_12 = 20'h0000_0 ;
|
650 |
|
|
wire wb_ba4_bit0 = 1'b0 ;
|
651 |
|
|
wire [31 : 12] wb_am4 = 20'h0000_0 ;
|
652 |
|
|
wire [31 : 12] wb_ta4 = 20'h0000_0 ;
|
653 |
|
|
|
654 |
|
|
parameter wb_image5 = 0 ;
|
655 |
|
|
wire [2 : 0] wb_img_ctrl5_bit2_0 = 3'b000 ;
|
656 |
|
|
wire [31 : 12] wb_ba5_bit31_12 = 20'h0000_0 ;
|
657 |
|
|
wire wb_ba5_bit0 = 1'b0 ;
|
658 |
|
|
wire [31 : 12] wb_am5 = 20'h0000_0 ;
|
659 |
|
|
wire [31 : 12] wb_ta5 = 20'h0000_0 ;
|
660 |
|
|
`endif
|
661 |
|
|
`ifdef WB_IMAGE2
|
662 |
|
|
parameter wb_image2 = 1 ;
|
663 |
|
|
reg [2 : 0] wb_img_ctrl2_bit2_0 ;
|
664 |
|
|
reg [31 : 12] wb_ba2_bit31_12 ;
|
665 |
|
|
reg wb_ba2_bit0 ;
|
666 |
|
|
reg [31 : 12] wb_am2 ;
|
667 |
|
|
reg [31 : 12] wb_ta2 ;
|
668 |
|
|
|
669 |
|
|
parameter wb_image3 = 0 ;
|
670 |
|
|
wire [2 : 0] wb_img_ctrl3_bit2_0 = 3'b000 ;
|
671 |
|
|
wire [31 : 12] wb_ba3_bit31_12 = 20'h0000_0 ;
|
672 |
|
|
wire wb_ba3_bit0 = 1'b0 ;
|
673 |
|
|
wire [31 : 12] wb_am3 = 20'h0000_0 ;
|
674 |
|
|
wire [31 : 12] wb_ta3 = 20'h0000_0 ;
|
675 |
|
|
|
676 |
|
|
parameter wb_image4 = 0 ;
|
677 |
|
|
wire [2 : 0] wb_img_ctrl4_bit2_0 = 3'b000 ;
|
678 |
|
|
wire [31 : 12] wb_ba4_bit31_12 = 20'h0000_0 ;
|
679 |
|
|
wire wb_ba4_bit0 = 1'b0 ;
|
680 |
|
|
wire [31 : 12] wb_am4 = 20'h0000_0 ;
|
681 |
|
|
wire [31 : 12] wb_ta4 = 20'h0000_0 ;
|
682 |
|
|
|
683 |
|
|
parameter wb_image5 = 0 ;
|
684 |
|
|
wire [2 : 0] wb_img_ctrl5_bit2_0 = 3'b000 ;
|
685 |
|
|
wire [31 : 12] wb_ba5_bit31_12 = 20'h0000_0 ;
|
686 |
|
|
wire wb_ba5_bit0 = 1'b0 ;
|
687 |
|
|
wire [31 : 12] wb_am5 = 20'h0000_0 ;
|
688 |
|
|
wire [31 : 12] wb_ta5 = 20'h0000_0 ;
|
689 |
|
|
`endif
|
690 |
|
|
`ifdef WB_IMAGE3
|
691 |
|
|
parameter wb_image2 = 1 ;
|
692 |
|
|
reg [2 : 0] wb_img_ctrl2_bit2_0 ;
|
693 |
|
|
reg [31 : 12] wb_ba2_bit31_12 ;
|
694 |
|
|
reg wb_ba2_bit0 ;
|
695 |
|
|
reg [31 : 12] wb_am2 ;
|
696 |
|
|
reg [31 : 12] wb_ta2 ;
|
697 |
|
|
|
698 |
|
|
parameter wb_image3 = 1 ;
|
699 |
|
|
reg [2 : 0] wb_img_ctrl3_bit2_0 ;
|
700 |
|
|
reg [31 : 12] wb_ba3_bit31_12 ;
|
701 |
|
|
reg wb_ba3_bit0 ;
|
702 |
|
|
reg [31 : 12] wb_am3 ;
|
703 |
|
|
reg [31 : 12] wb_ta3 ;
|
704 |
|
|
|
705 |
|
|
parameter wb_image4 = 0 ;
|
706 |
|
|
wire [2 : 0] wb_img_ctrl4_bit2_0 = 3'b000 ;
|
707 |
|
|
wire [31 : 12] wb_ba4_bit31_12 = 20'h0000_0 ;
|
708 |
|
|
wire wb_ba4_bit0 = 1'b0 ;
|
709 |
|
|
wire [31 : 12] wb_am4 = 20'h0000_0 ;
|
710 |
|
|
wire [31 : 12] wb_ta4 = 20'h0000_0 ;
|
711 |
|
|
|
712 |
|
|
parameter wb_image5 = 0 ;
|
713 |
|
|
wire [2 : 0] wb_img_ctrl5_bit2_0 = 3'b000 ;
|
714 |
|
|
wire [31 : 12] wb_ba5_bit31_12 = 20'h0000_0 ;
|
715 |
|
|
wire wb_ba5_bit0 = 1'b0 ;
|
716 |
|
|
wire [31 : 12] wb_am5 = 20'h0000_0 ;
|
717 |
|
|
wire [31 : 12] wb_ta5 = 20'h0000_0 ;
|
718 |
|
|
`endif
|
719 |
|
|
`ifdef WB_IMAGE4
|
720 |
|
|
parameter wb_image2 = 1 ;
|
721 |
|
|
reg [2 : 0] wb_img_ctrl2_bit2_0 ;
|
722 |
|
|
reg [31 : 12] wb_ba2_bit31_12 ;
|
723 |
|
|
reg wb_ba2_bit0 ;
|
724 |
|
|
reg [31 : 12] wb_am2 ;
|
725 |
|
|
reg [31 : 12] wb_ta2 ;
|
726 |
|
|
|
727 |
|
|
parameter wb_image3 = 1 ;
|
728 |
|
|
reg [2 : 0] wb_img_ctrl3_bit2_0 ;
|
729 |
|
|
reg [31 : 12] wb_ba3_bit31_12 ;
|
730 |
|
|
reg wb_ba3_bit0 ;
|
731 |
|
|
reg [31 : 12] wb_am3 ;
|
732 |
|
|
reg [31 : 12] wb_ta3 ;
|
733 |
|
|
|
734 |
|
|
parameter wb_image4 = 1 ;
|
735 |
|
|
reg [2 : 0] wb_img_ctrl4_bit2_0 ;
|
736 |
|
|
reg [31 : 12] wb_ba4_bit31_12 ;
|
737 |
|
|
reg wb_ba4_bit0 ;
|
738 |
|
|
reg [31 : 12] wb_am4 ;
|
739 |
|
|
reg [31 : 12] wb_ta4 ;
|
740 |
|
|
|
741 |
|
|
parameter wb_image5 = 0 ;
|
742 |
|
|
wire [2 : 0] wb_img_ctrl5_bit2_0 = 3'b000 ;
|
743 |
6 |
mihad |
wire [31 : 12] wb_ba5_bit31_12 = 20'h0000_0 ;
|
744 |
2 |
mihad |
wire wb_ba5_bit0 = 1'b0 ;
|
745 |
|
|
wire [31 : 12] wb_am5 = 20'h0000_0 ;
|
746 |
|
|
wire [31 : 12] wb_ta5 = 20'h0000_0 ;
|
747 |
|
|
`endif
|
748 |
|
|
`ifdef WB_IMAGE5
|
749 |
|
|
parameter wb_image2 = 1 ;
|
750 |
|
|
reg [2 : 0] wb_img_ctrl2_bit2_0 ;
|
751 |
|
|
reg [31 : 12] wb_ba2_bit31_12 ;
|
752 |
|
|
reg wb_ba2_bit0 ;
|
753 |
|
|
reg [31 : 12] wb_am2 ;
|
754 |
|
|
reg [31 : 12] wb_ta2 ;
|
755 |
|
|
|
756 |
|
|
parameter wb_image3 = 1 ;
|
757 |
|
|
reg [2 : 0] wb_img_ctrl3_bit2_0 ;
|
758 |
|
|
reg [31 : 12] wb_ba3_bit31_12 ;
|
759 |
|
|
reg wb_ba3_bit0 ;
|
760 |
|
|
reg [31 : 12] wb_am3 ;
|
761 |
|
|
reg [31 : 12] wb_ta3 ;
|
762 |
|
|
|
763 |
|
|
parameter wb_image4 = 1 ;
|
764 |
|
|
reg [2 : 0] wb_img_ctrl4_bit2_0 ;
|
765 |
|
|
reg [31 : 12] wb_ba4_bit31_12 ;
|
766 |
|
|
reg wb_ba4_bit0 ;
|
767 |
|
|
reg [31 : 12] wb_am4 ;
|
768 |
|
|
reg [31 : 12] wb_ta4 ;
|
769 |
|
|
|
770 |
|
|
parameter wb_image5 = 1 ;
|
771 |
|
|
reg [2 : 0] wb_img_ctrl5_bit2_0 ;
|
772 |
|
|
reg [31 : 12] wb_ba5_bit31_12 ;
|
773 |
|
|
reg wb_ba5_bit0 ;
|
774 |
|
|
reg [31 : 12] wb_am5 ;
|
775 |
|
|
reg [31 : 12] wb_ta5 ;
|
776 |
|
|
`endif
|
777 |
|
|
reg [31 : 24] wb_err_cs_bit31_24 ;
|
778 |
|
|
reg [10 : 8] wb_err_cs_bit10_8 ;
|
779 |
|
|
reg wb_err_cs_bit0 ;
|
780 |
|
|
reg [31 : 0] wb_err_addr ;
|
781 |
|
|
reg [31 : 0] wb_err_data ;
|
782 |
|
|
|
783 |
|
|
|
784 |
|
|
/*###########################################################################################################
|
785 |
|
|
-------------------------------------------------------------------------------------------------------------
|
786 |
|
|
Configuration Cycle address register
|
787 |
|
|
There are also some registers with NOT all bits implemented and therefor uses _bitX or _bitX2_X1 to
|
788 |
|
|
sign which bit or range of bits are implemented.
|
789 |
|
|
-------------------------------------------------------------------------------------------------------------
|
790 |
|
|
###########################################################################################################*/
|
791 |
|
|
|
792 |
|
|
/*-----------------------------------------------------------------------------------------------------------
|
793 |
|
|
[860h-868h]
|
794 |
|
|
PCI bridge must ignore Type 1 configuration cycles (Master Abort) since they are used for PCI to PCI
|
795 |
|
|
bridges. This is single function device, that means responding on configuration cycles to all functions
|
796 |
|
|
(or responding only to function 0). Configuration address register for generating configuration cycles
|
797 |
|
|
is prepared for all options (it includes Bus Number, Device, Function, Offset and Type).
|
798 |
|
|
Interrupt acknowledge register stores interrupt vector data returned during Interrupt Acknowledge cycle.
|
799 |
|
|
-----------------------------------------------------------------------------------------------------------*/
|
800 |
|
|
reg [23 : 2] cnf_addr_bit23_2 ;
|
801 |
|
|
reg cnf_addr_bit0 ;
|
802 |
|
|
// reg [31 : 0] cnf_data ; IMPLEMENTED elsewhere !!!!!
|
803 |
|
|
// reg [31 : 0] int_ack ; IMPLEMENTED elsewhere !!!!!
|
804 |
|
|
|
805 |
|
|
|
806 |
|
|
/*###########################################################################################################
|
807 |
|
|
-------------------------------------------------------------------------------------------------------------
|
808 |
|
|
General Interrupt registers
|
809 |
|
|
There are also some registers with NOT all bits implemented and therefor uses _bitX or _bitX2_X1 to
|
810 |
|
|
sign which bit or range of bits are implemented.
|
811 |
|
|
-------------------------------------------------------------------------------------------------------------
|
812 |
|
|
###########################################################################################################*/
|
813 |
|
|
|
814 |
|
|
/*-----------------------------------------------------------------------------------------------------------
|
815 |
|
|
[FF8h-FFCh]
|
816 |
|
|
Bit 31 in the Interrupt Control register is set by software and used to generate SOFT RESET. Other 4
|
817 |
|
|
bits are used to enable interrupt generations.
|
818 |
|
|
4 LSbits in the Interrupt Status register are indicating System Error Int, Parity Error Int, Error
|
819 |
|
|
Int and Inerrupt respecively.
|
820 |
|
|
-----------------------------------------------------------------------------------------------------------*/
|
821 |
|
|
reg icr_bit31 ;
|
822 |
|
|
reg [3 : 0] icr_bit3_0 ;
|
823 |
|
|
reg [3 : 0] isr_bit3_0 ;
|
824 |
|
|
|
825 |
|
|
|
826 |
|
|
/*###########################################################################################################
|
827 |
|
|
-------------------------------------------------------------------------------------------------------------
|
828 |
|
|
|
829 |
|
|
|
830 |
|
|
-----------------------------------------------------------------------------------------------------------*/
|
831 |
|
|
|
832 |
|
|
always@(r_re or
|
833 |
|
|
r_conf_address_in or
|
834 |
|
|
status_bit15_11 or status_bit8 or command_bit8 or command_bit6 or command_bit2_0 or
|
835 |
|
|
latency_timer or cache_line_size_reg or
|
836 |
|
|
pci_ba0_bit31_12 or
|
837 |
|
|
pci_img_ctrl0_bit2_1 or pci_am0 or pci_ta0 or pci_ba0_bit0 or
|
838 |
|
|
pci_img_ctrl1_bit2_1 or pci_am1 or pci_ta1 or pci_ba1_bit31_12 or pci_ba1_bit0 or
|
839 |
|
|
pci_img_ctrl2_bit2_1 or pci_am2 or pci_ta2 or pci_ba2_bit31_12 or pci_ba2_bit0 or
|
840 |
|
|
pci_img_ctrl3_bit2_1 or pci_am3 or pci_ta3 or pci_ba3_bit31_12 or pci_ba3_bit0 or
|
841 |
|
|
pci_img_ctrl4_bit2_1 or pci_am4 or pci_ta4 or pci_ba4_bit31_12 or pci_ba4_bit0 or
|
842 |
|
|
pci_img_ctrl5_bit2_1 or pci_am5 or pci_ta5 or pci_ba5_bit31_12 or pci_ba5_bit0 or
|
843 |
|
|
interrupt_line or
|
844 |
|
|
pci_err_cs_bit31_24 or pci_err_cs_bit10 or pci_err_cs_bit8 or pci_err_cs_bit0 or
|
845 |
|
|
pci_err_addr or pci_err_data or
|
846 |
|
|
wb_ba0_bit31_12 or wb_ba0_bit0 or
|
847 |
|
|
wb_img_ctrl1_bit2_0 or wb_ba1_bit31_12 or wb_ba1_bit0 or wb_am1 or wb_ta1 or
|
848 |
|
|
wb_img_ctrl2_bit2_0 or wb_ba2_bit31_12 or wb_ba2_bit0 or wb_am2 or wb_ta2 or
|
849 |
|
|
wb_img_ctrl3_bit2_0 or wb_ba3_bit31_12 or wb_ba3_bit0 or wb_am3 or wb_ta3 or
|
850 |
|
|
wb_img_ctrl4_bit2_0 or wb_ba4_bit31_12 or wb_ba4_bit0 or wb_am4 or wb_ta4 or
|
851 |
|
|
wb_img_ctrl5_bit2_0 or wb_ba5_bit31_12 or wb_ba5_bit0 or wb_am5 or wb_ta5 or
|
852 |
|
|
wb_err_cs_bit31_24 or wb_err_cs_bit10_8 or wb_err_cs_bit0 or wb_err_addr or wb_err_data or
|
853 |
|
|
cnf_addr_bit23_2 or cnf_addr_bit0 or icr_bit31 or icr_bit3_0 or isr_bit3_0
|
854 |
|
|
)
|
855 |
|
|
begin
|
856 |
|
|
if (r_re == 1'b1)
|
857 |
|
|
begin
|
858 |
|
|
case (r_conf_address_in[8])
|
859 |
|
|
1'b0 :
|
860 |
|
|
begin
|
861 |
|
|
case ({r_conf_address_in[7], r_conf_address_in[6]})
|
862 |
|
|
2'b00 :
|
863 |
|
|
begin
|
864 |
|
|
// PCI header - configuration space
|
865 |
|
|
case (r_conf_address_in[5:2])
|
866 |
|
|
4'h0: r_conf_data_out = { r_device_id, r_vendor_id } ;
|
867 |
|
|
4'h1: r_conf_data_out = { status_bit15_11, r_status_bit10_9, status_bit8, 2'h0, r_status_bit5,
|
868 |
|
|
5'h00, 7'h00, command_bit8, 1'h0, command_bit6, 3'h0, command_bit2_0 } ;
|
869 |
|
|
4'h2: r_conf_data_out = { r_class_code, r_revision_id } ;
|
870 |
|
|
4'h3: r_conf_data_out = { 8'h00, r_header_type, latency_timer, cache_line_size_reg } ;
|
871 |
|
|
4'h4: r_conf_data_out = { pci_ba0_bit31_12, 11'h000, pci_ba0_bit0 } & { pci_am0[31:12], 12'h001 } ;
|
872 |
|
|
4'h5: r_conf_data_out = { pci_ba1_bit31_12, 11'h000, pci_ba1_bit0 } & { pci_am1[31:12], 12'h001 } ;
|
873 |
|
|
4'h6: r_conf_data_out = { pci_ba2_bit31_12, 11'h000, pci_ba2_bit0 } & { pci_am2[31:12], 12'h001 } ;
|
874 |
|
|
4'h7: r_conf_data_out = { pci_ba3_bit31_12, 11'h000, pci_ba3_bit0 } & { pci_am3[31:12], 12'h001 } ;
|
875 |
|
|
4'h8: r_conf_data_out = { pci_ba4_bit31_12, 11'h000, pci_ba4_bit0 } & { pci_am4[31:12], 12'h001 } ;
|
876 |
|
|
4'h9: r_conf_data_out = { pci_ba5_bit31_12, 11'h000, pci_ba5_bit0 } & { pci_am5[31:12], 12'h001 } ;
|
877 |
|
|
4'hf: r_conf_data_out = { r_max_lat, r_min_gnt, r_interrupt_pin, interrupt_line } ;
|
878 |
|
|
default : r_conf_data_out = 32'h0000_0000 ;
|
879 |
|
|
endcase
|
880 |
|
|
end
|
881 |
|
|
default :
|
882 |
|
|
r_conf_data_out = 32'h0000_0000 ;
|
883 |
|
|
endcase
|
884 |
|
|
end
|
885 |
|
|
default :
|
886 |
|
|
begin
|
887 |
|
|
// PCI target - configuration space
|
888 |
|
|
case (r_conf_address_in[7:2])
|
889 |
|
|
`P_IMG_CTRL0_ADDR: r_conf_data_out = { 29'h00000000, pci_img_ctrl0_bit2_1, 1'h0 } ;
|
890 |
|
|
`P_BA0_ADDR : r_conf_data_out = { pci_ba0_bit31_12, 11'h000, pci_ba0_bit0 } & { pci_am0[31:12], 12'h001 } ;
|
891 |
|
|
`P_AM0_ADDR : r_conf_data_out = { pci_am0, 12'h000 } ;
|
892 |
|
|
`P_TA0_ADDR : r_conf_data_out = { pci_ta0, 12'h000 } ;
|
893 |
|
|
`P_IMG_CTRL1_ADDR: r_conf_data_out = { 29'h00000000, pci_img_ctrl1_bit2_1, 1'h0 } ;
|
894 |
|
|
`P_BA1_ADDR : r_conf_data_out = { pci_ba1_bit31_12, 11'h000, pci_ba1_bit0 } & { pci_am1[31:12], 12'h001 } ;
|
895 |
|
|
`P_AM1_ADDR : r_conf_data_out = { pci_am1, 12'h000 } ;
|
896 |
|
|
`P_TA1_ADDR : r_conf_data_out = { pci_ta1, 12'h000 } ;
|
897 |
|
|
`P_IMG_CTRL2_ADDR: r_conf_data_out = { 29'h00000000, pci_img_ctrl2_bit2_1, 1'h0 } ;
|
898 |
|
|
`P_BA2_ADDR : r_conf_data_out = { pci_ba2_bit31_12, 11'h000, pci_ba2_bit0 } & { pci_am2[31:12], 12'h001 } ;
|
899 |
|
|
`P_AM2_ADDR : r_conf_data_out = { pci_am2, 12'h000 } ;
|
900 |
|
|
`P_TA2_ADDR : r_conf_data_out = { pci_ta2, 12'h000 } ;
|
901 |
|
|
`P_IMG_CTRL3_ADDR: r_conf_data_out = { 29'h00000000, pci_img_ctrl3_bit2_1, 1'h0 } ;
|
902 |
|
|
`P_BA3_ADDR : r_conf_data_out = { pci_ba3_bit31_12, 11'h000, pci_ba3_bit0 } & { pci_am3[31:12], 12'h001 } ;
|
903 |
|
|
`P_AM3_ADDR : r_conf_data_out = { pci_am3, 12'h000 } ;
|
904 |
|
|
`P_TA3_ADDR : r_conf_data_out = { pci_ta3, 12'h000 } ;
|
905 |
|
|
`P_IMG_CTRL4_ADDR: r_conf_data_out = { 29'h00000000, pci_img_ctrl4_bit2_1, 1'h0 } ;
|
906 |
|
|
`P_BA4_ADDR : r_conf_data_out = { pci_ba4_bit31_12, 11'h000, pci_ba4_bit0 } & { pci_am4[31:12], 12'h001 } ;
|
907 |
|
|
`P_AM4_ADDR : r_conf_data_out = { pci_am4, 12'h000 } ;
|
908 |
|
|
`P_TA4_ADDR : r_conf_data_out = { pci_ta4, 12'h000 } ;
|
909 |
|
|
`P_IMG_CTRL5_ADDR: r_conf_data_out = { 29'h00000000, pci_img_ctrl5_bit2_1, 1'h0 } ;
|
910 |
|
|
`P_BA5_ADDR : r_conf_data_out = { pci_ba5_bit31_12, 11'h000, pci_ba5_bit0 } & { pci_am5[31:12], 12'h001 } ;
|
911 |
|
|
`P_AM5_ADDR : r_conf_data_out = { pci_am5, 12'h000 } ;
|
912 |
|
|
`P_TA5_ADDR : r_conf_data_out = { pci_ta5, 12'h000 } ;
|
913 |
|
|
`P_ERR_CS_ADDR : r_conf_data_out = { pci_err_cs_bit31_24, 13'h0000, pci_err_cs_bit10, 1'h0,
|
914 |
|
|
pci_err_cs_bit8, 7'h00, pci_err_cs_bit0 } ;
|
915 |
|
|
`P_ERR_ADDR_ADDR : r_conf_data_out = pci_err_addr ;
|
916 |
|
|
`P_ERR_DATA_ADDR : r_conf_data_out = pci_err_data ;
|
917 |
|
|
// WB slave - configuration space
|
918 |
|
|
`WB_CONF_SPC_BAR_ADDR: r_conf_data_out = { wb_ba0_bit31_12, 11'h000, wb_ba0_bit0 } ;
|
919 |
|
|
`W_IMG_CTRL1_ADDR: r_conf_data_out = { 29'h00000000, wb_img_ctrl1_bit2_0 } ;
|
920 |
|
|
`W_BA1_ADDR : r_conf_data_out = { wb_ba1_bit31_12, 11'h000, wb_ba1_bit0 } & { wb_am1[31:12], 12'h001 } ;
|
921 |
|
|
`W_AM1_ADDR : r_conf_data_out = { wb_am1, 12'h000 } ;
|
922 |
|
|
`W_TA1_ADDR : r_conf_data_out = { wb_ta1, 12'h000 } ;
|
923 |
|
|
`W_IMG_CTRL2_ADDR: r_conf_data_out = { 29'h00000000, wb_img_ctrl2_bit2_0 } ;
|
924 |
|
|
`W_BA2_ADDR : r_conf_data_out = { wb_ba2_bit31_12, 11'h000, wb_ba2_bit0 } & { wb_am2[31:12], 12'h001 } ;
|
925 |
|
|
`W_AM2_ADDR : r_conf_data_out = { wb_am2, 12'h000 } ;
|
926 |
|
|
`W_TA2_ADDR : r_conf_data_out = { wb_ta2, 12'h000 } ;
|
927 |
|
|
`W_IMG_CTRL3_ADDR: r_conf_data_out = { 29'h00000000, wb_img_ctrl3_bit2_0 } ;
|
928 |
|
|
`W_BA3_ADDR : r_conf_data_out = { wb_ba3_bit31_12, 11'h000, wb_ba3_bit0 } & { wb_am3[31:12], 12'h001 } ;
|
929 |
|
|
`W_AM3_ADDR : r_conf_data_out = { wb_am3, 12'h000 } ;
|
930 |
|
|
`W_TA3_ADDR : r_conf_data_out = { wb_ta3, 12'h000 } ;
|
931 |
|
|
`W_IMG_CTRL4_ADDR: r_conf_data_out = { 29'h00000000, wb_img_ctrl4_bit2_0 } ;
|
932 |
|
|
`W_BA4_ADDR : r_conf_data_out = { wb_ba4_bit31_12, 11'h000, wb_ba4_bit0 } & { wb_am4[31:12], 12'h001 } ;
|
933 |
|
|
`W_AM4_ADDR : r_conf_data_out = { wb_am4, 12'h000 } ;
|
934 |
|
|
`W_TA4_ADDR : r_conf_data_out = { wb_ta4, 12'h000 } ;
|
935 |
|
|
`W_IMG_CTRL5_ADDR: r_conf_data_out = { 29'h00000000, wb_img_ctrl5_bit2_0 } ;
|
936 |
|
|
`W_BA5_ADDR : r_conf_data_out = { wb_ba5_bit31_12, 11'h000, wb_ba5_bit0 } & { wb_am5[31:12], 12'h001 } ;
|
937 |
|
|
`W_AM5_ADDR : r_conf_data_out = { wb_am5, 12'h000 } ;
|
938 |
|
|
`W_TA5_ADDR : r_conf_data_out = { wb_ta5, 12'h000 } ;
|
939 |
|
|
`W_ERR_CS_ADDR : r_conf_data_out = { wb_err_cs_bit31_24, 13'h0000, wb_err_cs_bit10_8,
|
940 |
|
|
7'h00, wb_err_cs_bit0 } ;
|
941 |
|
|
`W_ERR_ADDR_ADDR : r_conf_data_out = wb_err_addr ;
|
942 |
|
|
`W_ERR_DATA_ADDR : r_conf_data_out = wb_err_data ;
|
943 |
|
|
|
944 |
|
|
`CNF_ADDR_ADDR : r_conf_data_out = { 8'h00, cnf_addr_bit23_2, 1'h0, cnf_addr_bit0 } ;
|
945 |
|
|
// `CNF_DATA_ADDR: implemented elsewhere !!!
|
946 |
|
|
// `INT_ACK_ADDR : implemented elsewhere !!!
|
947 |
|
|
`ICR_ADDR : r_conf_data_out = { icr_bit31, 27'h0000_000, icr_bit3_0 } ;
|
948 |
|
|
`ISR_ADDR : r_conf_data_out = { 28'h0000_000, isr_bit3_0 } ;
|
949 |
|
|
|
950 |
|
|
default : r_conf_data_out = 32'h0000_0000 ;
|
951 |
|
|
endcase
|
952 |
|
|
end
|
953 |
|
|
endcase
|
954 |
|
|
end
|
955 |
|
|
else
|
956 |
|
|
r_conf_data_out = 32'h0000_0000 ;
|
957 |
|
|
end
|
958 |
|
|
|
959 |
|
|
always@(w_re or
|
960 |
|
|
w_conf_address_in or
|
961 |
|
|
status_bit15_11 or status_bit8 or command_bit8 or command_bit6 or command_bit2_0 or
|
962 |
|
|
latency_timer or cache_line_size_reg or
|
963 |
|
|
pci_ba0_bit31_12 or
|
964 |
|
|
pci_img_ctrl0_bit2_1 or pci_am0 or pci_ta0 or pci_ba0_bit0 or
|
965 |
|
|
pci_img_ctrl1_bit2_1 or pci_am1 or pci_ta1 or pci_ba1_bit31_12 or pci_ba1_bit0 or
|
966 |
|
|
pci_img_ctrl2_bit2_1 or pci_am2 or pci_ta2 or pci_ba2_bit31_12 or pci_ba2_bit0 or
|
967 |
|
|
pci_img_ctrl3_bit2_1 or pci_am3 or pci_ta3 or pci_ba3_bit31_12 or pci_ba3_bit0 or
|
968 |
|
|
pci_img_ctrl4_bit2_1 or pci_am4 or pci_ta4 or pci_ba4_bit31_12 or pci_ba4_bit0 or
|
969 |
|
|
pci_img_ctrl5_bit2_1 or pci_am5 or pci_ta5 or pci_ba5_bit31_12 or pci_ba5_bit0 or
|
970 |
|
|
interrupt_line or
|
971 |
|
|
pci_err_cs_bit31_24 or pci_err_cs_bit10 or pci_err_cs_bit8 or pci_err_cs_bit0 or
|
972 |
|
|
pci_err_addr or pci_err_data or
|
973 |
|
|
wb_ba0_bit31_12 or wb_ba0_bit0 or
|
974 |
|
|
wb_img_ctrl1_bit2_0 or wb_ba1_bit31_12 or wb_ba1_bit0 or wb_am1 or wb_ta1 or
|
975 |
|
|
wb_img_ctrl2_bit2_0 or wb_ba2_bit31_12 or wb_ba2_bit0 or wb_am2 or wb_ta2 or
|
976 |
|
|
wb_img_ctrl3_bit2_0 or wb_ba3_bit31_12 or wb_ba3_bit0 or wb_am3 or wb_ta3 or
|
977 |
|
|
wb_img_ctrl4_bit2_0 or wb_ba4_bit31_12 or wb_ba4_bit0 or wb_am4 or wb_ta4 or
|
978 |
|
|
wb_img_ctrl5_bit2_0 or wb_ba5_bit31_12 or wb_ba5_bit0 or wb_am5 or wb_ta5 or
|
979 |
|
|
wb_err_cs_bit31_24 or wb_err_cs_bit10_8 or wb_err_cs_bit0 or wb_err_addr or wb_err_data or
|
980 |
|
|
cnf_addr_bit23_2 or cnf_addr_bit0 or icr_bit31 or icr_bit3_0 or isr_bit3_0
|
981 |
|
|
)
|
982 |
|
|
begin
|
983 |
|
|
if (w_re == 1'b1)
|
984 |
|
|
begin
|
985 |
|
|
case (w_conf_address_in[8])
|
986 |
|
|
1'b0 :
|
987 |
|
|
begin
|
988 |
|
|
case ({w_conf_address_in[7], w_conf_address_in[6]})
|
989 |
|
|
2'b00 :
|
990 |
|
|
begin
|
991 |
|
|
// PCI header - configuration space
|
992 |
|
|
case (w_conf_address_in[5:2])
|
993 |
|
|
4'h0: w_conf_data_out = { r_device_id, r_vendor_id } ;
|
994 |
|
|
4'h1: w_conf_data_out = { status_bit15_11, r_status_bit10_9, status_bit8, 2'h0, r_status_bit5,
|
995 |
|
|
5'h00, 7'h00, command_bit8, 1'h0, command_bit6, 3'h0, command_bit2_0 } ;
|
996 |
|
|
4'h2: w_conf_data_out = { r_class_code, r_revision_id } ;
|
997 |
|
|
4'h3: w_conf_data_out = { 8'h00, r_header_type, latency_timer, cache_line_size_reg } ;
|
998 |
|
|
4'h4: w_conf_data_out = { pci_ba0_bit31_12, 11'h000, pci_ba0_bit0 } & { pci_am0[31:12], 12'h001 } ;
|
999 |
|
|
4'h5: w_conf_data_out = { pci_ba1_bit31_12, 11'h000, pci_ba1_bit0 } & { pci_am1[31:12], 12'h001 } ;
|
1000 |
|
|
4'h6: w_conf_data_out = { pci_ba2_bit31_12, 11'h000, pci_ba2_bit0 } & { pci_am2[31:12], 12'h001 } ;
|
1001 |
|
|
4'h7: w_conf_data_out = { pci_ba3_bit31_12, 11'h000, pci_ba3_bit0 } & { pci_am3[31:12], 12'h001 } ;
|
1002 |
|
|
4'h8: w_conf_data_out = { pci_ba4_bit31_12, 11'h000, pci_ba4_bit0 } & { pci_am4[31:12], 12'h001 } ;
|
1003 |
|
|
4'h9: w_conf_data_out = { pci_ba5_bit31_12, 11'h000, pci_ba5_bit0 } & { pci_am5[31:12], 12'h001 } ;
|
1004 |
|
|
4'hf: w_conf_data_out = { r_max_lat, r_min_gnt, r_interrupt_pin, interrupt_line } ;
|
1005 |
|
|
default : w_conf_data_out = 32'h0000_0000 ;
|
1006 |
|
|
endcase
|
1007 |
|
|
end
|
1008 |
|
|
default :
|
1009 |
|
|
w_conf_data_out = 32'h0000_0000 ;
|
1010 |
|
|
endcase
|
1011 |
|
|
end
|
1012 |
|
|
default :
|
1013 |
|
|
begin
|
1014 |
|
|
// PCI target - configuration space
|
1015 |
|
|
case (w_conf_address_in[7:2])
|
1016 |
|
|
`P_IMG_CTRL0_ADDR: w_conf_data_out = { 29'h00000000, pci_img_ctrl0_bit2_1, 1'h0 } ;
|
1017 |
|
|
`P_BA0_ADDR : w_conf_data_out = { pci_ba0_bit31_12, 11'h000, pci_ba0_bit0 } & { pci_am0[31:12], 12'h001 } ;
|
1018 |
|
|
`P_AM0_ADDR : w_conf_data_out = { pci_am0, 12'h000 } ;
|
1019 |
|
|
`P_TA0_ADDR : w_conf_data_out = { pci_ta0, 12'h000 } ;
|
1020 |
|
|
`P_IMG_CTRL1_ADDR: w_conf_data_out = { 29'h00000000, pci_img_ctrl1_bit2_1, 1'h0 } ;
|
1021 |
|
|
`P_BA1_ADDR : w_conf_data_out = { pci_ba1_bit31_12, 11'h000, pci_ba1_bit0 } & { pci_am1[31:12], 12'h001 } ;
|
1022 |
|
|
`P_AM1_ADDR : w_conf_data_out = { pci_am1, 12'h000 } ;
|
1023 |
|
|
`P_TA1_ADDR : w_conf_data_out = { pci_ta1, 12'h000 } ;
|
1024 |
|
|
`P_IMG_CTRL2_ADDR: w_conf_data_out = { 29'h00000000, pci_img_ctrl2_bit2_1, 1'h0 } ;
|
1025 |
|
|
`P_BA2_ADDR : w_conf_data_out = { pci_ba2_bit31_12, 11'h000, pci_ba2_bit0 } & { pci_am2[31:12], 12'h001 } ;
|
1026 |
|
|
`P_AM2_ADDR : w_conf_data_out = { pci_am2, 12'h000 } ;
|
1027 |
|
|
`P_TA2_ADDR : w_conf_data_out = { pci_ta2, 12'h000 } ;
|
1028 |
|
|
`P_IMG_CTRL3_ADDR: w_conf_data_out = { 29'h00000000, pci_img_ctrl3_bit2_1, 1'h0 } ;
|
1029 |
|
|
`P_BA3_ADDR : w_conf_data_out = { pci_ba3_bit31_12, 11'h000, pci_ba3_bit0 } & { pci_am3[31:12], 12'h001 } ;
|
1030 |
|
|
`P_AM3_ADDR : w_conf_data_out = { pci_am3, 12'h000 } ;
|
1031 |
|
|
`P_TA3_ADDR : w_conf_data_out = { pci_ta3, 12'h000 } ;
|
1032 |
|
|
`P_IMG_CTRL4_ADDR: w_conf_data_out = { 29'h00000000, pci_img_ctrl4_bit2_1, 1'h0 } ;
|
1033 |
|
|
`P_BA4_ADDR : w_conf_data_out = { pci_ba4_bit31_12, 11'h000, pci_ba4_bit0 } & { pci_am4[31:12], 12'h001 } ;
|
1034 |
|
|
`P_AM4_ADDR : w_conf_data_out = { pci_am4, 12'h000 } ;
|
1035 |
|
|
`P_TA4_ADDR : w_conf_data_out = { pci_ta4, 12'h000 } ;
|
1036 |
|
|
`P_IMG_CTRL5_ADDR: w_conf_data_out = { 29'h00000000, pci_img_ctrl5_bit2_1, 1'h0 } ;
|
1037 |
|
|
`P_BA5_ADDR : w_conf_data_out = { pci_ba5_bit31_12, 11'h000, pci_ba5_bit0 } & { pci_am5[31:12], 12'h001 } ;
|
1038 |
|
|
`P_AM5_ADDR : w_conf_data_out = { pci_am5, 12'h000 } ;
|
1039 |
|
|
`P_TA5_ADDR : w_conf_data_out = { pci_ta5, 12'h000 } ;
|
1040 |
|
|
`P_ERR_CS_ADDR : w_conf_data_out = { pci_err_cs_bit31_24, 13'h0000, pci_err_cs_bit10, 1'h0,
|
1041 |
|
|
pci_err_cs_bit8, 7'h00, pci_err_cs_bit0 } ;
|
1042 |
|
|
`P_ERR_ADDR_ADDR : w_conf_data_out = pci_err_addr ;
|
1043 |
|
|
`P_ERR_DATA_ADDR : w_conf_data_out = pci_err_data ;
|
1044 |
|
|
// WB slave - configuration space
|
1045 |
|
|
`WB_CONF_SPC_BAR_ADDR: w_conf_data_out = { wb_ba0_bit31_12, 11'h000, wb_ba0_bit0 } ;
|
1046 |
|
|
`W_IMG_CTRL1_ADDR: w_conf_data_out = { 29'h00000000, wb_img_ctrl1_bit2_0 } ;
|
1047 |
|
|
`W_BA1_ADDR : w_conf_data_out = { wb_ba1_bit31_12, 11'h000, wb_ba1_bit0 } & { wb_am1[31:12], 12'h001 } ;
|
1048 |
|
|
`W_AM1_ADDR : w_conf_data_out = { wb_am1, 12'h000 } ;
|
1049 |
|
|
`W_TA1_ADDR : w_conf_data_out = { wb_ta1, 12'h000 } ;
|
1050 |
|
|
`W_IMG_CTRL2_ADDR: w_conf_data_out = { 29'h00000000, wb_img_ctrl2_bit2_0 } ;
|
1051 |
|
|
`W_BA2_ADDR : w_conf_data_out = { wb_ba2_bit31_12, 11'h000, wb_ba2_bit0 } & { wb_am2[31:12], 12'h001 } ;
|
1052 |
|
|
`W_AM2_ADDR : w_conf_data_out = { wb_am2, 12'h000 } ;
|
1053 |
|
|
`W_TA2_ADDR : w_conf_data_out = { wb_ta2, 12'h000 } ;
|
1054 |
|
|
`W_IMG_CTRL3_ADDR: w_conf_data_out = { 29'h00000000, wb_img_ctrl3_bit2_0 } ;
|
1055 |
|
|
`W_BA3_ADDR : w_conf_data_out = { wb_ba3_bit31_12, 11'h000, wb_ba3_bit0 } & { wb_am3[31:12], 12'h001 } ;
|
1056 |
|
|
`W_AM3_ADDR : w_conf_data_out = { wb_am3, 12'h000 } ;
|
1057 |
|
|
`W_TA3_ADDR : w_conf_data_out = { wb_ta3, 12'h000 } ;
|
1058 |
|
|
`W_IMG_CTRL4_ADDR: w_conf_data_out = { 29'h00000000, wb_img_ctrl4_bit2_0 } ;
|
1059 |
|
|
`W_BA4_ADDR : w_conf_data_out = { wb_ba4_bit31_12, 11'h000, wb_ba4_bit0 } & { wb_am4[31:12], 12'h001 } ;
|
1060 |
|
|
`W_AM4_ADDR : w_conf_data_out = { wb_am4, 12'h000 } ;
|
1061 |
|
|
`W_TA4_ADDR : w_conf_data_out = { wb_ta4, 12'h000 } ;
|
1062 |
|
|
`W_IMG_CTRL5_ADDR: w_conf_data_out = { 29'h00000000, wb_img_ctrl5_bit2_0 } ;
|
1063 |
|
|
`W_BA5_ADDR : w_conf_data_out = { wb_ba5_bit31_12, 11'h000, wb_ba5_bit0 } & { wb_am5[31:12], 12'h001 } ;
|
1064 |
|
|
`W_AM5_ADDR : w_conf_data_out = { wb_am5, 12'h000 } ;
|
1065 |
|
|
`W_TA5_ADDR : w_conf_data_out = { wb_ta5, 12'h000 } ;
|
1066 |
|
|
`W_ERR_CS_ADDR : w_conf_data_out = { wb_err_cs_bit31_24, 13'h0000, wb_err_cs_bit10_8,
|
1067 |
|
|
7'h00, wb_err_cs_bit0 } ;
|
1068 |
|
|
`W_ERR_ADDR_ADDR : w_conf_data_out = wb_err_addr ;
|
1069 |
|
|
`W_ERR_DATA_ADDR : w_conf_data_out = wb_err_data ;
|
1070 |
|
|
|
1071 |
|
|
`CNF_ADDR_ADDR : w_conf_data_out = { 8'h00, cnf_addr_bit23_2, 1'h0, cnf_addr_bit0 } ;
|
1072 |
|
|
// `CNF_DATA_ADDR: implemented elsewhere !!!
|
1073 |
|
|
// `INT_ACK_ADDR : implemented elsewhere !!!
|
1074 |
|
|
`ICR_ADDR : w_conf_data_out = { icr_bit31, 27'h0000_000, icr_bit3_0 } ;
|
1075 |
|
|
`ISR_ADDR : w_conf_data_out = { 28'h0000_000, isr_bit3_0 } ;
|
1076 |
|
|
default : w_conf_data_out = 32'h0000_0000 ;
|
1077 |
|
|
endcase
|
1078 |
|
|
end
|
1079 |
|
|
endcase
|
1080 |
|
|
end
|
1081 |
|
|
else
|
1082 |
|
|
w_conf_data_out = 32'h0000_0000 ;
|
1083 |
|
|
end
|
1084 |
|
|
|
1085 |
|
|
always@(posedge w_clock or posedge reset)
|
1086 |
|
|
begin
|
1087 |
|
|
// Here are implemented all registers that are reset with RESET signal otherwise they can be normaly written!!!
|
1088 |
|
|
// Registers that are commented are implemented after this alwasy statement, because they are e.g. reset with
|
1089 |
|
|
// RESET signal, set with some status signal and they are erased with writting '1' into them !!!
|
1090 |
|
|
if (reset)
|
1091 |
|
|
begin
|
1092 |
|
|
/*status_bit15_11 ; status_bit8 ;*/ command_bit8 <= 1'h0 ; command_bit6 <= 1'h0 ; command_bit2_0 <= 3'h0 ;
|
1093 |
|
|
latency_timer <= 8'h00 ; cache_line_size_reg <= 8'h00 ;
|
1094 |
|
|
// ALL pci_base address registers are the same as pci_baX registers !
|
1095 |
|
|
interrupt_line <= 8'h00 ;
|
1096 |
|
|
|
1097 |
|
|
`ifdef HOST
|
1098 |
|
|
`ifdef PCI_IMAGE6 // if PCI bridge is HOST and IMAGE0 is assigned as general image space
|
1099 |
|
|
pci_img_ctrl0_bit2_1 <= 2'h0 ;
|
1100 |
|
|
// pci_ba0_bit31_12 is always a register (never parameter) !!!
|
1101 |
|
|
pci_ba0_bit0 <= 1'h0 ;
|
1102 |
|
|
pci_am0 <= def_pci_image0_addr_map ;
|
1103 |
|
|
pci_ta0 <= 20'h0000_0 ;
|
1104 |
|
|
`endif
|
1105 |
|
|
`endif
|
1106 |
|
|
pci_ba0_bit31_12 <= 20'h0000_0 ;
|
1107 |
|
|
|
1108 |
|
|
pci_img_ctrl1_bit2_1 <= 2'h0 ;
|
1109 |
|
|
pci_ba1_bit31_12 <= 20'h0000_0 ; pci_ba1_bit0 <= 1'h0 ;
|
1110 |
|
|
pci_am1 <= def_pci_image1_addr_map ;
|
1111 |
|
|
pci_ta1 <= 20'h0000_0 ;
|
1112 |
|
|
`ifdef PCI_IMAGE2
|
1113 |
|
|
pci_img_ctrl2_bit2_1 <= 2'h0 ;
|
1114 |
|
|
pci_ba2_bit31_12 <= 20'h0000_0 ; pci_ba2_bit0 <= 1'h0 ;
|
1115 |
|
|
pci_am2 <= def_pci_image2_addr_map ;
|
1116 |
|
|
pci_ta2 <= 20'h0000_0 ;
|
1117 |
|
|
`endif
|
1118 |
|
|
`ifdef PCI_IMAGE3
|
1119 |
|
|
pci_img_ctrl2_bit2_1 <= 2'h0 ;
|
1120 |
|
|
pci_ba2_bit31_12 <= 20'h0000_0 ; pci_ba2_bit0 <= 1'h0 ;
|
1121 |
|
|
pci_am2 <= def_pci_image2_addr_map ;
|
1122 |
|
|
pci_ta2 <= 20'h0000_0 ;
|
1123 |
|
|
pci_img_ctrl3_bit2_1 <= 2'h0 ;
|
1124 |
|
|
pci_ba3_bit31_12 <= 20'h0000_0 ; pci_ba3_bit0 <= 1'h0 ;
|
1125 |
|
|
pci_am3 <= def_pci_image3_addr_map ;
|
1126 |
|
|
pci_ta3 <= 20'h0000_0 ;
|
1127 |
|
|
`endif
|
1128 |
|
|
`ifdef PCI_IMAGE4
|
1129 |
|
|
pci_img_ctrl2_bit2_1 <= 2'h0 ;
|
1130 |
|
|
pci_ba2_bit31_12 <= 20'h0000_0 ; pci_ba2_bit0 <= 1'h0 ;
|
1131 |
|
|
pci_am2 <= def_pci_image2_addr_map ;
|
1132 |
|
|
pci_ta2 <= 20'h0000_0 ;
|
1133 |
|
|
pci_img_ctrl3_bit2_1 <= 2'h0 ;
|
1134 |
|
|
pci_ba3_bit31_12 <= 20'h0000_0 ; pci_ba3_bit0 <= 1'h0 ;
|
1135 |
|
|
pci_am3 <= def_pci_image3_addr_map ;
|
1136 |
|
|
pci_ta3 <= 20'h0000_0 ;
|
1137 |
|
|
pci_img_ctrl4_bit2_1 <= 2'h0 ;
|
1138 |
|
|
pci_ba4_bit31_12 <= 20'h0000_0 ; pci_ba4_bit0 <= 1'h0 ;
|
1139 |
|
|
pci_am4 <= def_pci_image4_addr_map ;
|
1140 |
|
|
pci_ta4 <= 20'h0000_0 ;
|
1141 |
|
|
`endif
|
1142 |
|
|
`ifdef PCI_IMAGE5
|
1143 |
|
|
pci_img_ctrl2_bit2_1 <= 2'h0 ;
|
1144 |
|
|
pci_ba2_bit31_12 <= 20'h0000_0 ; pci_ba2_bit0 <= 1'h0 ;
|
1145 |
|
|
pci_am2 <= def_pci_image2_addr_map ;
|
1146 |
|
|
pci_ta2 <= 20'h0000_0 ;
|
1147 |
|
|
pci_img_ctrl3_bit2_1 <= 2'h0 ;
|
1148 |
|
|
pci_ba3_bit31_12 <= 20'h0000_0 ; pci_ba3_bit0 <= 1'h0 ;
|
1149 |
|
|
pci_am3 <= def_pci_image3_addr_map ;
|
1150 |
|
|
pci_ta3 <= 20'h0000_0 ;
|
1151 |
|
|
pci_img_ctrl4_bit2_1 <= 2'h0 ;
|
1152 |
|
|
pci_ba4_bit31_12 <= 20'h0000_0 ; pci_ba4_bit0 <= 1'h0 ;
|
1153 |
|
|
pci_am4 <= def_pci_image4_addr_map ;
|
1154 |
|
|
pci_ta4 <= 20'h0000_0 ;
|
1155 |
|
|
pci_img_ctrl5_bit2_1 <= 2'h0 ;
|
1156 |
|
|
pci_ba5_bit31_12 <= 20'h0000_0 ; pci_ba5_bit0 <= 1'h0 ;
|
1157 |
|
|
pci_am5 <= def_pci_image5_addr_map ;
|
1158 |
|
|
pci_ta5 <= 20'h0000_0 ;
|
1159 |
|
|
`endif
|
1160 |
|
|
`ifdef PCI_IMAGE6
|
1161 |
|
|
pci_img_ctrl2_bit2_1 <= 2'h0 ;
|
1162 |
|
|
pci_ba2_bit31_12 <= 20'h0000_0 ; pci_ba2_bit0 <= 1'h0 ;
|
1163 |
|
|
pci_am2 <= def_pci_image2_addr_map ;
|
1164 |
|
|
pci_ta2 <= 20'h0000_0 ;
|
1165 |
|
|
pci_img_ctrl3_bit2_1 <= 2'h0 ;
|
1166 |
|
|
pci_ba3_bit31_12 <= 20'h0000_0 ; pci_ba3_bit0 <= 1'h0 ;
|
1167 |
|
|
pci_am3 <= def_pci_image3_addr_map ;
|
1168 |
|
|
pci_ta3 <= 20'h0000_0 ;
|
1169 |
|
|
pci_img_ctrl4_bit2_1 <= 2'h0 ;
|
1170 |
|
|
pci_ba4_bit31_12 <= 20'h0000_0 ; pci_ba4_bit0 <= 1'h0 ;
|
1171 |
|
|
pci_am4 <= def_pci_image4_addr_map ;
|
1172 |
|
|
pci_ta4 <= 20'h0000_0 ;
|
1173 |
|
|
pci_img_ctrl5_bit2_1 <= 2'h0 ;
|
1174 |
|
|
pci_ba5_bit31_12 <= 20'h0000_0 ; pci_ba5_bit0 <= 1'h0 ;
|
1175 |
|
|
pci_am5 <= def_pci_image5_addr_map ;
|
1176 |
|
|
pci_ta5 <= 20'h0000_0 ;
|
1177 |
|
|
`endif
|
1178 |
|
|
/*pci_err_cs_bit31_24 ; pci_err_cs_bit10 ; pci_err_cs_bit8 ;*/ pci_err_cs_bit0 <= 1'h0 ;
|
1179 |
|
|
/*pci_err_addr ;*/
|
1180 |
|
|
/*pci_err_data ;*/
|
1181 |
|
|
//
|
1182 |
|
|
wb_img_ctrl1_bit2_0 <= 3'h0 ;
|
1183 |
|
|
wb_ba1_bit31_12 <= 20'h0000_0 ; wb_ba1_bit0 <= 1'h0 ;
|
1184 |
|
|
wb_am1 <= def_wb_image1_addr_map ;
|
1185 |
|
|
wb_ta1 <= 20'h0000_0 ;
|
1186 |
|
|
`ifdef WB_IMAGE2
|
1187 |
|
|
wb_img_ctrl2_bit2_0 <= 3'h0 ;
|
1188 |
|
|
wb_ba2_bit31_12 <= 20'h0000_0 ; wb_ba2_bit0 <= 1'h0 ;
|
1189 |
|
|
wb_am2 <= def_wb_image2_addr_map ;
|
1190 |
|
|
wb_ta2 <= 20'h0000_0 ;
|
1191 |
|
|
`endif
|
1192 |
|
|
`ifdef WB_IMAGE3
|
1193 |
|
|
wb_img_ctrl2_bit2_0 <= 3'h0 ;
|
1194 |
|
|
wb_ba2_bit31_12 <= 20'h0000_0 ; wb_ba2_bit0 <= 1'h0 ;
|
1195 |
|
|
wb_am2 <= def_wb_image2_addr_map ;
|
1196 |
|
|
wb_ta2 <= 20'h0000_0 ;
|
1197 |
|
|
wb_img_ctrl3_bit2_0 <= 3'h0 ;
|
1198 |
|
|
wb_ba3_bit31_12 <= 20'h0000_0 ; wb_ba3_bit0 <= 1'h0 ;
|
1199 |
|
|
wb_am3 <= def_wb_image3_addr_map ;
|
1200 |
|
|
wb_ta3 <= 20'h0000_0 ;
|
1201 |
|
|
`endif
|
1202 |
|
|
`ifdef WB_IMAGE4
|
1203 |
|
|
wb_img_ctrl2_bit2_0 <= 3'h0 ;
|
1204 |
|
|
wb_ba2_bit31_12 <= 20'h0000_0 ; wb_ba2_bit0 <= 1'h0 ;
|
1205 |
|
|
wb_am2 <= def_wb_image2_addr_map ;
|
1206 |
|
|
wb_ta2 <= 20'h0000_0 ;
|
1207 |
|
|
wb_img_ctrl3_bit2_0 <= 3'h0 ;
|
1208 |
|
|
wb_ba3_bit31_12 <= 20'h0000_0 ; wb_ba3_bit0 <= 1'h0 ;
|
1209 |
|
|
wb_am3 <= def_wb_image3_addr_map ;
|
1210 |
|
|
wb_ta3 <= 20'h0000_0 ;
|
1211 |
|
|
wb_img_ctrl4_bit2_0 <= 3'h0 ;
|
1212 |
|
|
wb_ba4_bit31_12 <= 20'h0000_0 ; wb_ba4_bit0 <= 1'h0 ;
|
1213 |
|
|
wb_am4 <= def_wb_image4_addr_map ;
|
1214 |
|
|
wb_ta4 <= 20'h0000_0 ;
|
1215 |
|
|
`endif
|
1216 |
|
|
`ifdef WB_IMAGE5
|
1217 |
|
|
wb_img_ctrl2_bit2_0 <= 3'h0 ;
|
1218 |
|
|
wb_ba2_bit31_12 <= 20'h0000_0 ; wb_ba2_bit0 <= 1'h0 ;
|
1219 |
|
|
wb_am2 <= def_wb_image2_addr_map ;
|
1220 |
|
|
wb_ta2 <= 20'h0000_0 ;
|
1221 |
|
|
wb_img_ctrl3_bit2_0 <= 3'h0 ;
|
1222 |
|
|
wb_ba3_bit31_12 <= 20'h0000_0 ; wb_ba3_bit0 <= 1'h0 ;
|
1223 |
|
|
wb_am3 <= def_wb_image3_addr_map ;
|
1224 |
|
|
wb_ta3 <= 20'h0000_0 ;
|
1225 |
|
|
wb_img_ctrl4_bit2_0 <= 3'h0 ;
|
1226 |
|
|
wb_ba4_bit31_12 <= 20'h0000_0 ; wb_ba4_bit0 <= 1'h0 ;
|
1227 |
|
|
wb_am4 <= def_wb_image4_addr_map ;
|
1228 |
|
|
wb_ta4 <= 20'h0000_0 ;
|
1229 |
|
|
wb_img_ctrl5_bit2_0 <= 3'h0 ;
|
1230 |
|
|
wb_ba5_bit31_12 <= 20'h0000_0 ; wb_ba5_bit0 <= 1'h0 ;
|
1231 |
|
|
wb_am5 <= def_wb_image5_addr_map ;
|
1232 |
|
|
wb_ta5 <= 20'h0000_0 ;
|
1233 |
|
|
`endif
|
1234 |
|
|
/*wb_err_cs_bit31_24 ; wb_err_cs_bit10_8 ;*/ wb_err_cs_bit0 <= 1'h0 ;
|
1235 |
|
|
/*wb_err_addr ;*/
|
1236 |
|
|
/*wb_err_data ;*/
|
1237 |
|
|
|
1238 |
|
|
cnf_addr_bit23_2 <= 22'h0000_00 ; cnf_addr_bit0 <= 1'h0 ;
|
1239 |
|
|
icr_bit31 <= 1'h0 ; icr_bit3_0 <= 4'h0 ;
|
1240 |
|
|
/*isr_bit3_0 ;*/
|
1241 |
|
|
end
|
1242 |
|
|
/* -----------------------------------------------------------------------------------------------------------
|
1243 |
|
|
Following register bits should have asynchronous RESET & SET! That is why they are IMPLEMENTED separately
|
1244 |
|
|
after this ALWAYS block!!! (for every register bit, there are two D-FF implemented)
|
1245 |
|
|
status_bit15_11[15] <= 1'b1 ;
|
1246 |
|
|
status_bit15_11[14] <= 1'b1 ;
|
1247 |
|
|
status_bit15_11[13] <= 1'b1 ;
|
1248 |
|
|
status_bit15_11[12] <= 1'b1 ;
|
1249 |
|
|
status_bit15_11[11] <= 1'b1 ;
|
1250 |
|
|
status_bit8 <= 1'b1 ;
|
1251 |
|
|
pci_err_cs_bit10 <= 1'b1 ;
|
1252 |
|
|
pci_err_cs_bit8 <= 1'b1 ;
|
1253 |
|
|
pci_err_cs_bit31_24 <= { pci_error_be, pci_error_bc } ;
|
1254 |
|
|
pci_err_addr <= pci_error_addr ;
|
1255 |
|
|
pci_err_data <= pci_error_data ;
|
1256 |
|
|
wb_err_cs_bit10_8[10] <= 1'b1 ;
|
1257 |
|
|
wb_err_cs_bit10_8[9] <= 1'b1 ;
|
1258 |
|
|
wb_err_cs_bit10_8[8] <= 1'b1 ;
|
1259 |
|
|
wb_err_cs_bit31_24 <= { wb_error_be, wb_error_bc } ;
|
1260 |
|
|
wb_err_addr <= wb_error_addr ;
|
1261 |
|
|
wb_err_data <= wb_error_data ;
|
1262 |
|
|
isr_bit3_0[3] <= 1'b1 & icr_bit3_0[3] ;
|
1263 |
|
|
isr_bit3_0[2] <= 1'b1 & icr_bit3_0[2] ;
|
1264 |
|
|
isr_bit3_0[1] <= 1'b1 & icr_bit3_0[1] ;
|
1265 |
|
|
isr_bit3_0[0] <= 1'b1 & icr_bit3_0[0] ;
|
1266 |
|
|
-----------------------------------------------------------------------------------------------------------*/
|
1267 |
|
|
// Here follows normal writting to registers (only to their valid bits) !
|
1268 |
|
|
else
|
1269 |
|
|
begin
|
1270 |
|
|
if (w_we == 1'b1)
|
1271 |
|
|
begin
|
1272 |
|
|
case (w_conf_address_in[8])
|
1273 |
|
|
1'b0 :
|
1274 |
|
|
begin
|
1275 |
|
|
case ({w_conf_address_in[7], w_conf_address_in[6]})
|
1276 |
|
|
2'b00 :
|
1277 |
|
|
begin
|
1278 |
|
|
// PCI header - configuration space
|
1279 |
|
|
case (w_conf_address_in[5:2])
|
1280 |
|
|
4'h1:
|
1281 |
|
|
begin
|
1282 |
|
|
if (w_byte_en[1] == 1'b0)
|
1283 |
|
|
command_bit8 <= #`FF_DELAY w_conf_data_in[8] ;
|
1284 |
|
|
if (w_byte_en[0] == 1'b0)
|
1285 |
|
|
begin
|
1286 |
|
|
command_bit6 <= #`FF_DELAY w_conf_data_in[6] ;
|
1287 |
|
|
command_bit2_0 <= #`FF_DELAY w_conf_data_in[2:0] ;
|
1288 |
|
|
end
|
1289 |
|
|
end
|
1290 |
|
|
4'h3:
|
1291 |
|
|
begin
|
1292 |
|
|
if (w_byte_en[1] == 1'b0)
|
1293 |
|
|
latency_timer <= #`FF_DELAY w_conf_data_in[15:8] ;
|
1294 |
|
|
if (w_byte_en[0] == 1'b0)
|
1295 |
|
|
cache_line_size_reg <= #`FF_DELAY w_conf_data_in[7:0] ;
|
1296 |
|
|
end
|
1297 |
|
|
4'h4:
|
1298 |
|
|
begin
|
1299 |
|
|
if (w_byte_en[3] == 1'b0)
|
1300 |
|
|
pci_ba0_bit31_12[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1301 |
|
|
if (w_byte_en[2] == 1'b0)
|
1302 |
|
|
pci_ba0_bit31_12[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1303 |
|
|
if (w_byte_en[1] == 1'b0)
|
1304 |
|
|
pci_ba0_bit31_12[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1305 |
|
|
end
|
1306 |
|
|
4'h5:
|
1307 |
|
|
begin
|
1308 |
|
|
if (w_byte_en[3] == 1'b0)
|
1309 |
|
|
pci_ba1_bit31_12[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1310 |
|
|
if (w_byte_en[2] == 1'b0)
|
1311 |
|
|
pci_ba1_bit31_12[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1312 |
|
|
if (w_byte_en[1] == 1'b0)
|
1313 |
|
|
pci_ba1_bit31_12[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1314 |
|
|
if (w_byte_en[0] == 1'b0)
|
1315 |
|
|
pci_ba1_bit0 <= #`FF_DELAY w_conf_data_in[0] ;
|
1316 |
|
|
end
|
1317 |
|
|
`ifdef PCI_IMAGE2
|
1318 |
|
|
4'h6:
|
1319 |
|
|
begin
|
1320 |
|
|
if (w_byte_en[3] == 1'b0)
|
1321 |
|
|
pci_ba2_bit31_12[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1322 |
|
|
if (w_byte_en[2] == 1'b0)
|
1323 |
|
|
pci_ba2_bit31_12[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1324 |
|
|
if (w_byte_en[1] == 1'b0)
|
1325 |
|
|
pci_ba2_bit31_12[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1326 |
|
|
if (w_byte_en[0] == 1'b0)
|
1327 |
|
|
pci_ba2_bit0 <= #`FF_DELAY w_conf_data_in[0] ;
|
1328 |
|
|
end
|
1329 |
|
|
`endif
|
1330 |
|
|
`ifdef PCI_IMAGE3
|
1331 |
|
|
4'h6:
|
1332 |
|
|
begin
|
1333 |
|
|
if (w_byte_en[3] == 1'b0)
|
1334 |
|
|
pci_ba2_bit31_12[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1335 |
|
|
if (w_byte_en[2] == 1'b0)
|
1336 |
|
|
pci_ba2_bit31_12[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1337 |
|
|
if (w_byte_en[1] == 1'b0)
|
1338 |
|
|
pci_ba2_bit31_12[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1339 |
|
|
if (w_byte_en[0] == 1'b0)
|
1340 |
|
|
pci_ba2_bit0 <= #`FF_DELAY w_conf_data_in[0] ;
|
1341 |
|
|
end
|
1342 |
|
|
4'h7:
|
1343 |
|
|
begin
|
1344 |
|
|
if (w_byte_en[3] == 1'b0)
|
1345 |
|
|
pci_ba3_bit31_12[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1346 |
|
|
if (w_byte_en[2] == 1'b0)
|
1347 |
|
|
pci_ba3_bit31_12[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1348 |
|
|
if (w_byte_en[1] == 1'b0)
|
1349 |
|
|
pci_ba3_bit31_12[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1350 |
|
|
if (w_byte_en[0] == 1'b0)
|
1351 |
|
|
pci_ba3_bit0 <= #`FF_DELAY w_conf_data_in[0] ;
|
1352 |
|
|
end
|
1353 |
|
|
`endif
|
1354 |
|
|
`ifdef PCI_IMAGE4
|
1355 |
|
|
4'h6:
|
1356 |
|
|
begin
|
1357 |
|
|
if (w_byte_en[3] == 1'b0)
|
1358 |
|
|
pci_ba2_bit31_12[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1359 |
|
|
if (w_byte_en[2] == 1'b0)
|
1360 |
|
|
pci_ba2_bit31_12[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1361 |
|
|
if (w_byte_en[1] == 1'b0)
|
1362 |
|
|
pci_ba2_bit31_12[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1363 |
|
|
if (w_byte_en[0] == 1'b0)
|
1364 |
|
|
pci_ba2_bit0 <= #`FF_DELAY w_conf_data_in[0] ;
|
1365 |
|
|
end
|
1366 |
|
|
4'h7:
|
1367 |
|
|
begin
|
1368 |
|
|
if (w_byte_en[3] == 1'b0)
|
1369 |
|
|
pci_ba3_bit31_12[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1370 |
|
|
if (w_byte_en[2] == 1'b0)
|
1371 |
|
|
pci_ba3_bit31_12[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1372 |
|
|
if (w_byte_en[1] == 1'b0)
|
1373 |
|
|
pci_ba3_bit31_12[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1374 |
|
|
if (w_byte_en[0] == 1'b0)
|
1375 |
|
|
pci_ba3_bit0 <= #`FF_DELAY w_conf_data_in[0] ;
|
1376 |
|
|
end
|
1377 |
|
|
4'h8:
|
1378 |
|
|
begin
|
1379 |
|
|
if (w_byte_en[3] == 1'b0)
|
1380 |
|
|
pci_ba4_bit31_12[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1381 |
|
|
if (w_byte_en[2] == 1'b0)
|
1382 |
|
|
pci_ba4_bit31_12[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1383 |
|
|
if (w_byte_en[1] == 1'b0)
|
1384 |
|
|
pci_ba4_bit31_12[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1385 |
|
|
if (w_byte_en[0] == 1'b0)
|
1386 |
|
|
pci_ba4_bit0 <= #`FF_DELAY w_conf_data_in[0] ;
|
1387 |
|
|
end
|
1388 |
|
|
`endif
|
1389 |
|
|
`ifdef PCI_IMAGE5
|
1390 |
|
|
4'h6:
|
1391 |
|
|
begin
|
1392 |
|
|
if (w_byte_en[3] == 1'b0)
|
1393 |
|
|
pci_ba2_bit31_12[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1394 |
|
|
if (w_byte_en[2] == 1'b0)
|
1395 |
|
|
pci_ba2_bit31_12[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1396 |
|
|
if (w_byte_en[1] == 1'b0)
|
1397 |
|
|
pci_ba2_bit31_12[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1398 |
|
|
if (w_byte_en[0] == 1'b0)
|
1399 |
|
|
pci_ba2_bit0 <= #`FF_DELAY w_conf_data_in[0] ;
|
1400 |
|
|
end
|
1401 |
|
|
4'h7:
|
1402 |
|
|
begin
|
1403 |
|
|
if (w_byte_en[3] == 1'b0)
|
1404 |
|
|
pci_ba3_bit31_12[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1405 |
|
|
if (w_byte_en[2] == 1'b0)
|
1406 |
|
|
pci_ba3_bit31_12[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1407 |
|
|
if (w_byte_en[1] == 1'b0)
|
1408 |
|
|
pci_ba3_bit31_12[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1409 |
|
|
if (w_byte_en[0] == 1'b0)
|
1410 |
|
|
pci_ba3_bit0 <= #`FF_DELAY w_conf_data_in[0] ;
|
1411 |
|
|
end
|
1412 |
|
|
4'h8:
|
1413 |
|
|
begin
|
1414 |
|
|
if (w_byte_en[3] == 1'b0)
|
1415 |
|
|
pci_ba4_bit31_12[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1416 |
|
|
if (w_byte_en[2] == 1'b0)
|
1417 |
|
|
pci_ba4_bit31_12[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1418 |
|
|
if (w_byte_en[1] == 1'b0)
|
1419 |
|
|
pci_ba4_bit31_12[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1420 |
|
|
if (w_byte_en[0] == 1'b0)
|
1421 |
|
|
pci_ba4_bit0 <= #`FF_DELAY w_conf_data_in[0] ;
|
1422 |
|
|
end
|
1423 |
|
|
4'h9:
|
1424 |
|
|
begin
|
1425 |
|
|
if (w_byte_en[3] == 1'b0)
|
1426 |
|
|
pci_ba5_bit31_12[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1427 |
|
|
if (w_byte_en[2] == 1'b0)
|
1428 |
|
|
pci_ba5_bit31_12[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1429 |
|
|
if (w_byte_en[1] == 1'b0)
|
1430 |
|
|
pci_ba5_bit31_12[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1431 |
|
|
if (w_byte_en[0] == 1'b0)
|
1432 |
|
|
pci_ba5_bit0 <= #`FF_DELAY w_conf_data_in[0] ;
|
1433 |
|
|
end
|
1434 |
|
|
`endif
|
1435 |
|
|
`ifdef PCI_IMAGE6
|
1436 |
|
|
4'h6:
|
1437 |
|
|
begin
|
1438 |
|
|
if (w_byte_en[3] == 1'b0)
|
1439 |
|
|
pci_ba2_bit31_12[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1440 |
|
|
if (w_byte_en[2] == 1'b0)
|
1441 |
|
|
pci_ba2_bit31_12[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1442 |
|
|
if (w_byte_en[1] == 1'b0)
|
1443 |
|
|
pci_ba2_bit31_12[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1444 |
|
|
if (w_byte_en[0] == 1'b0)
|
1445 |
|
|
pci_ba2_bit0 <= #`FF_DELAY w_conf_data_in[0] ;
|
1446 |
|
|
end
|
1447 |
|
|
4'h7:
|
1448 |
|
|
begin
|
1449 |
|
|
if (w_byte_en[3] == 1'b0)
|
1450 |
|
|
pci_ba3_bit31_12[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1451 |
|
|
if (w_byte_en[2] == 1'b0)
|
1452 |
|
|
pci_ba3_bit31_12[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1453 |
|
|
if (w_byte_en[1] == 1'b0)
|
1454 |
|
|
pci_ba3_bit31_12[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1455 |
|
|
if (w_byte_en[0] == 1'b0)
|
1456 |
|
|
pci_ba3_bit0 <= #`FF_DELAY w_conf_data_in[0] ;
|
1457 |
|
|
end
|
1458 |
|
|
4'h8:
|
1459 |
|
|
begin
|
1460 |
|
|
if (w_byte_en[3] == 1'b0)
|
1461 |
|
|
pci_ba4_bit31_12[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1462 |
|
|
if (w_byte_en[2] == 1'b0)
|
1463 |
|
|
pci_ba4_bit31_12[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1464 |
|
|
if (w_byte_en[1] == 1'b0)
|
1465 |
|
|
pci_ba4_bit31_12[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1466 |
|
|
if (w_byte_en[0] == 1'b0)
|
1467 |
|
|
pci_ba4_bit0 <= #`FF_DELAY w_conf_data_in[0] ;
|
1468 |
|
|
end
|
1469 |
|
|
4'h9:
|
1470 |
|
|
begin
|
1471 |
|
|
if (w_byte_en[3] == 1'b0)
|
1472 |
|
|
pci_ba5_bit31_12[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1473 |
|
|
if (w_byte_en[2] == 1'b0)
|
1474 |
|
|
pci_ba5_bit31_12[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1475 |
|
|
if (w_byte_en[1] == 1'b0)
|
1476 |
|
|
pci_ba5_bit31_12[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1477 |
|
|
if (w_byte_en[0] == 1'b0)
|
1478 |
|
|
pci_ba5_bit0 <= #`FF_DELAY w_conf_data_in[0] ;
|
1479 |
|
|
end
|
1480 |
|
|
`endif
|
1481 |
|
|
4'hf:
|
1482 |
|
|
begin
|
1483 |
|
|
if (w_byte_en[0] == 1'b0)
|
1484 |
|
|
interrupt_line <= #`FF_DELAY w_conf_data_in[7:0] ;
|
1485 |
|
|
end
|
1486 |
|
|
default :
|
1487 |
|
|
begin
|
1488 |
|
|
end
|
1489 |
|
|
endcase
|
1490 |
|
|
end
|
1491 |
|
|
default :
|
1492 |
|
|
begin
|
1493 |
|
|
end
|
1494 |
|
|
endcase
|
1495 |
|
|
end
|
1496 |
|
|
default :
|
1497 |
|
|
begin
|
1498 |
|
|
// PCI target - configuration space
|
1499 |
|
|
case (w_conf_address_in[7:2])
|
1500 |
|
|
`ifdef HOST
|
1501 |
|
|
`ifdef PCI_IMAGE6 // if PCI bridge is HOST and IMAGE0 is assigned as general image space
|
1502 |
|
|
`P_IMG_CTRL0_ADDR:
|
1503 |
|
|
begin
|
1504 |
|
|
if (w_byte_en[0] == 1'b0)
|
1505 |
|
|
pci_img_ctrl0_bit2_1 <= #`FF_DELAY w_conf_data_in[2:1] ;
|
1506 |
|
|
end
|
1507 |
|
|
`endif
|
1508 |
|
|
`endif
|
1509 |
|
|
// pci_ba0_bit31_12 & pci_ba0_bit0 are always registers (never parameters) !!!
|
1510 |
|
|
`P_BA0_ADDR:
|
1511 |
|
|
begin
|
1512 |
|
|
if (w_byte_en[3] == 1'b0)
|
1513 |
|
|
pci_ba0_bit31_12[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1514 |
|
|
if (w_byte_en[2] == 1'b0)
|
1515 |
|
|
pci_ba0_bit31_12[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1516 |
|
|
if (w_byte_en[1] == 1'b0)
|
1517 |
|
|
pci_ba0_bit31_12[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1518 |
|
|
`ifdef HOST
|
1519 |
|
|
`ifdef PCI_IMAGE6 // if PCI bridge is HOST and IMAGE0 is assigned as general image space
|
1520 |
|
|
if (w_byte_en[0] == 1'b0)
|
1521 |
|
|
pci_ba0_bit0 <= #`FF_DELAY w_conf_data_in[0] ;
|
1522 |
|
|
`endif
|
1523 |
|
|
`endif
|
1524 |
|
|
end
|
1525 |
|
|
`ifdef HOST
|
1526 |
|
|
`ifdef PCI_IMAGE6 // if PCI bridge is HOST and IMAGE0 is assigned as general image space
|
1527 |
|
|
`P_AM0_ADDR:
|
1528 |
|
|
begin
|
1529 |
|
|
if (w_byte_en[3] == 1'b0)
|
1530 |
|
|
pci_am0[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1531 |
|
|
if (w_byte_en[2] == 1'b0)
|
1532 |
|
|
pci_am0[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1533 |
|
|
if (w_byte_en[1] == 1'b0)
|
1534 |
|
|
pci_am0[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1535 |
|
|
end
|
1536 |
|
|
`P_TA0_ADDR:
|
1537 |
|
|
begin
|
1538 |
|
|
if (w_byte_en[3] == 1'b0)
|
1539 |
|
|
pci_ta0[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1540 |
|
|
if (w_byte_en[2] == 1'b0)
|
1541 |
|
|
pci_ta0[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1542 |
|
|
if (w_byte_en[1] == 1'b0)
|
1543 |
|
|
pci_ta0[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1544 |
|
|
end
|
1545 |
|
|
`endif
|
1546 |
|
|
`endif
|
1547 |
|
|
`P_IMG_CTRL1_ADDR:
|
1548 |
|
|
begin
|
1549 |
|
|
if (w_byte_en[0] == 1'b0)
|
1550 |
|
|
pci_img_ctrl1_bit2_1 <= #`FF_DELAY w_conf_data_in[2:1] ;
|
1551 |
|
|
end
|
1552 |
|
|
`P_BA1_ADDR:
|
1553 |
|
|
begin
|
1554 |
|
|
if (w_byte_en[3] == 1'b0)
|
1555 |
|
|
pci_ba1_bit31_12[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1556 |
|
|
if (w_byte_en[2] == 1'b0)
|
1557 |
|
|
pci_ba1_bit31_12[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1558 |
|
|
if (w_byte_en[1] == 1'b0)
|
1559 |
|
|
pci_ba1_bit31_12[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1560 |
|
|
if (w_byte_en[0] == 1'b0)
|
1561 |
|
|
pci_ba1_bit0 <= #`FF_DELAY w_conf_data_in[0] ;
|
1562 |
|
|
end
|
1563 |
|
|
`P_AM1_ADDR:
|
1564 |
|
|
begin
|
1565 |
|
|
if (w_byte_en[3] == 1'b0)
|
1566 |
|
|
pci_am1[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1567 |
|
|
if (w_byte_en[2] == 1'b0)
|
1568 |
|
|
pci_am1[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1569 |
|
|
if (w_byte_en[1] == 1'b0)
|
1570 |
|
|
pci_am1[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1571 |
|
|
end
|
1572 |
|
|
`P_TA1_ADDR:
|
1573 |
|
|
begin
|
1574 |
|
|
if (w_byte_en[3] == 1'b0)
|
1575 |
|
|
pci_ta1[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1576 |
|
|
if (w_byte_en[2] == 1'b0)
|
1577 |
|
|
pci_ta1[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1578 |
|
|
if (w_byte_en[1] == 1'b0)
|
1579 |
|
|
pci_ta1[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1580 |
|
|
end
|
1581 |
|
|
`ifdef PCI_IMAGE2
|
1582 |
|
|
`P_IMG_CTRL2_ADDR:
|
1583 |
|
|
begin
|
1584 |
|
|
if (w_byte_en[0] == 1'b0)
|
1585 |
|
|
pci_img_ctrl2_bit2_1 <= #`FF_DELAY w_conf_data_in[2:1] ;
|
1586 |
|
|
end
|
1587 |
|
|
`P_BA2_ADDR:
|
1588 |
|
|
begin
|
1589 |
|
|
if (w_byte_en[3] == 1'b0)
|
1590 |
|
|
pci_ba2_bit31_12[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1591 |
|
|
if (w_byte_en[2] == 1'b0)
|
1592 |
|
|
pci_ba2_bit31_12[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1593 |
|
|
if (w_byte_en[1] == 1'b0)
|
1594 |
|
|
pci_ba2_bit31_12[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1595 |
|
|
if (w_byte_en[0] == 1'b0)
|
1596 |
|
|
pci_ba2_bit0 <= #`FF_DELAY w_conf_data_in[0] ;
|
1597 |
|
|
end
|
1598 |
|
|
`P_AM2_ADDR:
|
1599 |
|
|
begin
|
1600 |
|
|
if (w_byte_en[3] == 1'b0)
|
1601 |
|
|
pci_am2[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1602 |
|
|
if (w_byte_en[2] == 1'b0)
|
1603 |
|
|
pci_am2[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1604 |
|
|
if (w_byte_en[1] == 1'b0)
|
1605 |
|
|
pci_am2[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1606 |
|
|
end
|
1607 |
|
|
`P_TA2_ADDR:
|
1608 |
|
|
begin
|
1609 |
|
|
if (w_byte_en[3] == 1'b0)
|
1610 |
|
|
pci_ta2[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1611 |
|
|
if (w_byte_en[2] == 1'b0)
|
1612 |
|
|
pci_ta2[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1613 |
|
|
if (w_byte_en[1] == 1'b0)
|
1614 |
|
|
pci_ta2[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1615 |
|
|
end
|
1616 |
|
|
`endif
|
1617 |
|
|
`ifdef PCI_IMAGE3
|
1618 |
|
|
`P_IMG_CTRL2_ADDR:
|
1619 |
|
|
begin
|
1620 |
|
|
if (w_byte_en[0] == 1'b0)
|
1621 |
|
|
pci_img_ctrl2_bit2_1 <= #`FF_DELAY w_conf_data_in[2:1] ;
|
1622 |
|
|
end
|
1623 |
|
|
`P_BA2_ADDR:
|
1624 |
|
|
begin
|
1625 |
|
|
if (w_byte_en[3] == 1'b0)
|
1626 |
|
|
pci_ba2_bit31_12[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1627 |
|
|
if (w_byte_en[2] == 1'b0)
|
1628 |
|
|
pci_ba2_bit31_12[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1629 |
|
|
if (w_byte_en[1] == 1'b0)
|
1630 |
|
|
pci_ba2_bit31_12[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1631 |
|
|
if (w_byte_en[0] == 1'b0)
|
1632 |
|
|
pci_ba2_bit0 <= #`FF_DELAY w_conf_data_in[0] ;
|
1633 |
|
|
end
|
1634 |
|
|
`P_AM2_ADDR:
|
1635 |
|
|
begin
|
1636 |
|
|
if (w_byte_en[3] == 1'b0)
|
1637 |
|
|
pci_am2[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1638 |
|
|
if (w_byte_en[2] == 1'b0)
|
1639 |
|
|
pci_am2[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1640 |
|
|
if (w_byte_en[1] == 1'b0)
|
1641 |
|
|
pci_am2[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1642 |
|
|
end
|
1643 |
|
|
`P_TA2_ADDR:
|
1644 |
|
|
begin
|
1645 |
|
|
if (w_byte_en[3] == 1'b0)
|
1646 |
|
|
pci_ta2[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1647 |
|
|
if (w_byte_en[2] == 1'b0)
|
1648 |
|
|
pci_ta2[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1649 |
|
|
if (w_byte_en[1] == 1'b0)
|
1650 |
|
|
pci_ta2[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1651 |
|
|
end
|
1652 |
|
|
`P_IMG_CTRL3_ADDR:
|
1653 |
|
|
begin
|
1654 |
|
|
if (w_byte_en[0] == 1'b0)
|
1655 |
|
|
pci_img_ctrl3_bit2_1 <= #`FF_DELAY w_conf_data_in[2:1] ;
|
1656 |
|
|
end
|
1657 |
|
|
`P_BA3_ADDR:
|
1658 |
|
|
begin
|
1659 |
|
|
if (w_byte_en[3] == 1'b0)
|
1660 |
|
|
pci_ba3_bit31_12[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1661 |
|
|
if (w_byte_en[2] == 1'b0)
|
1662 |
|
|
pci_ba3_bit31_12[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1663 |
|
|
if (w_byte_en[1] == 1'b0)
|
1664 |
|
|
pci_ba3_bit31_12[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1665 |
|
|
if (w_byte_en[0] == 1'b0)
|
1666 |
|
|
pci_ba3_bit0 <= #`FF_DELAY w_conf_data_in[0] ;
|
1667 |
|
|
end
|
1668 |
|
|
`P_AM3_ADDR:
|
1669 |
|
|
begin
|
1670 |
|
|
if (w_byte_en[3] == 1'b0)
|
1671 |
|
|
pci_am3[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1672 |
|
|
if (w_byte_en[2] == 1'b0)
|
1673 |
|
|
pci_am3[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1674 |
|
|
if (w_byte_en[1] == 1'b0)
|
1675 |
|
|
pci_am3[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1676 |
|
|
end
|
1677 |
|
|
`P_TA3_ADDR:
|
1678 |
|
|
begin
|
1679 |
|
|
if (w_byte_en[3] == 1'b0)
|
1680 |
|
|
pci_ta3[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1681 |
|
|
if (w_byte_en[2] == 1'b0)
|
1682 |
|
|
pci_ta3[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1683 |
|
|
if (w_byte_en[1] == 1'b0)
|
1684 |
|
|
pci_ta3[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1685 |
|
|
end
|
1686 |
|
|
`endif
|
1687 |
|
|
`ifdef PCI_IMAGE4
|
1688 |
|
|
`P_IMG_CTRL2_ADDR:
|
1689 |
|
|
begin
|
1690 |
|
|
if (w_byte_en[0] == 1'b0)
|
1691 |
|
|
pci_img_ctrl2_bit2_1 <= #`FF_DELAY w_conf_data_in[2:1] ;
|
1692 |
|
|
end
|
1693 |
|
|
`P_BA2_ADDR:
|
1694 |
|
|
begin
|
1695 |
|
|
if (w_byte_en[3] == 1'b0)
|
1696 |
|
|
pci_ba2_bit31_12[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1697 |
|
|
if (w_byte_en[2] == 1'b0)
|
1698 |
|
|
pci_ba2_bit31_12[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1699 |
|
|
if (w_byte_en[1] == 1'b0)
|
1700 |
|
|
pci_ba2_bit31_12[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1701 |
|
|
if (w_byte_en[0] == 1'b0)
|
1702 |
|
|
pci_ba2_bit0 <= #`FF_DELAY w_conf_data_in[0] ;
|
1703 |
|
|
end
|
1704 |
|
|
`P_AM2_ADDR:
|
1705 |
|
|
begin
|
1706 |
|
|
if (w_byte_en[3] == 1'b0)
|
1707 |
|
|
pci_am2[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1708 |
|
|
if (w_byte_en[2] == 1'b0)
|
1709 |
|
|
pci_am2[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1710 |
|
|
if (w_byte_en[1] == 1'b0)
|
1711 |
|
|
pci_am2[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1712 |
|
|
end
|
1713 |
|
|
`P_TA2_ADDR:
|
1714 |
|
|
begin
|
1715 |
|
|
if (w_byte_en[3] == 1'b0)
|
1716 |
|
|
pci_ta2[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1717 |
|
|
if (w_byte_en[2] == 1'b0)
|
1718 |
|
|
pci_ta2[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1719 |
|
|
if (w_byte_en[1] == 1'b0)
|
1720 |
|
|
pci_ta2[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1721 |
|
|
end
|
1722 |
|
|
`P_IMG_CTRL3_ADDR:
|
1723 |
|
|
begin
|
1724 |
|
|
if (w_byte_en[0] == 1'b0)
|
1725 |
|
|
pci_img_ctrl3_bit2_1 <= #`FF_DELAY w_conf_data_in[2:1] ;
|
1726 |
|
|
end
|
1727 |
|
|
`P_BA3_ADDR:
|
1728 |
|
|
begin
|
1729 |
|
|
if (w_byte_en[3] == 1'b0)
|
1730 |
|
|
pci_ba3_bit31_12[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1731 |
|
|
if (w_byte_en[2] == 1'b0)
|
1732 |
|
|
pci_ba3_bit31_12[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1733 |
|
|
if (w_byte_en[1] == 1'b0)
|
1734 |
|
|
pci_ba3_bit31_12[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1735 |
|
|
if (w_byte_en[0] == 1'b0)
|
1736 |
|
|
pci_ba3_bit0 <= #`FF_DELAY w_conf_data_in[0] ;
|
1737 |
|
|
end
|
1738 |
|
|
`P_AM3_ADDR:
|
1739 |
|
|
begin
|
1740 |
|
|
if (w_byte_en[3] == 1'b0)
|
1741 |
|
|
pci_am3[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1742 |
|
|
if (w_byte_en[2] == 1'b0)
|
1743 |
|
|
pci_am3[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1744 |
|
|
if (w_byte_en[1] == 1'b0)
|
1745 |
|
|
pci_am3[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1746 |
|
|
end
|
1747 |
|
|
`P_TA3_ADDR:
|
1748 |
|
|
begin
|
1749 |
|
|
if (w_byte_en[3] == 1'b0)
|
1750 |
|
|
pci_ta3[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1751 |
|
|
if (w_byte_en[2] == 1'b0)
|
1752 |
|
|
pci_ta3[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1753 |
|
|
if (w_byte_en[1] == 1'b0)
|
1754 |
|
|
pci_ta3[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1755 |
|
|
end
|
1756 |
|
|
`P_IMG_CTRL4_ADDR:
|
1757 |
|
|
begin
|
1758 |
|
|
if (w_byte_en[0] == 1'b0)
|
1759 |
|
|
pci_img_ctrl4_bit2_1 <= #`FF_DELAY w_conf_data_in[2:1] ;
|
1760 |
|
|
end
|
1761 |
|
|
`P_BA4_ADDR:
|
1762 |
|
|
begin
|
1763 |
|
|
if (w_byte_en[3] == 1'b0)
|
1764 |
|
|
pci_ba4_bit31_12[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1765 |
|
|
if (w_byte_en[2] == 1'b0)
|
1766 |
|
|
pci_ba4_bit31_12[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1767 |
|
|
if (w_byte_en[1] == 1'b0)
|
1768 |
|
|
pci_ba4_bit31_12[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1769 |
|
|
if (w_byte_en[0] == 1'b0)
|
1770 |
|
|
pci_ba4_bit0 <= #`FF_DELAY w_conf_data_in[0] ;
|
1771 |
|
|
end
|
1772 |
|
|
`P_AM4_ADDR:
|
1773 |
|
|
begin
|
1774 |
|
|
if (w_byte_en[3] == 1'b0)
|
1775 |
|
|
pci_am4[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1776 |
|
|
if (w_byte_en[2] == 1'b0)
|
1777 |
|
|
pci_am4[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1778 |
|
|
if (w_byte_en[1] == 1'b0)
|
1779 |
|
|
pci_am4[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1780 |
|
|
end
|
1781 |
|
|
`P_TA4_ADDR:
|
1782 |
|
|
begin
|
1783 |
|
|
if (w_byte_en[3] == 1'b0)
|
1784 |
|
|
pci_ta4[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1785 |
|
|
if (w_byte_en[2] == 1'b0)
|
1786 |
|
|
pci_ta4[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1787 |
|
|
if (w_byte_en[1] == 1'b0)
|
1788 |
|
|
pci_ta4[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1789 |
|
|
end
|
1790 |
|
|
`endif
|
1791 |
|
|
`ifdef PCI_IMAGE5
|
1792 |
|
|
`P_IMG_CTRL2_ADDR:
|
1793 |
|
|
begin
|
1794 |
|
|
if (w_byte_en[0] == 1'b0)
|
1795 |
|
|
pci_img_ctrl2_bit2_1 <= #`FF_DELAY w_conf_data_in[2:1] ;
|
1796 |
|
|
end
|
1797 |
|
|
`P_BA2_ADDR:
|
1798 |
|
|
begin
|
1799 |
|
|
if (w_byte_en[3] == 1'b0)
|
1800 |
|
|
pci_ba2_bit31_12[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1801 |
|
|
if (w_byte_en[2] == 1'b0)
|
1802 |
|
|
pci_ba2_bit31_12[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1803 |
|
|
if (w_byte_en[1] == 1'b0)
|
1804 |
|
|
pci_ba2_bit31_12[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1805 |
|
|
if (w_byte_en[0] == 1'b0)
|
1806 |
|
|
pci_ba2_bit0 <= #`FF_DELAY w_conf_data_in[0] ;
|
1807 |
|
|
end
|
1808 |
|
|
`P_AM2_ADDR:
|
1809 |
|
|
begin
|
1810 |
|
|
if (w_byte_en[3] == 1'b0)
|
1811 |
|
|
pci_am2[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1812 |
|
|
if (w_byte_en[2] == 1'b0)
|
1813 |
|
|
pci_am2[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1814 |
|
|
if (w_byte_en[1] == 1'b0)
|
1815 |
|
|
pci_am2[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1816 |
|
|
end
|
1817 |
|
|
`P_TA2_ADDR:
|
1818 |
|
|
begin
|
1819 |
|
|
if (w_byte_en[3] == 1'b0)
|
1820 |
|
|
pci_ta2[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1821 |
|
|
if (w_byte_en[2] == 1'b0)
|
1822 |
|
|
pci_ta2[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1823 |
|
|
if (w_byte_en[1] == 1'b0)
|
1824 |
|
|
pci_ta2[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1825 |
|
|
end
|
1826 |
|
|
`P_IMG_CTRL3_ADDR:
|
1827 |
|
|
begin
|
1828 |
|
|
if (w_byte_en[0] == 1'b0)
|
1829 |
|
|
pci_img_ctrl3_bit2_1 <= #`FF_DELAY w_conf_data_in[2:1] ;
|
1830 |
|
|
end
|
1831 |
|
|
`P_BA3_ADDR:
|
1832 |
|
|
begin
|
1833 |
|
|
if (w_byte_en[3] == 1'b0)
|
1834 |
|
|
pci_ba3_bit31_12[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1835 |
|
|
if (w_byte_en[2] == 1'b0)
|
1836 |
|
|
pci_ba3_bit31_12[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1837 |
|
|
if (w_byte_en[1] == 1'b0)
|
1838 |
|
|
pci_ba3_bit31_12[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1839 |
|
|
if (w_byte_en[0] == 1'b0)
|
1840 |
|
|
pci_ba3_bit0 <= #`FF_DELAY w_conf_data_in[0] ;
|
1841 |
|
|
end
|
1842 |
|
|
`P_AM3_ADDR:
|
1843 |
|
|
begin
|
1844 |
|
|
if (w_byte_en[3] == 1'b0)
|
1845 |
|
|
pci_am3[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1846 |
|
|
if (w_byte_en[2] == 1'b0)
|
1847 |
|
|
pci_am3[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1848 |
|
|
if (w_byte_en[1] == 1'b0)
|
1849 |
|
|
pci_am3[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1850 |
|
|
end
|
1851 |
|
|
`P_TA3_ADDR:
|
1852 |
|
|
begin
|
1853 |
|
|
if (w_byte_en[3] == 1'b0)
|
1854 |
|
|
pci_ta3[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1855 |
|
|
if (w_byte_en[2] == 1'b0)
|
1856 |
|
|
pci_ta3[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1857 |
|
|
if (w_byte_en[1] == 1'b0)
|
1858 |
|
|
pci_ta3[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1859 |
|
|
end
|
1860 |
|
|
`P_IMG_CTRL4_ADDR:
|
1861 |
|
|
begin
|
1862 |
|
|
if (w_byte_en[0] == 1'b0)
|
1863 |
|
|
pci_img_ctrl4_bit2_1 <= #`FF_DELAY w_conf_data_in[2:1] ;
|
1864 |
|
|
end
|
1865 |
|
|
`P_BA4_ADDR:
|
1866 |
|
|
begin
|
1867 |
|
|
if (w_byte_en[3] == 1'b0)
|
1868 |
|
|
pci_ba4_bit31_12[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1869 |
|
|
if (w_byte_en[2] == 1'b0)
|
1870 |
|
|
pci_ba4_bit31_12[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1871 |
|
|
if (w_byte_en[1] == 1'b0)
|
1872 |
|
|
pci_ba4_bit31_12[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1873 |
|
|
if (w_byte_en[0] == 1'b0)
|
1874 |
|
|
pci_ba4_bit0 <= #`FF_DELAY w_conf_data_in[0] ;
|
1875 |
|
|
end
|
1876 |
|
|
`P_AM4_ADDR:
|
1877 |
|
|
begin
|
1878 |
|
|
if (w_byte_en[3] == 1'b0)
|
1879 |
|
|
pci_am4[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1880 |
|
|
if (w_byte_en[2] == 1'b0)
|
1881 |
|
|
pci_am4[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1882 |
|
|
if (w_byte_en[1] == 1'b0)
|
1883 |
|
|
pci_am4[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1884 |
|
|
end
|
1885 |
|
|
`P_TA4_ADDR:
|
1886 |
|
|
begin
|
1887 |
|
|
if (w_byte_en[3] == 1'b0)
|
1888 |
|
|
pci_ta4[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1889 |
|
|
if (w_byte_en[2] == 1'b0)
|
1890 |
|
|
pci_ta4[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1891 |
|
|
if (w_byte_en[1] == 1'b0)
|
1892 |
|
|
pci_ta4[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1893 |
|
|
end
|
1894 |
|
|
`P_IMG_CTRL5_ADDR:
|
1895 |
|
|
begin
|
1896 |
|
|
if (w_byte_en[0] == 1'b0)
|
1897 |
|
|
pci_img_ctrl5_bit2_1 <= #`FF_DELAY w_conf_data_in[2:1] ;
|
1898 |
|
|
end
|
1899 |
|
|
`P_BA5_ADDR:
|
1900 |
|
|
begin
|
1901 |
|
|
if (w_byte_en[3] == 1'b0)
|
1902 |
|
|
pci_ba5_bit31_12[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1903 |
|
|
if (w_byte_en[2] == 1'b0)
|
1904 |
|
|
pci_ba5_bit31_12[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1905 |
|
|
if (w_byte_en[1] == 1'b0)
|
1906 |
|
|
pci_ba5_bit31_12[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1907 |
|
|
if (w_byte_en[0] == 1'b0)
|
1908 |
|
|
pci_ba5_bit0 <= #`FF_DELAY w_conf_data_in[0] ;
|
1909 |
|
|
end
|
1910 |
|
|
`P_AM5_ADDR:
|
1911 |
|
|
begin
|
1912 |
|
|
if (w_byte_en[3] == 1'b0)
|
1913 |
|
|
pci_am5[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1914 |
|
|
if (w_byte_en[2] == 1'b0)
|
1915 |
|
|
pci_am5[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1916 |
|
|
if (w_byte_en[1] == 1'b0)
|
1917 |
|
|
pci_am5[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1918 |
|
|
end
|
1919 |
|
|
`P_TA5_ADDR:
|
1920 |
|
|
begin
|
1921 |
|
|
if (w_byte_en[3] == 1'b0)
|
1922 |
|
|
pci_ta5[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1923 |
|
|
if (w_byte_en[2] == 1'b0)
|
1924 |
|
|
pci_ta5[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1925 |
|
|
if (w_byte_en[1] == 1'b0)
|
1926 |
|
|
pci_ta5[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1927 |
|
|
end
|
1928 |
|
|
`endif
|
1929 |
|
|
`ifdef PCI_IMAGE6
|
1930 |
|
|
`P_IMG_CTRL2_ADDR:
|
1931 |
|
|
begin
|
1932 |
|
|
if (w_byte_en[0] == 1'b0)
|
1933 |
|
|
pci_img_ctrl2_bit2_1 <= #`FF_DELAY w_conf_data_in[2:1] ;
|
1934 |
|
|
end
|
1935 |
|
|
`P_BA2_ADDR:
|
1936 |
|
|
begin
|
1937 |
|
|
if (w_byte_en[3] == 1'b0)
|
1938 |
|
|
pci_ba2_bit31_12[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1939 |
|
|
if (w_byte_en[2] == 1'b0)
|
1940 |
|
|
pci_ba2_bit31_12[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1941 |
|
|
if (w_byte_en[1] == 1'b0)
|
1942 |
|
|
pci_ba2_bit31_12[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1943 |
|
|
if (w_byte_en[0] == 1'b0)
|
1944 |
|
|
pci_ba2_bit0 <= #`FF_DELAY w_conf_data_in[0] ;
|
1945 |
|
|
end
|
1946 |
|
|
`P_AM2_ADDR:
|
1947 |
|
|
begin
|
1948 |
|
|
if (w_byte_en[3] == 1'b0)
|
1949 |
|
|
pci_am2[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1950 |
|
|
if (w_byte_en[2] == 1'b0)
|
1951 |
|
|
pci_am2[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1952 |
|
|
if (w_byte_en[1] == 1'b0)
|
1953 |
|
|
pci_am2[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1954 |
|
|
end
|
1955 |
|
|
`P_TA2_ADDR:
|
1956 |
|
|
begin
|
1957 |
|
|
if (w_byte_en[3] == 1'b0)
|
1958 |
|
|
pci_ta2[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1959 |
|
|
if (w_byte_en[2] == 1'b0)
|
1960 |
|
|
pci_ta2[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1961 |
|
|
if (w_byte_en[1] == 1'b0)
|
1962 |
|
|
pci_ta2[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1963 |
|
|
end
|
1964 |
|
|
`P_IMG_CTRL3_ADDR:
|
1965 |
|
|
begin
|
1966 |
|
|
if (w_byte_en[0] == 1'b0)
|
1967 |
|
|
pci_img_ctrl3_bit2_1 <= #`FF_DELAY w_conf_data_in[2:1] ;
|
1968 |
|
|
end
|
1969 |
|
|
`P_BA3_ADDR:
|
1970 |
|
|
begin
|
1971 |
|
|
if (w_byte_en[3] == 1'b0)
|
1972 |
|
|
pci_ba3_bit31_12[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1973 |
|
|
if (w_byte_en[2] == 1'b0)
|
1974 |
|
|
pci_ba3_bit31_12[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1975 |
|
|
if (w_byte_en[1] == 1'b0)
|
1976 |
|
|
pci_ba3_bit31_12[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1977 |
|
|
if (w_byte_en[0] == 1'b0)
|
1978 |
|
|
pci_ba3_bit0 <= #`FF_DELAY w_conf_data_in[0] ;
|
1979 |
|
|
end
|
1980 |
|
|
`P_AM3_ADDR:
|
1981 |
|
|
begin
|
1982 |
|
|
if (w_byte_en[3] == 1'b0)
|
1983 |
|
|
pci_am3[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1984 |
|
|
if (w_byte_en[2] == 1'b0)
|
1985 |
|
|
pci_am3[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1986 |
|
|
if (w_byte_en[1] == 1'b0)
|
1987 |
|
|
pci_am3[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1988 |
|
|
end
|
1989 |
|
|
`P_TA3_ADDR:
|
1990 |
|
|
begin
|
1991 |
|
|
if (w_byte_en[3] == 1'b0)
|
1992 |
|
|
pci_ta3[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
1993 |
|
|
if (w_byte_en[2] == 1'b0)
|
1994 |
|
|
pci_ta3[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
1995 |
|
|
if (w_byte_en[1] == 1'b0)
|
1996 |
|
|
pci_ta3[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
1997 |
|
|
end
|
1998 |
|
|
`P_IMG_CTRL4_ADDR:
|
1999 |
|
|
begin
|
2000 |
|
|
if (w_byte_en[0] == 1'b0)
|
2001 |
|
|
pci_img_ctrl4_bit2_1 <= #`FF_DELAY w_conf_data_in[2:1] ;
|
2002 |
|
|
end
|
2003 |
|
|
`P_BA4_ADDR:
|
2004 |
|
|
begin
|
2005 |
|
|
if (w_byte_en[3] == 1'b0)
|
2006 |
|
|
pci_ba4_bit31_12[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
2007 |
|
|
if (w_byte_en[2] == 1'b0)
|
2008 |
|
|
pci_ba4_bit31_12[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
2009 |
|
|
if (w_byte_en[1] == 1'b0)
|
2010 |
|
|
pci_ba4_bit31_12[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
2011 |
|
|
if (w_byte_en[0] == 1'b0)
|
2012 |
|
|
pci_ba4_bit0 <= #`FF_DELAY w_conf_data_in[0] ;
|
2013 |
|
|
end
|
2014 |
|
|
`P_AM4_ADDR:
|
2015 |
|
|
begin
|
2016 |
|
|
if (w_byte_en[3] == 1'b0)
|
2017 |
|
|
pci_am4[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
2018 |
|
|
if (w_byte_en[2] == 1'b0)
|
2019 |
|
|
pci_am4[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
2020 |
|
|
if (w_byte_en[1] == 1'b0)
|
2021 |
|
|
pci_am4[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
2022 |
|
|
end
|
2023 |
|
|
`P_TA4_ADDR:
|
2024 |
|
|
begin
|
2025 |
|
|
if (w_byte_en[3] == 1'b0)
|
2026 |
|
|
pci_ta4[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
2027 |
|
|
if (w_byte_en[2] == 1'b0)
|
2028 |
|
|
pci_ta4[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
2029 |
|
|
if (w_byte_en[1] == 1'b0)
|
2030 |
|
|
pci_ta4[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
2031 |
|
|
end
|
2032 |
|
|
`P_IMG_CTRL5_ADDR:
|
2033 |
|
|
begin
|
2034 |
|
|
if (w_byte_en[0] == 1'b0)
|
2035 |
|
|
pci_img_ctrl5_bit2_1 <= #`FF_DELAY w_conf_data_in[2:1] ;
|
2036 |
|
|
end
|
2037 |
|
|
`P_BA5_ADDR:
|
2038 |
|
|
begin
|
2039 |
|
|
if (w_byte_en[3] == 1'b0)
|
2040 |
|
|
pci_ba5_bit31_12[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
2041 |
|
|
if (w_byte_en[2] == 1'b0)
|
2042 |
|
|
pci_ba5_bit31_12[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
2043 |
|
|
if (w_byte_en[1] == 1'b0)
|
2044 |
|
|
pci_ba5_bit31_12[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
2045 |
|
|
if (w_byte_en[0] == 1'b0)
|
2046 |
|
|
pci_ba5_bit0 <= #`FF_DELAY w_conf_data_in[0] ;
|
2047 |
|
|
end
|
2048 |
|
|
`P_AM5_ADDR:
|
2049 |
|
|
begin
|
2050 |
|
|
if (w_byte_en[3] == 1'b0)
|
2051 |
|
|
pci_am5[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
2052 |
|
|
if (w_byte_en[2] == 1'b0)
|
2053 |
|
|
pci_am5[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
2054 |
|
|
if (w_byte_en[1] == 1'b0)
|
2055 |
|
|
pci_am5[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
2056 |
|
|
end
|
2057 |
|
|
`P_TA5_ADDR:
|
2058 |
|
|
begin
|
2059 |
|
|
if (w_byte_en[3] == 1'b0)
|
2060 |
|
|
pci_ta5[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
2061 |
|
|
if (w_byte_en[2] == 1'b0)
|
2062 |
|
|
pci_ta5[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
2063 |
|
|
if (w_byte_en[1] == 1'b0)
|
2064 |
|
|
pci_ta5[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
2065 |
|
|
end
|
2066 |
|
|
`endif
|
2067 |
|
|
`P_ERR_CS_ADDR:
|
2068 |
|
|
begin
|
2069 |
|
|
if (w_byte_en[0] == 1'b0)
|
2070 |
|
|
pci_err_cs_bit0 <= #`FF_DELAY w_conf_data_in[0] ;
|
2071 |
|
|
end
|
2072 |
|
|
// WB slave - configuration space
|
2073 |
|
|
`W_IMG_CTRL1_ADDR:
|
2074 |
|
|
begin
|
2075 |
|
|
if (w_byte_en[0] == 1'b0)
|
2076 |
|
|
wb_img_ctrl1_bit2_0 <= #`FF_DELAY w_conf_data_in[2:0] ;
|
2077 |
|
|
end
|
2078 |
|
|
`W_BA1_ADDR:
|
2079 |
|
|
begin
|
2080 |
|
|
if (w_byte_en[3] == 1'b0)
|
2081 |
|
|
wb_ba1_bit31_12[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
2082 |
|
|
if (w_byte_en[2] == 1'b0)
|
2083 |
|
|
wb_ba1_bit31_12[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
2084 |
|
|
if (w_byte_en[1] == 1'b0)
|
2085 |
|
|
wb_ba1_bit31_12[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
2086 |
|
|
if (w_byte_en[0] == 1'b0)
|
2087 |
|
|
wb_ba1_bit0 <= #`FF_DELAY w_conf_data_in[0] ;
|
2088 |
|
|
end
|
2089 |
|
|
`W_AM1_ADDR:
|
2090 |
|
|
begin
|
2091 |
|
|
if (w_byte_en[3] == 1'b0)
|
2092 |
|
|
wb_am1[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
2093 |
|
|
if (w_byte_en[2] == 1'b0)
|
2094 |
|
|
wb_am1[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
2095 |
|
|
if (w_byte_en[1] == 1'b0)
|
2096 |
|
|
wb_am1[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
2097 |
|
|
end
|
2098 |
|
|
`W_TA1_ADDR:
|
2099 |
|
|
begin
|
2100 |
|
|
if (w_byte_en[3] == 1'b0)
|
2101 |
|
|
wb_ta1[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
2102 |
|
|
if (w_byte_en[2] == 1'b0)
|
2103 |
|
|
wb_ta1[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
2104 |
|
|
if (w_byte_en[1] == 1'b0)
|
2105 |
|
|
wb_ta1[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
2106 |
|
|
end
|
2107 |
|
|
`ifdef WB_IMAGE2
|
2108 |
|
|
`W_IMG_CTRL2_ADDR:
|
2109 |
|
|
begin
|
2110 |
|
|
if (w_byte_en[0] == 1'b0)
|
2111 |
|
|
wb_img_ctrl2_bit2_0 <= #`FF_DELAY w_conf_data_in[2:0] ;
|
2112 |
|
|
end
|
2113 |
|
|
`W_BA2_ADDR:
|
2114 |
|
|
begin
|
2115 |
|
|
if (w_byte_en[3] == 1'b0)
|
2116 |
|
|
wb_ba2_bit31_12[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
2117 |
|
|
if (w_byte_en[2] == 1'b0)
|
2118 |
|
|
wb_ba2_bit31_12[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
2119 |
|
|
if (w_byte_en[1] == 1'b0)
|
2120 |
|
|
wb_ba2_bit31_12[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
2121 |
|
|
if (w_byte_en[0] == 1'b0)
|
2122 |
|
|
wb_ba2_bit0 <= #`FF_DELAY w_conf_data_in[0] ;
|
2123 |
|
|
end
|
2124 |
|
|
`W_AM2_ADDR:
|
2125 |
|
|
begin
|
2126 |
|
|
if (w_byte_en[3] == 1'b0)
|
2127 |
|
|
wb_am2[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
2128 |
|
|
if (w_byte_en[2] == 1'b0)
|
2129 |
|
|
wb_am2[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
2130 |
|
|
if (w_byte_en[1] == 1'b0)
|
2131 |
|
|
wb_am2[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
2132 |
|
|
end
|
2133 |
|
|
`W_TA2_ADDR:
|
2134 |
|
|
begin
|
2135 |
|
|
if (w_byte_en[3] == 1'b0)
|
2136 |
|
|
wb_ta2[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
2137 |
|
|
if (w_byte_en[2] == 1'b0)
|
2138 |
|
|
wb_ta2[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
2139 |
|
|
if (w_byte_en[1] == 1'b0)
|
2140 |
|
|
wb_ta2[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
2141 |
|
|
end
|
2142 |
|
|
`endif
|
2143 |
|
|
`ifdef WB_IMAGE3
|
2144 |
|
|
`W_IMG_CTRL2_ADDR:
|
2145 |
|
|
begin
|
2146 |
|
|
if (w_byte_en[0] == 1'b0)
|
2147 |
|
|
wb_img_ctrl2_bit2_0 <= #`FF_DELAY w_conf_data_in[2:0] ;
|
2148 |
|
|
end
|
2149 |
|
|
`W_BA2_ADDR:
|
2150 |
|
|
begin
|
2151 |
|
|
if (w_byte_en[3] == 1'b0)
|
2152 |
|
|
wb_ba2_bit31_12[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
2153 |
|
|
if (w_byte_en[2] == 1'b0)
|
2154 |
|
|
wb_ba2_bit31_12[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
2155 |
|
|
if (w_byte_en[1] == 1'b0)
|
2156 |
|
|
wb_ba2_bit31_12[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
2157 |
|
|
if (w_byte_en[0] == 1'b0)
|
2158 |
|
|
wb_ba2_bit0 <= #`FF_DELAY w_conf_data_in[0] ;
|
2159 |
|
|
end
|
2160 |
|
|
`W_AM2_ADDR:
|
2161 |
|
|
begin
|
2162 |
|
|
if (w_byte_en[3] == 1'b0)
|
2163 |
|
|
wb_am2[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
2164 |
|
|
if (w_byte_en[2] == 1'b0)
|
2165 |
|
|
wb_am2[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
2166 |
|
|
if (w_byte_en[1] == 1'b0)
|
2167 |
|
|
wb_am2[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
2168 |
|
|
end
|
2169 |
|
|
`W_TA2_ADDR:
|
2170 |
|
|
begin
|
2171 |
|
|
if (w_byte_en[3] == 1'b0)
|
2172 |
|
|
wb_ta2[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
2173 |
|
|
if (w_byte_en[2] == 1'b0)
|
2174 |
|
|
wb_ta2[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
2175 |
|
|
if (w_byte_en[1] == 1'b0)
|
2176 |
|
|
wb_ta2[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
2177 |
|
|
end
|
2178 |
|
|
`W_IMG_CTRL3_ADDR:
|
2179 |
|
|
begin
|
2180 |
|
|
if (w_byte_en[0] == 1'b0)
|
2181 |
|
|
wb_img_ctrl3_bit2_0 <= #`FF_DELAY w_conf_data_in[2:0] ;
|
2182 |
|
|
end
|
2183 |
|
|
`W_BA3_ADDR:
|
2184 |
|
|
begin
|
2185 |
|
|
if (w_byte_en[3] == 1'b0)
|
2186 |
|
|
wb_ba3_bit31_12[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
2187 |
|
|
if (w_byte_en[2] == 1'b0)
|
2188 |
|
|
wb_ba3_bit31_12[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
2189 |
|
|
if (w_byte_en[1] == 1'b0)
|
2190 |
|
|
wb_ba3_bit31_12[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
2191 |
|
|
if (w_byte_en[0] == 1'b0)
|
2192 |
|
|
wb_ba3_bit0 <= #`FF_DELAY w_conf_data_in[0] ;
|
2193 |
|
|
end
|
2194 |
|
|
`W_AM3_ADDR:
|
2195 |
|
|
begin
|
2196 |
|
|
if (w_byte_en[3] == 1'b0)
|
2197 |
|
|
wb_am3[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
2198 |
|
|
if (w_byte_en[2] == 1'b0)
|
2199 |
|
|
wb_am3[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
2200 |
|
|
if (w_byte_en[1] == 1'b0)
|
2201 |
|
|
wb_am3[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
2202 |
|
|
end
|
2203 |
|
|
`W_TA3_ADDR:
|
2204 |
|
|
begin
|
2205 |
|
|
if (w_byte_en[3] == 1'b0)
|
2206 |
|
|
wb_ta3[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
2207 |
|
|
if (w_byte_en[2] == 1'b0)
|
2208 |
|
|
wb_ta3[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
2209 |
|
|
if (w_byte_en[1] == 1'b0)
|
2210 |
|
|
wb_ta3[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
2211 |
|
|
end
|
2212 |
|
|
`endif
|
2213 |
|
|
`ifdef WB_IMAGE4
|
2214 |
|
|
`W_IMG_CTRL2_ADDR:
|
2215 |
|
|
begin
|
2216 |
|
|
if (w_byte_en[0] == 1'b0)
|
2217 |
|
|
wb_img_ctrl2_bit2_0 <= #`FF_DELAY w_conf_data_in[2:0] ;
|
2218 |
|
|
end
|
2219 |
|
|
`W_BA2_ADDR:
|
2220 |
|
|
begin
|
2221 |
|
|
if (w_byte_en[3] == 1'b0)
|
2222 |
|
|
wb_ba2_bit31_12[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
2223 |
|
|
if (w_byte_en[2] == 1'b0)
|
2224 |
|
|
wb_ba2_bit31_12[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
2225 |
|
|
if (w_byte_en[1] == 1'b0)
|
2226 |
|
|
wb_ba2_bit31_12[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
2227 |
|
|
if (w_byte_en[0] == 1'b0)
|
2228 |
|
|
wb_ba2_bit0 <= #`FF_DELAY w_conf_data_in[0] ;
|
2229 |
|
|
end
|
2230 |
|
|
`W_AM2_ADDR:
|
2231 |
|
|
begin
|
2232 |
|
|
if (w_byte_en[3] == 1'b0)
|
2233 |
|
|
wb_am2[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
2234 |
|
|
if (w_byte_en[2] == 1'b0)
|
2235 |
|
|
wb_am2[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
2236 |
|
|
if (w_byte_en[1] == 1'b0)
|
2237 |
|
|
wb_am2[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
2238 |
|
|
end
|
2239 |
|
|
`W_TA2_ADDR:
|
2240 |
|
|
begin
|
2241 |
|
|
if (w_byte_en[3] == 1'b0)
|
2242 |
|
|
wb_ta2[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
2243 |
|
|
if (w_byte_en[2] == 1'b0)
|
2244 |
|
|
wb_ta2[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
2245 |
|
|
if (w_byte_en[1] == 1'b0)
|
2246 |
|
|
wb_ta2[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
2247 |
|
|
end
|
2248 |
|
|
`W_IMG_CTRL3_ADDR:
|
2249 |
|
|
begin
|
2250 |
|
|
if (w_byte_en[0] == 1'b0)
|
2251 |
|
|
wb_img_ctrl3_bit2_0 <= #`FF_DELAY w_conf_data_in[2:0] ;
|
2252 |
|
|
end
|
2253 |
|
|
`W_BA3_ADDR:
|
2254 |
|
|
begin
|
2255 |
|
|
if (w_byte_en[3] == 1'b0)
|
2256 |
|
|
wb_ba3_bit31_12[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
2257 |
|
|
if (w_byte_en[2] == 1'b0)
|
2258 |
|
|
wb_ba3_bit31_12[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
2259 |
|
|
if (w_byte_en[1] == 1'b0)
|
2260 |
|
|
wb_ba3_bit31_12[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
2261 |
|
|
if (w_byte_en[0] == 1'b0)
|
2262 |
|
|
wb_ba3_bit0 <= #`FF_DELAY w_conf_data_in[0] ;
|
2263 |
|
|
end
|
2264 |
|
|
`W_AM3_ADDR:
|
2265 |
|
|
begin
|
2266 |
|
|
if (w_byte_en[3] == 1'b0)
|
2267 |
|
|
wb_am3[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
2268 |
|
|
if (w_byte_en[2] == 1'b0)
|
2269 |
|
|
wb_am3[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
2270 |
|
|
if (w_byte_en[1] == 1'b0)
|
2271 |
|
|
wb_am3[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
2272 |
|
|
end
|
2273 |
|
|
`W_TA3_ADDR:
|
2274 |
|
|
begin
|
2275 |
|
|
if (w_byte_en[3] == 1'b0)
|
2276 |
|
|
wb_ta3[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
2277 |
|
|
if (w_byte_en[2] == 1'b0)
|
2278 |
|
|
wb_ta3[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
2279 |
|
|
if (w_byte_en[1] == 1'b0)
|
2280 |
|
|
wb_ta3[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
2281 |
|
|
end
|
2282 |
|
|
`W_IMG_CTRL4_ADDR:
|
2283 |
|
|
begin
|
2284 |
|
|
if (w_byte_en[0] == 1'b0)
|
2285 |
|
|
wb_img_ctrl4_bit2_0 <= #`FF_DELAY w_conf_data_in[2:0] ;
|
2286 |
|
|
end
|
2287 |
|
|
`W_BA4_ADDR:
|
2288 |
|
|
begin
|
2289 |
|
|
if (w_byte_en[3] == 1'b0)
|
2290 |
|
|
wb_ba4_bit31_12[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
2291 |
|
|
if (w_byte_en[2] == 1'b0)
|
2292 |
|
|
wb_ba4_bit31_12[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
2293 |
|
|
if (w_byte_en[1] == 1'b0)
|
2294 |
|
|
wb_ba4_bit31_12[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
2295 |
|
|
if (w_byte_en[0] == 1'b0)
|
2296 |
|
|
wb_ba4_bit0 <= #`FF_DELAY w_conf_data_in[0] ;
|
2297 |
|
|
end
|
2298 |
|
|
`W_AM4_ADDR:
|
2299 |
|
|
begin
|
2300 |
|
|
if (w_byte_en[3] == 1'b0)
|
2301 |
|
|
wb_am4[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
2302 |
|
|
if (w_byte_en[2] == 1'b0)
|
2303 |
|
|
wb_am4[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
2304 |
|
|
if (w_byte_en[1] == 1'b0)
|
2305 |
|
|
wb_am4[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
2306 |
|
|
end
|
2307 |
|
|
`W_TA4_ADDR:
|
2308 |
|
|
begin
|
2309 |
|
|
if (w_byte_en[3] == 1'b0)
|
2310 |
|
|
wb_ta4[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
2311 |
|
|
if (w_byte_en[2] == 1'b0)
|
2312 |
|
|
wb_ta4[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
2313 |
|
|
if (w_byte_en[1] == 1'b0)
|
2314 |
|
|
wb_ta4[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
2315 |
|
|
end
|
2316 |
|
|
`endif
|
2317 |
|
|
`ifdef WB_IMAGE5
|
2318 |
|
|
`W_IMG_CTRL2_ADDR:
|
2319 |
|
|
begin
|
2320 |
|
|
if (w_byte_en[0] == 1'b0)
|
2321 |
|
|
wb_img_ctrl2_bit2_0 <= #`FF_DELAY w_conf_data_in[2:0] ;
|
2322 |
|
|
end
|
2323 |
|
|
`W_BA2_ADDR:
|
2324 |
|
|
begin
|
2325 |
|
|
if (w_byte_en[3] == 1'b0)
|
2326 |
|
|
wb_ba2_bit31_12[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
2327 |
|
|
if (w_byte_en[2] == 1'b0)
|
2328 |
|
|
wb_ba2_bit31_12[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
2329 |
|
|
if (w_byte_en[1] == 1'b0)
|
2330 |
|
|
wb_ba2_bit31_12[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
2331 |
|
|
if (w_byte_en[0] == 1'b0)
|
2332 |
|
|
wb_ba2_bit0 <= #`FF_DELAY w_conf_data_in[0] ;
|
2333 |
|
|
end
|
2334 |
|
|
`W_AM2_ADDR:
|
2335 |
|
|
begin
|
2336 |
|
|
if (w_byte_en[3] == 1'b0)
|
2337 |
|
|
wb_am2[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
2338 |
|
|
if (w_byte_en[2] == 1'b0)
|
2339 |
|
|
wb_am2[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
2340 |
|
|
if (w_byte_en[1] == 1'b0)
|
2341 |
|
|
wb_am2[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
2342 |
|
|
end
|
2343 |
|
|
`W_TA2_ADDR:
|
2344 |
|
|
begin
|
2345 |
|
|
if (w_byte_en[3] == 1'b0)
|
2346 |
|
|
wb_ta2[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
2347 |
|
|
if (w_byte_en[2] == 1'b0)
|
2348 |
|
|
wb_ta2[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
2349 |
|
|
if (w_byte_en[1] == 1'b0)
|
2350 |
|
|
wb_ta2[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
2351 |
|
|
end
|
2352 |
|
|
`W_IMG_CTRL3_ADDR:
|
2353 |
|
|
begin
|
2354 |
|
|
if (w_byte_en[0] == 1'b0)
|
2355 |
|
|
wb_img_ctrl3_bit2_0 <= #`FF_DELAY w_conf_data_in[2:0] ;
|
2356 |
|
|
end
|
2357 |
|
|
`W_BA3_ADDR:
|
2358 |
|
|
begin
|
2359 |
|
|
if (w_byte_en[3] == 1'b0)
|
2360 |
|
|
wb_ba3_bit31_12[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
2361 |
|
|
if (w_byte_en[2] == 1'b0)
|
2362 |
|
|
wb_ba3_bit31_12[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
2363 |
|
|
if (w_byte_en[1] == 1'b0)
|
2364 |
|
|
wb_ba3_bit31_12[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
2365 |
|
|
if (w_byte_en[0] == 1'b0)
|
2366 |
|
|
wb_ba3_bit0 <= #`FF_DELAY w_conf_data_in[0] ;
|
2367 |
|
|
end
|
2368 |
|
|
`W_AM3_ADDR:
|
2369 |
|
|
begin
|
2370 |
|
|
if (w_byte_en[3] == 1'b0)
|
2371 |
|
|
wb_am3[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
2372 |
|
|
if (w_byte_en[2] == 1'b0)
|
2373 |
|
|
wb_am3[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
2374 |
|
|
if (w_byte_en[1] == 1'b0)
|
2375 |
|
|
wb_am3[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
2376 |
|
|
end
|
2377 |
|
|
`W_TA3_ADDR:
|
2378 |
|
|
begin
|
2379 |
|
|
if (w_byte_en[3] == 1'b0)
|
2380 |
|
|
wb_ta3[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
2381 |
|
|
if (w_byte_en[2] == 1'b0)
|
2382 |
|
|
wb_ta3[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
2383 |
|
|
if (w_byte_en[1] == 1'b0)
|
2384 |
|
|
wb_ta3[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
2385 |
|
|
end
|
2386 |
|
|
`W_IMG_CTRL4_ADDR:
|
2387 |
|
|
begin
|
2388 |
|
|
if (w_byte_en[0] == 1'b0)
|
2389 |
|
|
wb_img_ctrl4_bit2_0 <= #`FF_DELAY w_conf_data_in[2:0] ;
|
2390 |
|
|
end
|
2391 |
|
|
`W_BA4_ADDR:
|
2392 |
|
|
begin
|
2393 |
|
|
if (w_byte_en[3] == 1'b0)
|
2394 |
|
|
wb_ba4_bit31_12[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
2395 |
|
|
if (w_byte_en[2] == 1'b0)
|
2396 |
|
|
wb_ba4_bit31_12[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
2397 |
|
|
if (w_byte_en[1] == 1'b0)
|
2398 |
|
|
wb_ba4_bit31_12[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
2399 |
|
|
if (w_byte_en[0] == 1'b0)
|
2400 |
|
|
wb_ba4_bit0 <= #`FF_DELAY w_conf_data_in[0] ;
|
2401 |
|
|
end
|
2402 |
|
|
`W_AM4_ADDR:
|
2403 |
|
|
begin
|
2404 |
|
|
if (w_byte_en[3] == 1'b0)
|
2405 |
|
|
wb_am4[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
2406 |
|
|
if (w_byte_en[2] == 1'b0)
|
2407 |
|
|
wb_am4[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
2408 |
|
|
if (w_byte_en[1] == 1'b0)
|
2409 |
|
|
wb_am4[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
2410 |
|
|
end
|
2411 |
|
|
`W_TA4_ADDR:
|
2412 |
|
|
begin
|
2413 |
|
|
if (w_byte_en[3] == 1'b0)
|
2414 |
|
|
wb_ta4[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
2415 |
|
|
if (w_byte_en[2] == 1'b0)
|
2416 |
|
|
wb_ta4[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
2417 |
|
|
if (w_byte_en[1] == 1'b0)
|
2418 |
|
|
wb_ta4[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
2419 |
|
|
end
|
2420 |
|
|
`W_IMG_CTRL5_ADDR:
|
2421 |
|
|
begin
|
2422 |
|
|
if (w_byte_en[0] == 1'b0)
|
2423 |
|
|
wb_img_ctrl5_bit2_0 <= #`FF_DELAY w_conf_data_in[2:0] ;
|
2424 |
|
|
end
|
2425 |
|
|
`W_BA5_ADDR:
|
2426 |
|
|
begin
|
2427 |
|
|
if (w_byte_en[3] == 1'b0)
|
2428 |
|
|
wb_ba5_bit31_12[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
2429 |
|
|
if (w_byte_en[2] == 1'b0)
|
2430 |
|
|
wb_ba5_bit31_12[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
2431 |
|
|
if (w_byte_en[1] == 1'b0)
|
2432 |
|
|
wb_ba5_bit31_12[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
2433 |
|
|
if (w_byte_en[0] == 1'b0)
|
2434 |
|
|
wb_ba5_bit0 <= #`FF_DELAY w_conf_data_in[0] ;
|
2435 |
|
|
end
|
2436 |
|
|
`W_AM5_ADDR:
|
2437 |
|
|
begin
|
2438 |
|
|
if (w_byte_en[3] == 1'b0)
|
2439 |
|
|
wb_am5[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
2440 |
|
|
if (w_byte_en[2] == 1'b0)
|
2441 |
|
|
wb_am5[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
2442 |
|
|
if (w_byte_en[1] == 1'b0)
|
2443 |
|
|
wb_am5[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
2444 |
|
|
end
|
2445 |
|
|
`W_TA5_ADDR:
|
2446 |
|
|
begin
|
2447 |
|
|
if (w_byte_en[3] == 1'b0)
|
2448 |
|
|
wb_ta5[31:24] <= #`FF_DELAY w_conf_data_in[31:24] ;
|
2449 |
|
|
if (w_byte_en[2] == 1'b0)
|
2450 |
|
|
wb_ta5[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
2451 |
|
|
if (w_byte_en[1] == 1'b0)
|
2452 |
|
|
wb_ta5[15:12] <= #`FF_DELAY w_conf_data_in[15:12] ;
|
2453 |
|
|
end
|
2454 |
|
|
`endif
|
2455 |
|
|
`W_ERR_CS_ADDR:
|
2456 |
|
|
begin
|
2457 |
|
|
if (w_byte_en[0] == 1'b0)
|
2458 |
|
|
wb_err_cs_bit0 <= #`FF_DELAY w_conf_data_in[0] ;
|
2459 |
|
|
end
|
2460 |
|
|
|
2461 |
|
|
`CNF_ADDR_ADDR:
|
2462 |
|
|
begin
|
2463 |
|
|
if (w_byte_en[2] == 1'b0)
|
2464 |
|
|
cnf_addr_bit23_2[23:16] <= #`FF_DELAY w_conf_data_in[23:16] ;
|
2465 |
|
|
if (w_byte_en[1] == 1'b0)
|
2466 |
|
|
cnf_addr_bit23_2[15:8] <= #`FF_DELAY w_conf_data_in[15:8] ;
|
2467 |
|
|
if (w_byte_en[0] == 1'b0)
|
2468 |
|
|
begin
|
2469 |
|
|
cnf_addr_bit23_2[7:2] <= #`FF_DELAY w_conf_data_in[7:2] ;
|
2470 |
|
|
cnf_addr_bit0 <= #`FF_DELAY w_conf_data_in[0] ;
|
2471 |
|
|
end
|
2472 |
|
|
end
|
2473 |
|
|
// `CNF_DATA_ADDR: implemented elsewhere !!!
|
2474 |
|
|
// `INT_ACK_ADDR : implemented elsewhere !!!
|
2475 |
|
|
`ICR_ADDR:
|
2476 |
|
|
begin
|
2477 |
|
|
if (w_byte_en[3] == 1'b0)
|
2478 |
|
|
icr_bit31 <= #`FF_DELAY w_conf_data_in[31] ;
|
2479 |
|
|
if (w_byte_en[0] == 1'b0)
|
2480 |
|
|
icr_bit3_0 <= #`FF_DELAY w_conf_data_in[3:0] ;
|
2481 |
|
|
end
|
2482 |
|
|
default :
|
2483 |
|
|
begin
|
2484 |
|
|
end
|
2485 |
|
|
endcase
|
2486 |
|
|
end
|
2487 |
|
|
endcase
|
2488 |
|
|
end
|
2489 |
|
|
end
|
2490 |
|
|
end
|
2491 |
|
|
|
2492 |
|
|
// This signals are synchronous resets for registers, whic occures when asynchronous RESET is '1' or
|
2493 |
|
|
// data '1' is synchronously written into them!
|
2494 |
|
|
reg delete_status_bit15 ;
|
2495 |
|
|
reg delete_status_bit14 ;
|
2496 |
|
|
reg delete_status_bit13 ;
|
2497 |
|
|
reg delete_status_bit12 ;
|
2498 |
|
|
reg delete_status_bit11 ;
|
2499 |
|
|
reg delete_status_bit8 ;
|
2500 |
|
|
reg delete_pci_err_cs_bit10 ;
|
2501 |
|
|
reg delete_pci_err_cs_bit8 ;
|
2502 |
|
|
reg delete_wb_err_cs_bit10 ;
|
2503 |
|
|
reg delete_wb_err_cs_bit8 ;
|
2504 |
|
|
reg delete_isr_bit3 ;
|
2505 |
|
|
reg delete_isr_bit2 ;
|
2506 |
|
|
reg delete_isr_bit1 ;
|
2507 |
|
|
reg delete_isr_bit0 ;
|
2508 |
|
|
|
2509 |
|
|
// If nothing is written into, then the value is '0' (W_WE = 0) !!!
|
2510 |
|
|
wire delete_status_bit15_in = w_we ? w_conf_data_in[31] : 1'b0 ;
|
2511 |
|
|
wire delete_status_bit14_in = w_we ? w_conf_data_in[30] : 1'b0 ;
|
2512 |
|
|
wire delete_status_bit13_in = w_we ? w_conf_data_in[29] : 1'b0 ;
|
2513 |
|
|
wire delete_status_bit12_in = w_we ? w_conf_data_in[28] : 1'b0 ;
|
2514 |
|
|
wire delete_status_bit11_in = w_we ? w_conf_data_in[27] : 1'b0 ;
|
2515 |
|
|
wire delete_status_bit8_in = w_we ? w_conf_data_in[24] : 1'b0 ;
|
2516 |
|
|
wire delete_pci_err_cs_bit10_in = w_we ? w_conf_data_in[10] : 1'b0 ;
|
2517 |
|
|
wire delete_pci_err_cs_bit8_in = w_we ? w_conf_data_in[8] : 1'b0 ;
|
2518 |
|
|
wire delete_wb_err_cs_bit10_in = w_we ? w_conf_data_in[10] : 1'b0 ;
|
2519 |
|
|
wire delete_wb_err_cs_bit8_in = w_we ? w_conf_data_in[8] : 1'b0 ;
|
2520 |
|
|
wire delete_isr_bit3_in = w_we ? w_conf_data_in[3] : 1'b0 ;
|
2521 |
|
|
wire delete_isr_bit2_in = w_we ? w_conf_data_in[2] : 1'b0 ;
|
2522 |
|
|
wire delete_isr_bit1_in = w_we ? w_conf_data_in[1] : 1'b0 ;
|
2523 |
|
|
wire delete_isr_bit0_in = w_we ? w_conf_data_in[0] : 1'b0 ;
|
2524 |
|
|
|
2525 |
|
|
// This are aditional register bits, which are resets when their value is '1' !!!
|
2526 |
|
|
always@(posedge w_clock or posedge reset)
|
2527 |
|
|
begin
|
2528 |
|
|
if (reset) // Asynchronous RESET sets signals to '1'
|
2529 |
|
|
begin
|
2530 |
|
|
delete_status_bit15 <= #`FF_DELAY 1'b1 ;
|
2531 |
|
|
delete_status_bit14 <= #`FF_DELAY 1'b1 ;
|
2532 |
|
|
delete_status_bit13 <= #`FF_DELAY 1'b1 ;
|
2533 |
|
|
delete_status_bit12 <= #`FF_DELAY 1'b1 ;
|
2534 |
|
|
delete_status_bit11 <= #`FF_DELAY 1'b1 ;
|
2535 |
|
|
delete_status_bit8 <= #`FF_DELAY 1'b1 ;
|
2536 |
|
|
delete_pci_err_cs_bit10 <= #`FF_DELAY 1'b1 ;
|
2537 |
|
|
delete_pci_err_cs_bit8 <= #`FF_DELAY 1'b1 ;
|
2538 |
|
|
delete_wb_err_cs_bit10 <= #`FF_DELAY 1'b1 ;
|
2539 |
|
|
delete_wb_err_cs_bit8 <= #`FF_DELAY 1'b1 ;
|
2540 |
|
|
delete_isr_bit3 <= #`FF_DELAY 1'b1 ;
|
2541 |
|
|
delete_isr_bit2 <= #`FF_DELAY 1'b1 ;
|
2542 |
|
|
delete_isr_bit1 <= #`FF_DELAY 1'b1 ;
|
2543 |
|
|
delete_isr_bit0 <= #`FF_DELAY 1'b1 ;
|
2544 |
|
|
end
|
2545 |
|
|
else
|
2546 |
|
|
begin // If '1' is written into, then it also sets signals to '1'
|
2547 |
|
|
case (w_conf_address_in[8])
|
2548 |
|
|
1'b0 :
|
2549 |
|
|
// if (~w_conf_address_in[8])
|
2550 |
|
|
begin
|
2551 |
|
|
case ({w_conf_address_in[7], w_conf_address_in[6]})
|
2552 |
|
|
2'b00 :
|
2553 |
|
|
// if ((~w_conf_address_in[7]) && (~w_conf_address_in[6]))
|
2554 |
|
|
begin
|
2555 |
|
|
// PCI header - configuration space
|
2556 |
|
|
case (w_conf_address_in[5:2])
|
2557 |
|
|
4'h1:
|
2558 |
|
|
begin
|
2559 |
|
|
if (w_byte_en[3] == 1'b0)
|
2560 |
|
|
begin
|
2561 |
|
|
delete_status_bit15 <= #`FF_DELAY delete_status_bit15_in ;
|
2562 |
|
|
delete_status_bit14 <= #`FF_DELAY delete_status_bit14_in ;
|
2563 |
|
|
delete_status_bit13 <= #`FF_DELAY delete_status_bit13_in ;
|
2564 |
|
|
delete_status_bit12 <= #`FF_DELAY delete_status_bit12_in ;
|
2565 |
|
|
delete_status_bit11 <= #`FF_DELAY delete_status_bit11_in ;
|
2566 |
|
|
delete_status_bit8 <= #`FF_DELAY delete_status_bit8_in ;
|
2567 |
|
|
end
|
2568 |
|
|
end
|
2569 |
|
|
default :
|
2570 |
|
|
begin
|
2571 |
|
|
end
|
2572 |
|
|
endcase
|
2573 |
|
|
end
|
2574 |
|
|
default :
|
2575 |
|
|
begin
|
2576 |
|
|
end
|
2577 |
|
|
endcase
|
2578 |
|
|
end
|
2579 |
|
|
default :
|
2580 |
|
|
// else
|
2581 |
|
|
begin
|
2582 |
|
|
// PCI target - configuration space
|
2583 |
|
|
case (w_conf_address_in[7:2])
|
2584 |
|
|
`P_ERR_CS_ADDR:
|
2585 |
|
|
begin
|
2586 |
|
|
if (w_byte_en[1] == 1'b0)
|
2587 |
|
|
begin
|
2588 |
|
|
delete_pci_err_cs_bit10 <= #`FF_DELAY delete_pci_err_cs_bit10_in ;
|
2589 |
|
|
delete_pci_err_cs_bit8 <= #`FF_DELAY delete_pci_err_cs_bit8_in ;
|
2590 |
|
|
end
|
2591 |
|
|
end
|
2592 |
|
|
`W_ERR_CS_ADDR:
|
2593 |
|
|
begin
|
2594 |
|
|
if (w_byte_en[1] == 1'b0)
|
2595 |
|
|
begin
|
2596 |
|
|
delete_wb_err_cs_bit10 <= #`FF_DELAY delete_wb_err_cs_bit10_in ;
|
2597 |
|
|
delete_wb_err_cs_bit8 <= #`FF_DELAY delete_wb_err_cs_bit8_in ;
|
2598 |
|
|
end
|
2599 |
|
|
end
|
2600 |
|
|
`ISR_ADDR:
|
2601 |
|
|
begin
|
2602 |
|
|
if (w_byte_en[0] == 1'b0)
|
2603 |
|
|
begin
|
2604 |
|
|
delete_isr_bit3 <= #`FF_DELAY delete_isr_bit3_in ;
|
2605 |
|
|
delete_isr_bit2 <= #`FF_DELAY delete_isr_bit2_in ;
|
2606 |
|
|
delete_isr_bit1 <= #`FF_DELAY delete_isr_bit1_in ;
|
2607 |
|
|
delete_isr_bit0 <= #`FF_DELAY delete_isr_bit0_in ;
|
2608 |
|
|
end
|
2609 |
|
|
end
|
2610 |
|
|
default :
|
2611 |
|
|
begin
|
2612 |
|
|
end
|
2613 |
|
|
endcase
|
2614 |
|
|
end
|
2615 |
|
|
endcase
|
2616 |
|
|
end
|
2617 |
|
|
end
|
2618 |
|
|
|
2619 |
|
|
// Following are REGISTERS , which have "asynchronous & synchronous RESET" and synchronous SET on pci_clk !
|
2620 |
|
|
always@(posedge pci_clk or posedge delete_status_bit15)
|
2621 |
|
|
begin
|
2622 |
|
|
if (delete_status_bit15) // Asynchronous reset
|
2623 |
|
|
status_bit15_11[15] <= #`FF_DELAY 1'b0 ;
|
2624 |
|
|
else
|
2625 |
|
|
if (perr_in)
|
2626 |
|
|
status_bit15_11[15] <= #`FF_DELAY 1'b1 ;
|
2627 |
|
|
end
|
2628 |
|
|
always@(posedge pci_clk or posedge delete_status_bit14)
|
2629 |
|
|
begin
|
2630 |
|
|
if (delete_status_bit14) // Asynchronous reset
|
2631 |
|
|
status_bit15_11[14] <= #`FF_DELAY 1'b0 ;
|
2632 |
|
|
else
|
2633 |
|
|
if (serr_in)
|
2634 |
|
|
status_bit15_11[14] <= #`FF_DELAY 1'b1 ;
|
2635 |
|
|
end
|
2636 |
|
|
always@(posedge pci_clk or posedge delete_status_bit13)
|
2637 |
|
|
begin
|
2638 |
|
|
if (delete_status_bit13) // Asynchronous reset
|
2639 |
|
|
status_bit15_11[13] <= #`FF_DELAY 1'b0 ;
|
2640 |
|
|
else
|
2641 |
|
|
if (master_abort_recv)
|
2642 |
|
|
status_bit15_11[13] <= #`FF_DELAY 1'b1 ;
|
2643 |
|
|
end
|
2644 |
|
|
always@(posedge pci_clk or posedge delete_status_bit12)
|
2645 |
|
|
begin
|
2646 |
|
|
if (delete_status_bit12) // Asynchronous reset
|
2647 |
|
|
status_bit15_11[12] <= #`FF_DELAY 1'b0 ;
|
2648 |
|
|
else
|
2649 |
|
|
if (target_abort_recv)
|
2650 |
|
|
status_bit15_11[12] <= #`FF_DELAY 1'b1 ;
|
2651 |
|
|
end
|
2652 |
|
|
always@(posedge pci_clk or posedge delete_status_bit11)
|
2653 |
|
|
begin
|
2654 |
|
|
if (delete_status_bit11) // Asynchronous reset
|
2655 |
|
|
status_bit15_11[11] <= #`FF_DELAY 1'b0 ;
|
2656 |
|
|
else
|
2657 |
|
|
if (target_abort_set)
|
2658 |
|
|
status_bit15_11[11] <= #`FF_DELAY 1'b1 ;
|
2659 |
|
|
end
|
2660 |
|
|
always@(posedge pci_clk or posedge delete_status_bit8)
|
2661 |
|
|
begin
|
2662 |
|
|
if (delete_status_bit8) // Asynchronous reset
|
2663 |
|
|
status_bit8 <= #`FF_DELAY 1'b0 ;
|
2664 |
|
|
else
|
2665 |
|
|
if (master_data_par_err && command_bit6)
|
2666 |
|
|
status_bit8 <= #`FF_DELAY 1'b1 ;
|
2667 |
|
|
end
|
2668 |
|
|
|
2669 |
|
|
// Following are REGISTERS , which have "asynchronous & synchronous RESET" and synchronous SET on w_clock !
|
2670 |
|
|
always@(posedge wb_clk or posedge delete_pci_err_cs_bit10)
|
2671 |
|
|
begin
|
2672 |
|
|
if (delete_pci_err_cs_bit10) // Asynchronous reset
|
2673 |
|
|
pci_err_cs_bit10 <= #`FF_DELAY 1'b0 ;
|
2674 |
|
|
else
|
2675 |
|
|
if (pci_error_rty_exp && pci_err_cs_bit0)
|
2676 |
|
|
pci_err_cs_bit10 <= #`FF_DELAY 1'b1 ;
|
2677 |
|
|
end
|
2678 |
|
|
always@(posedge wb_clk or posedge delete_pci_err_cs_bit8)
|
2679 |
|
|
begin
|
2680 |
|
|
if (delete_pci_err_cs_bit8) // Asynchronous reset
|
2681 |
|
|
pci_err_cs_bit8 <= #`FF_DELAY 1'b0 ;
|
2682 |
|
|
else
|
2683 |
|
|
if (pci_error_sig && pci_err_cs_bit0)
|
2684 |
|
|
pci_err_cs_bit8 <= #`FF_DELAY 1'b1 ;
|
2685 |
|
|
end
|
2686 |
|
|
always@(posedge wb_clk or posedge reset)
|
2687 |
|
|
begin
|
2688 |
|
|
if (reset) // Asynchronous reset
|
2689 |
|
|
begin
|
2690 |
|
|
pci_err_cs_bit31_24 <= #`FF_DELAY 8'h00 ;
|
2691 |
|
|
pci_err_addr <= #`FF_DELAY 32'h0000_0000 ;
|
2692 |
|
|
pci_err_data <= #`FF_DELAY 32'h0000_0000 ;
|
2693 |
|
|
end
|
2694 |
|
|
else
|
2695 |
|
|
if (pci_error_sig && pci_err_cs_bit0)
|
2696 |
|
|
begin
|
2697 |
|
|
pci_err_cs_bit31_24 <= #`FF_DELAY { pci_error_be, pci_error_bc } ;
|
2698 |
|
|
pci_err_addr <= #`FF_DELAY pci_error_addr ;
|
2699 |
|
|
pci_err_data <= #`FF_DELAY pci_error_data ;
|
2700 |
|
|
end
|
2701 |
|
|
end
|
2702 |
|
|
|
2703 |
|
|
always@(posedge pci_clk or posedge delete_wb_err_cs_bit10)
|
2704 |
|
|
begin
|
2705 |
|
|
if (delete_wb_err_cs_bit10) // Asynchronous reset
|
2706 |
|
|
wb_err_cs_bit10_8[10] <= #`FF_DELAY 1'b0 ;
|
2707 |
|
|
else
|
2708 |
|
|
if (wb_error_rty_exp && wb_err_cs_bit0)
|
2709 |
|
|
wb_err_cs_bit10_8[10] <= #`FF_DELAY 1'b1 ;
|
2710 |
|
|
end
|
2711 |
|
|
always@(posedge pci_clk or posedge reset)
|
2712 |
|
|
begin
|
2713 |
|
|
if (reset) // Asynchronous reset
|
2714 |
|
|
wb_err_cs_bit10_8[9] <= #`FF_DELAY 1'b0 ;
|
2715 |
|
|
else
|
2716 |
|
|
if (wb_error_sig && wb_err_cs_bit0)
|
2717 |
|
|
wb_err_cs_bit10_8[9] <= #`FF_DELAY wb_error_es ;
|
2718 |
|
|
end
|
2719 |
|
|
always@(posedge pci_clk or posedge delete_wb_err_cs_bit8)
|
2720 |
|
|
begin
|
2721 |
|
|
if (delete_wb_err_cs_bit8) // Asynchronous reset
|
2722 |
|
|
wb_err_cs_bit10_8[8] <= #`FF_DELAY 1'b0 ;
|
2723 |
|
|
else
|
2724 |
|
|
if (wb_error_sig && wb_err_cs_bit0)
|
2725 |
|
|
wb_err_cs_bit10_8[8] <= #`FF_DELAY 1'b1 ;
|
2726 |
|
|
end
|
2727 |
|
|
always@(posedge pci_clk or posedge reset)
|
2728 |
|
|
begin
|
2729 |
|
|
if (reset) // Asynchronous reset
|
2730 |
|
|
begin
|
2731 |
|
|
wb_err_cs_bit31_24 <= #`FF_DELAY 8'h00 ;
|
2732 |
|
|
wb_err_addr <= #`FF_DELAY 32'h0000_0000 ;
|
2733 |
|
|
wb_err_data <= #`FF_DELAY 32'h0000_0000 ;
|
2734 |
|
|
end
|
2735 |
|
|
else
|
2736 |
|
|
if (wb_error_sig && wb_err_cs_bit0)
|
2737 |
|
|
begin
|
2738 |
|
|
wb_err_cs_bit31_24 <= #`FF_DELAY { wb_error_be, wb_error_bc } ;
|
2739 |
|
|
wb_err_addr <= #`FF_DELAY wb_error_addr ;
|
2740 |
|
|
wb_err_data <= #`FF_DELAY wb_error_data ;
|
2741 |
|
|
end
|
2742 |
|
|
end
|
2743 |
|
|
|
2744 |
|
|
always@(posedge w_clock or posedge delete_isr_bit3)
|
2745 |
|
|
begin
|
2746 |
|
|
if (delete_isr_bit3) // Asynchronous reset
|
2747 |
|
|
isr_bit3_0[3] <= #`FF_DELAY 1'b0 ;
|
2748 |
|
|
else
|
2749 |
|
|
if (isr_int_prop && icr_bit3_0[3])
|
2750 |
|
|
isr_bit3_0[3] <= #`FF_DELAY 1'b1 ;
|
2751 |
|
|
end
|
2752 |
|
|
always@(posedge w_clock or posedge delete_isr_bit2)
|
2753 |
|
|
begin
|
2754 |
|
|
if (delete_isr_bit2) // Asynchronous reset
|
2755 |
|
|
isr_bit3_0[2] <= #`FF_DELAY 1'b0 ;
|
2756 |
|
|
else
|
2757 |
|
|
if (isr_err_int && icr_bit3_0[2])
|
2758 |
|
|
isr_bit3_0[2] <= #`FF_DELAY 1'b1 ;
|
2759 |
|
|
end
|
2760 |
|
|
always@(posedge w_clock or posedge delete_isr_bit1)
|
2761 |
|
|
begin
|
2762 |
|
|
if (delete_isr_bit1) // Asynchronous reset
|
2763 |
|
|
isr_bit3_0[1] <= #`FF_DELAY 1'b0 ;
|
2764 |
|
|
else
|
2765 |
|
|
if (isr_par_err_int && icr_bit3_0[1])
|
2766 |
|
|
isr_bit3_0[1] <= #`FF_DELAY 1'b1 ;
|
2767 |
|
|
end
|
2768 |
|
|
always@(posedge w_clock or posedge delete_isr_bit0)
|
2769 |
|
|
begin
|
2770 |
|
|
if (delete_isr_bit0) // Asynchronous reset
|
2771 |
|
|
isr_bit3_0[0] <= #`FF_DELAY 1'b0 ;
|
2772 |
|
|
else
|
2773 |
|
|
if (isr_sys_err_int && icr_bit3_0[0])
|
2774 |
|
|
isr_bit3_0[0] <= #`FF_DELAY 1'b1 ;
|
2775 |
|
|
end
|
2776 |
|
|
|
2777 |
|
|
|
2778 |
|
|
/*-----------------------------------------------------------------------------------------------------------
|
2779 |
|
|
OUTPUTs from registers !!!
|
2780 |
|
|
-----------------------------------------------------------------------------------------------------------*/
|
2781 |
|
|
// PCI header outputs from command register
|
2782 |
|
|
assign serr_enable = command_bit8 ;
|
2783 |
|
|
assign perr_response = command_bit6 ;
|
2784 |
|
|
assign pci_master_enable = command_bit2_0[2] ;
|
2785 |
|
|
assign memory_space_enable = command_bit2_0[1] ;
|
2786 |
|
|
assign io_space_enable = command_bit2_0[0] ;
|
2787 |
|
|
// PCI header output from cache_line_size, latency timer and interrupt pin
|
2788 |
|
|
assign cache_line_size[7 : 0] = cache_line_size_reg ;
|
2789 |
|
|
assign latency_tim[7 : 0] = latency_timer ;
|
2790 |
|
|
assign int_pin[2 : 0] = r_interrupt_pin ;
|
2791 |
|
|
// PCI output from image registers
|
2792 |
|
|
assign pci_base_addr0[31 : 12] = pci_ba0_bit31_12 ;
|
2793 |
|
|
assign pci_base_addr1[31 : 12] = pci_ba1_bit31_12 ;
|
2794 |
|
|
assign pci_base_addr2[31 : 12] = pci_ba2_bit31_12 ;
|
2795 |
|
|
assign pci_base_addr3[31 : 12] = pci_ba3_bit31_12 ;
|
2796 |
|
|
assign pci_base_addr4[31 : 12] = pci_ba4_bit31_12 ;
|
2797 |
|
|
assign pci_base_addr5[31 : 12] = pci_ba5_bit31_12 ;
|
2798 |
|
|
assign pci_memory_io0 = pci_ba0_bit0 ;
|
2799 |
|
|
assign pci_memory_io1 = pci_ba1_bit0 ;
|
2800 |
|
|
assign pci_memory_io2 = pci_ba2_bit0 ;
|
2801 |
|
|
assign pci_memory_io3 = pci_ba3_bit0 ;
|
2802 |
|
|
assign pci_memory_io4 = pci_ba4_bit0 ;
|
2803 |
|
|
assign pci_memory_io5 = pci_ba5_bit0 ;
|
2804 |
|
|
assign pci_addr_mask0[31 : 12] = pci_am0 ;
|
2805 |
|
|
assign pci_addr_mask1[31 : 12] = pci_am1 ;
|
2806 |
|
|
assign pci_addr_mask2[31 : 12] = pci_am2 ;
|
2807 |
|
|
assign pci_addr_mask3[31 : 12] = pci_am3 ;
|
2808 |
|
|
assign pci_addr_mask4[31 : 12] = pci_am4 ;
|
2809 |
|
|
assign pci_addr_mask5[31 : 12] = pci_am5 ;
|
2810 |
|
|
assign pci_tran_addr0[31 : 12] = pci_ta0 ;
|
2811 |
|
|
assign pci_tran_addr1[31 : 12] = pci_ta1 ;
|
2812 |
|
|
assign pci_tran_addr2[31 : 12] = pci_ta2 ;
|
2813 |
|
|
assign pci_tran_addr3[31 : 12] = pci_ta3 ;
|
2814 |
|
|
assign pci_tran_addr4[31 : 12] = pci_ta4 ;
|
2815 |
|
|
assign pci_tran_addr5[31 : 12] = pci_ta5 ;
|
2816 |
|
|
assign pci_img_ctrl0[2 : 1] = pci_img_ctrl0_bit2_1 ;
|
2817 |
|
|
assign pci_img_ctrl1[2 : 1] = pci_img_ctrl1_bit2_1 ;
|
2818 |
|
|
assign pci_img_ctrl2[2 : 1] = pci_img_ctrl2_bit2_1 ;
|
2819 |
|
|
assign pci_img_ctrl3[2 : 1] = pci_img_ctrl3_bit2_1 ;
|
2820 |
|
|
assign pci_img_ctrl4[2 : 1] = pci_img_ctrl4_bit2_1 ;
|
2821 |
|
|
assign pci_img_ctrl5[2 : 1] = pci_img_ctrl5_bit2_1 ;
|
2822 |
|
|
// PCI output from pci error control and status register
|
2823 |
|
|
assign pci_error_en = pci_err_cs_bit0 ;
|
2824 |
|
|
assign pci_error_sig_set = pci_err_cs_bit8 ;
|
2825 |
|
|
assign pci_error_rty_exp_set = pci_err_cs_bit10 ;
|
2826 |
|
|
// WISHBONE output from image registers
|
2827 |
|
|
assign wb_base_addr0[31 : 12] = wb_ba0_bit31_12 ;
|
2828 |
|
|
assign wb_base_addr1[31 : 12] = wb_ba1_bit31_12 ;
|
2829 |
|
|
assign wb_base_addr2[31 : 12] = wb_ba2_bit31_12 ;
|
2830 |
|
|
assign wb_base_addr3[31 : 12] = wb_ba3_bit31_12 ;
|
2831 |
|
|
assign wb_base_addr4[31 : 12] = wb_ba4_bit31_12 ;
|
2832 |
|
|
assign wb_base_addr5[31 : 12] = wb_ba5_bit31_12 ;
|
2833 |
|
|
assign wb_memory_io0 = wb_ba0_bit0 ;
|
2834 |
|
|
assign wb_memory_io1 = wb_ba1_bit0 ;
|
2835 |
|
|
assign wb_memory_io2 = wb_ba2_bit0 ;
|
2836 |
|
|
assign wb_memory_io3 = wb_ba3_bit0 ;
|
2837 |
|
|
assign wb_memory_io4 = wb_ba4_bit0 ;
|
2838 |
|
|
assign wb_memory_io5 = wb_ba5_bit0 ;
|
2839 |
|
|
assign wb_addr_mask0[31 : 12] = wb_am0 ;
|
2840 |
|
|
assign wb_addr_mask1[31 : 12] = wb_am1 ;
|
2841 |
|
|
assign wb_addr_mask2[31 : 12] = wb_am2 ;
|
2842 |
|
|
assign wb_addr_mask3[31 : 12] = wb_am3 ;
|
2843 |
|
|
assign wb_addr_mask4[31 : 12] = wb_am4 ;
|
2844 |
|
|
assign wb_addr_mask5[31 : 12] = wb_am5 ;
|
2845 |
|
|
assign wb_tran_addr0[31 : 12] = wb_ta0 ;
|
2846 |
|
|
assign wb_tran_addr1[31 : 12] = wb_ta1 ;
|
2847 |
|
|
assign wb_tran_addr2[31 : 12] = wb_ta2 ;
|
2848 |
|
|
assign wb_tran_addr3[31 : 12] = wb_ta3 ;
|
2849 |
|
|
assign wb_tran_addr4[31 : 12] = wb_ta4 ;
|
2850 |
|
|
assign wb_tran_addr5[31 : 12] = wb_ta5 ;
|
2851 |
|
|
assign wb_img_ctrl0[2 : 0] = wb_img_ctrl0_bit2_0 ;
|
2852 |
|
|
assign wb_img_ctrl1[2 : 0] = wb_img_ctrl1_bit2_0 ;
|
2853 |
|
|
assign wb_img_ctrl2[2 : 0] = wb_img_ctrl2_bit2_0 ;
|
2854 |
|
|
assign wb_img_ctrl3[2 : 0] = wb_img_ctrl3_bit2_0 ;
|
2855 |
|
|
assign wb_img_ctrl4[2 : 0] = wb_img_ctrl4_bit2_0 ;
|
2856 |
|
|
assign wb_img_ctrl5[2 : 0] = wb_img_ctrl5_bit2_0 ;
|
2857 |
|
|
// WISHBONE output from wb error control and status register
|
2858 |
|
|
assign wb_error_en = wb_err_cs_bit0 ;
|
2859 |
|
|
assign wb_error_sig_set = wb_err_cs_bit10_8[8] ;
|
2860 |
|
|
assign wb_error_rty_exp_set = wb_err_cs_bit10_8[10] ;
|
2861 |
|
|
// GENERAL output from conf. cycle generation register & int. control register
|
2862 |
|
|
assign config_addr[23 : 0] = { cnf_addr_bit23_2, 1'b0, cnf_addr_bit0 } ;
|
2863 |
|
|
assign icr_soft_res = icr_bit31 ;
|
2864 |
|
|
assign serr_int_en = icr_bit3_0[3] ;
|
2865 |
|
|
assign perr_int_en = icr_bit3_0[2] ;
|
2866 |
|
|
assign error_int_en = icr_bit3_0[1] ;
|
2867 |
|
|
assign int_prop_en = icr_bit3_0[0] ;
|
2868 |
|
|
|
2869 |
|
|
|
2870 |
|
|
endmodule
|
2871 |
|
|
|