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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Simple Small VGA IP Core                                    ////
////                                                              ////
////  This file is part of the Simple Small VGA project           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  512 entry FIFO for storing line video data. It uses one     ////
////  clock for reading and writing.                              ////
////                                                              ////
////  To Do:                                                      ////
////   Nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2001/10/02 15:33:33  mihad
// New project directory structure
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
module ssvga_fifo(
        clk, rst, dat_i, wr_en, rd_en,
        dat_o, full, empty, ssvga_en
);
 
//
// I/O ports
//
input                   clk;            // Clock
input                   rst;            // Reset
input   [31:0]   dat_i;          // Input data
input                   wr_en;          // Write enable
input                   rd_en;          // Read enable
output  [7:0]    dat_o;          // Output data
output                  full;           // Full flag
output                  empty;          // Empty flag
input           ssvga_en ;  // vga enable
 
//
// Internal wires and regs
//
reg     [7:0]            wr_ptr;             // Write pointer
reg     [7:0]            wr_ptr_plus1;   // Write pointer
reg     [9:0]            rd_ptr;             // Read pointer
reg     [9:0]            rd_ptr_plus1;   // Read pointer plus1
wire                    rd_en_int;          // FIFO internal read enable
 
//
// Write pointer + 1
//
 
always @(posedge clk or posedge rst)
    if (rst)
                wr_ptr_plus1 <= #1 8'b0000_0001 ;
    else if (~ssvga_en)
        wr_ptr_plus1 <= #1 8'b0000_0001 ;
        else if (wr_en)
                wr_ptr_plus1 <= #1 wr_ptr_plus1 + 1;
 
//
// Write pointer
//
always @(posedge clk or posedge rst)
        if (rst)
                wr_ptr <= #1 8'b0000_0000;
    else if (~ssvga_en)
        wr_ptr <= #1 8'b0000_0000;
        else if (wr_en)
                wr_ptr <= #1 wr_ptr_plus1 ;
 
//
// Read pointer
//
always @(posedge clk or posedge rst)
        if (rst)
                rd_ptr <= #1 10'b00_0000_0000;
    else if (~ssvga_en)
        rd_ptr <= #1 10'b00_0000_0000;
        else if (rd_en_int)
                rd_ptr <= #1 rd_ptr_plus1 ;
 
always @(posedge clk or posedge rst)
        if (rst)
                rd_ptr_plus1 <= #1 10'b00_0000_0001;
    else if (~ssvga_en)
        rd_ptr_plus1 <= #1 10'b00_0000_0001;
        else if (rd_en_int)
                rd_ptr_plus1 <= #1 rd_ptr_plus1 + 1 ;
 
//
// Empty is asserted when both pointers match
//
assign empty = ( rd_ptr == {wr_ptr, 2'b00} ) ;
 
//
// Full is asserted when both pointers match
// and wr_ptr did increment in previous clock cycle
//
assign full = ( wr_ptr_plus1 == rd_ptr[9:2] ) ;
 
wire valid_pix = 1'b1 ;
 
//
// Read enable for FIFO
//
assign rd_en_int = rd_en & !empty & valid_pix;
 
wire [8:0] ram_pix_address = rd_en_int ? {rd_ptr_plus1[9:2], rd_ptr_plus1[0]} : {rd_ptr[9:2], rd_ptr[0]} ;
 
wire [7:0] dat_o_low ;
wire [7:0] dat_o_high ;
 
assign dat_o = rd_ptr[1] ? dat_o_high : dat_o_low ;
 
RAMB4_S8_S16 ramb4_s8_0(
        .CLKA(clk),
        .RSTA(rst),
        .ADDRA(ram_pix_address),
        .DIA(8'h00),
        .ENA(1'b1),
        .WEA(1'b0),
        .DOA(dat_o_low),
 
        .CLKB(clk),
        .RSTB(rst),
        .ADDRB(wr_ptr),
        .DIB(dat_i[15:0]),
        .ENB(1'b1),
        .WEB(wr_en),
        .DOB()
);
 
RAMB4_S8_S16 ramb4_s8_1(
        .CLKA(clk),
        .RSTA(rst),
        .ADDRA(ram_pix_address),
        .DIA(8'h00),
        .ENA(1'b1),
        .WEA(1'b0),
        .DOA(dat_o_high),
 
        .CLKB(clk),
        .RSTB(rst),
        .ADDRB(wr_ptr),
        .DIB(dat_i[31:16]),
        .ENB(1'b1),
        .WEB(wr_en),
        .DOB()
);
 
endmodule

Line No.	Rev	Author	Line
1	2	mihad	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Simple Small VGA IP Core ////`
4			`//// ////`
5			`//// This file is part of the Simple Small VGA project ////`
6			`//// ////`
7			`//// ////`
8			`//// Description ////`
9			`//// 512 entry FIFO for storing line video data. It uses one ////`
10			`//// clock for reading and writing. ////`
11			`//// ////`
12			`//// To Do: ////`
13			`//// Nothing ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Damjan Lampret, lampret@opencores.org ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48	21	mihad	`// Revision 1.1.1.1 2001/10/02 15:33:33 mihad`
49			`// New project directory structure`
50	2	mihad	`//`
51	21	mihad	`//`
52	2	mihad
53			`// synopsys translate_off`
54			`include "timescale.v"
55			`// synopsys translate_on`
56
57			`module ssvga_fifo(`
58	21	mihad	`clk, rst, dat_i, wr_en, rd_en,`
59	2	mihad	`dat_o, full, empty, ssvga_en`
60			`);`
61
62			`//`
63			`// I/O ports`
64			`//`
65			`input clk; // Clock`
66			`input rst; // Reset`
67			`input [31:0] dat_i; // Input data`
68			`input wr_en; // Write enable`
69			`input rd_en; // Read enable`
70			`output [7:0] dat_o; // Output data`
71			`output full; // Full flag`
72			`output empty; // Empty flag`
73			`input ssvga_en ; // vga enable`
74
75			`//`
76			`// Internal wires and regs`
77			`//`
78			`reg [7:0] wr_ptr; // Write pointer`
79			`reg [7:0] wr_ptr_plus1; // Write pointer`
80			`reg [9:0] rd_ptr; // Read pointer`
81			`reg [9:0] rd_ptr_plus1; // Read pointer plus1`
82			`wire rd_en_int; // FIFO internal read enable`
83
84			`//`
85			`// Write pointer + 1`
86			`//`
87
88			`always @(posedge clk or posedge rst)`
89			`if (rst)`
90			`wr_ptr_plus1 <= #1 8'b0000_0001 ;`
91			`else if (~ssvga_en)`
92			`wr_ptr_plus1 <= #1 8'b0000_0001 ;`
93			`else if (wr_en)`
94			`wr_ptr_plus1 <= #1 wr_ptr_plus1 + 1;`
95
96			`//`
97			`// Write pointer`
98			`//`
99			`always @(posedge clk or posedge rst)`
100			`if (rst)`
101			`wr_ptr <= #1 8'b0000_0000;`
102			`else if (~ssvga_en)`
103			`wr_ptr <= #1 8'b0000_0000;`
104			`else if (wr_en)`
105			`wr_ptr <= #1 wr_ptr_plus1 ;`
106
107			`//`
108			`// Read pointer`
109			`//`
110	21	mihad	`always @(posedge clk or posedge rst)`
111	2	mihad	`if (rst)`
112			`rd_ptr <= #1 10'b00_0000_0000;`
113	21	mihad	`else if (~ssvga_en)`
114	2	mihad	`rd_ptr <= #1 10'b00_0000_0000;`
115			`else if (rd_en_int)`
116			`rd_ptr <= #1 rd_ptr_plus1 ;`
117
118	21	mihad	`always @(posedge clk or posedge rst)`
119	2	mihad	`if (rst)`
120			`rd_ptr_plus1 <= #1 10'b00_0000_0001;`
121	21	mihad	`else if (~ssvga_en)`
122	2	mihad	`rd_ptr_plus1 <= #1 10'b00_0000_0001;`
123			`else if (rd_en_int)`
124			`rd_ptr_plus1 <= #1 rd_ptr_plus1 + 1 ;`
125
126			`//`
127			`// Empty is asserted when both pointers match`
128			`//`
129	21	mihad	`assign empty = ( rd_ptr == {wr_ptr, 2'b00} ) ;`
130	2	mihad
131			`//`
132			`// Full is asserted when both pointers match`
133			`// and wr_ptr did increment in previous clock cycle`
134			`//`
135	21	mihad	`assign full = ( wr_ptr_plus1 == rd_ptr[9:2] ) ;`
136	2	mihad
137			`wire valid_pix = 1'b1 ;`
138
139			`//`
140			`// Read enable for FIFO`
141			`//`
142			`assign rd_en_int = rd_en & !empty & valid_pix;`
143
144			`wire [8:0] ram_pix_address = rd_en_int ? {rd_ptr_plus1[9:2], rd_ptr_plus1[0]} : {rd_ptr[9:2], rd_ptr[0]} ;`
145
146			`wire [7:0] dat_o_low ;`
147			`wire [7:0] dat_o_high ;`
148
149			`assign dat_o = rd_ptr[1] ? dat_o_high : dat_o_low ;`
150
151			`RAMB4_S8_S16 ramb4_s8_0(`
152	21	mihad	`.CLKA(clk),`
153	2	mihad	`.RSTA(rst),`
154			`.ADDRA(ram_pix_address),`
155			`.DIA(8'h00),`
156			`.ENA(1'b1),`
157			`.WEA(1'b0),`
158			`.DOA(dat_o_low),`
159
160			`.CLKB(clk),`
161			`.RSTB(rst),`
162			`.ADDRB(wr_ptr),`
163			`.DIB(dat_i[15:0]),`
164			`.ENB(1'b1),`
165			`.WEB(wr_en),`
166			`.DOB()`
167			`);`
168
169			`RAMB4_S8_S16 ramb4_s8_1(`
170	21	mihad	`.CLKA(clk),`
171	2	mihad	`.RSTA(rst),`
172			`.ADDRA(ram_pix_address),`
173			`.DIA(8'h00),`
174			`.ENA(1'b1),`
175			`.WEA(1'b0),`
176			`.DOA(dat_o_high),`
177
178			`.CLKB(clk),`
179			`.RSTB(rst),`
180			`.ADDRB(wr_ptr),`
181			`.DIB(dat_i[31:16]),`
182			`.ENB(1'b1),`
183			`.WEB(wr_en),`
184			`.DOB()`
185			`);`
186
187			`endmodule`

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[/] [pci/] [tags/] [rel_10/] [apps/] [crt/] [rtl/] [verilog/] [ssvga_fifo.v] - Blame information for rev 125