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//////////////////////////////////////////////////////////////////////
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//// ////
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//// File name: pci_target32_clk_en.v ////
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//// ////
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//// This file is part of the "PCI bridge" project ////
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//// http://www.opencores.org/cores/pci/ ////
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//// ////
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//// Author(s): ////
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//// - Tadej Markovic, tadej@opencores.org ////
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//// ////
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//// All additional information is avaliable in the README.txt ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2001/10/05 08:14:30 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// New project directory structure
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//
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//
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// module is used to separate logic which uses criticaly constrained inputs from slower logic.
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// It is used to synthesize critical timing logic separately with faster cells or without optimization
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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module PCI_TARGET32_CLK_EN
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(
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addr_phase,
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config_access,
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addr_claim_in,
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pci_frame_in,
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state_wait,
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state_transfere,
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state_default,
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clk_enable
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);
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input addr_phase ; // indicates registered address phase on PCI bus
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input config_access ; // indicates configuration access
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input addr_claim_in ; // indicates claimed input PCI address
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input pci_frame_in ; // critical constrained input signal
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input state_wait ; // indicates WAIT state of FSM
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input state_transfere ; // indicates TRANSFERE state of FSM
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input state_default ; // indicates DEFAULT state of FSM
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output clk_enable ; // FSM clock enable output
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// clock enable signal when FSM is in IDLE state
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wire s_idle_clk_en = ((addr_phase && config_access) ||
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(addr_phase && ~config_access && addr_claim_in)) ;
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// clock enable signal when FSM is in WAIT state or in DEFAULT state
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wire s_wait_clk_en = (state_wait || state_default) ;
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// clock enable signal when FSM is in TRANSFERE state
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wire s_tran_clk_en = (state_transfere && pci_frame_in) ;
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// Clock enable signal for FSM with preserved hierarchy for minimum delay!
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assign clk_enable = (s_idle_clk_en || s_wait_clk_en || s_tran_clk_en) ;
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endmodule
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